JP2000066903A - Interrupt processing system and interrupt processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load of timer resetting processing due to an interval timer interrupt event by providing a timer designation table having information showing a timer counter performing updation next. SOLUTION: A timer processing means 102 is used at the time of performing processing execution of an interval timer interrupt event 113. The timer processing means 102 consists of a timer selecting means which selects a timer to be processed in interval timer interrupt processing, plural timers which decrement timer values corresponding to respective timers in every processing and a timer designation table 103 which designates a timer to be next processed. The table 103 generates a cyclic integer (i) for dispatch processing. When an interval timer interrupt occurs, the main processing part of this system enters timer interrupt processing and the processing of only one timer selected according to the integer (i) is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing system, and more particularly, to a load of timer interrupt processing by an interval timer interrupt event in a processing program (hereinafter, also referred to as "embedded software") using a plurality of soft timers simultaneously. The present invention relates to a system capable of alleviating the problem.

[0002]

2. Description of the Related Art Conventionally, a problem of a processor that accepts a plurality of interrupt requests including an interval timer interrupt event is that a plurality of interrupt requests for real-time processing occur frequently at the same time.
Of course, some jobs that have generated an interrupt event are designed to enter the standby state when notified that the interrupt request is not accepted, but some jobs require a real-time interrupt. Some have the character that

Therefore, even when designing embedded software, it is one of the most important factors to consider the time required for individual interrupt processing and the total thereof. Here, even in a method in which resetting of various timers in which a timeout occurs is collectively processed by, for example, periodic interrupt processing, a job to be processed by the interrupt may be a job that may take a long time. In some cases, for example, when the embedded software uses a plurality of timers at the same time, the total processing time required for resetting the timers when all or some of the plurality of timers simultaneously time out is determined. Need to be taken into account.

When a technology belonging to this field is retrospectively investigated from past patent applications, Japanese Patent Application Laid-Open No. 7-219784 discloses an invention called "interrupt control system". The present invention
The first interval timer interrupt event occurs while the control unit that controls the interval timer interrupt event and the normal interrupt event is already accepting one interrupt request and processing it with the processor that processes the interrupt request. Then, this is stored in a reception table, and an interrupt request is continuously asserted to the processor. If a second interval timer interrupt event occurs during this time, the processor that generated the event is A technique for notifying that the event is in an unacceptable state is disclosed.

[0005]

However, in the case of a system requiring a large number of timers for the above reasons,
In some situations, the processing time of the processor is significantly increased, which limits the number of timers that can be processed simultaneously. Therefore, a system and method for efficiently setting the timer and maximizing the capacity of the processor are needed.

Generally, a system having interrupt processing means as shown in FIG. 4, that is, one processor (40
In 1), the system that processes a plurality of interrupt events (411 to 413) compiled by the OR logic circuit (402) captures the interrupt events without fail regardless of the timing of each of the interrupt events. It is configured on the premise that the processing is performed by.
However, in a system having an interrupt processing method as shown in FIG. 5, that is, a system having a timer process (502) for controlling a plurality of timers (503 to 506) with one interval timer interrupt event (413), some If these timers have timed out at the same time, it may take a long processing time to reset them, and the other interrupt events (411, 412) occurring during this processing time may be overlooked. There was a problem that this could not be imported.

[0007] In some cases, at the timing when the processing of the first interval timer interrupt event is not completed, the second and subsequent interval timer interrupt events may occur and the system may enter a standby state. The processing performed by
In addition to resetting the timer that has timed out, for example, processing that requires a new setting of the timer from the current time, that is, interrupt processing that does not allow delay is also included. Occurrence of the condition, although often a cause of failure, has been one of the difficult problems to solve.

[0008] In devising the present invention, it has been considered that, as a minimum, a situation in which an interrupt request that does not necessarily need to be processed in real time affects an interrupt request that needs to be processed in real time should be avoided. .

Therefore, the processing required by an interrupt request that does not necessarily need to be processed in real time
Reduction of the processing time was studied, and a method of reducing the processing time for one interrupt request and distributing the load to a plurality of interrupt requests was studied.

As an interrupt request for which such a method should be adopted, an interval timer interrupt event for resetting the above-mentioned time-out timer has been extracted.

The technique disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 7-219784 does not essentially solve the above-mentioned problem that occurs when real-time interrupt requests occur frequently. This is because the second and subsequent interrupt requests generated during the processing of a certain interrupt request are forced to wait.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems in the conventional interrupt processing method, and an interrupt capable of reducing the load of timer reset processing due to an interval timer interrupt event of embedded software. It is an object to provide a processing system.

[0013]

According to the present invention, there is provided a system for accepting both a timer interrupt and a normal interrupt, comprising: a plurality of timer counters for counting the number of accepted timer interrupts; A timer specification table having information indicating a timer counter to be updated next among a plurality of timer counters, and, when a timer interrupt is accepted, referring to information included in the timer specification table to perform an update next to the plurality of timer counters Selecting means for selecting a timer counter; changing means for changing a value of the timer counter selected by the selecting means to a predetermined value; and a value of a counter of the timer counter changed by the changing means, the value of which is a predetermined value. When the condition is satisfied, perform the interrupt processing performed when the timer counter times out. Providing means, a timer specifying table, the interrupt process distribution system including a updating means for updating the information indicating the timer counter which is different from the timer counter.

In the above-mentioned distributed interrupt processing system, each of the plurality of timer counters has a predetermined initial value and means for changing the value of the timer counter to an initial value corresponding to the timer counter at the end of the processing means. Further provisions are possible.

Further, in the above interrupt distribution system, each of the plurality of timer counters further has a predetermined processing order, and the updating means refers to the processing order of each of the plurality of timer counters. Means for changing the timer designation table to information indicating a timer counter next to the timer counter processed by the processing means.

In addition, in a system that accepts both a timer interrupt and a normal interrupt, when a timer interrupt is accepted, a timer designation table having information indicating a timer counter to be updated next among a plurality of timer counters is referred to. A selecting step of selecting a timer counter to be updated next; a changing step of adding a predetermined value to the value of the timer counter selected by the selecting step; Provided is a method for distributing interrupt processing, comprising: a processing step of performing an interrupt processing performed when a timer counter times out when a value is satisfied; and an updating step of updating a timer designation table with information indicating a timer counter different from the timer counter. .

In the above-mentioned interrupt processing distribution method, a step of giving a predetermined initial value to each of the plurality of timer counters in advance and a step of changing the value of the timer counter to a corresponding initial value at the end of the above-mentioned processing steps And can be further provided.

Further, in the above interrupt distribution method, the method further comprises the step of giving a predetermined processing order to each of the plurality of timer counters, and the updating step includes the step of changing the processing order of each of the plurality of timer counters. And changing the timer designation table to information indicating a timer counter next to the timer counter processed in the processing step.

Still further, in a system for accepting both a timer interrupt and a normal interrupt, a step of previously securing a plurality of timer counters for counting the number of accepted timer interrupts, and a timer for updating the next one of the plurality of timer counters A step of securing a timer designation table having information indicating the counter in advance, and a step of selecting a timer counter to be updated next among the plurality of timer counters with reference to the information contained in the timer designation table when accepting a timer interrupt A changing step of adding a predetermined value to the value of the timer counter selected in the selecting step; and performing a time-out operation of the timer counter when the value of the timer counter changed in the changing step satisfies a predetermined value. Processing routine to perform interrupt processing And-up, the timer specification table,
An update step of updating to information indicating a timer different from a timer counter, and a recording medium recording a program for executing the update step.

Further, in the above-mentioned recording medium, a step of giving a predetermined initial value to each of the plurality of timer counters in advance, and an initialization of initializing the value of the timer counter to a corresponding initial value at the end of the above processing steps Steps and
Can be further recorded.

Further, the above-mentioned recording medium further comprises a step of giving a predetermined processing order to each of the plurality of timer counters, and the updating step refers to the processing order of each of the plurality of timer counters. In addition, a configuration may be adopted in which a program for executing a step of changing the timer designation table is recorded in information indicating a timer counter in the next order of the timer counter processed in the processing step.

Hereinafter, the operation of the present invention will be described. The interrupt processing method of the processing program according to the present invention, the timer management processing by the interrupt processing in the embedded software that uses a plurality of soft timers simultaneously, with one interrupt,
It is a method that is always performed for only one timer.

That is, in the interrupt processing method of the processing program according to the present invention, as shown in the flowchart of FIG. 3, an interrupt processing operation is performed so that only one timer is processed by one interval timer interrupt event. This prevents multiple timers from timing out simultaneously at the interval timer interrupt.

Naturally, it can be considered that the interval of the interval timer interrupt is set to be shorter than that of the conventional system.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic diagram of a hardware configuration of an interrupt processing system according to a first embodiment of the present invention.

A plurality of interrupt events (111 to 11)
A selection unit (106) for selecting 3) and a selection unit (106)
And a process execution unit (101) for executing the process of the interrupt event selected by the user. The processing execution unit (101) includes a timer processing unit (102), and the timer processing unit (102) has a timer processing table (103). This timer processing means (10
2) is an interval timer interrupt event (11
It is used when the processing of 3) is executed. The device (10
The program can be read from the recording medium (105) via 4), and the processing execution unit (101) has a function of executing the read program.

FIG. 2 is a flowchart showing the operation of the interrupt processing system according to the first embodiment of the present invention. FIG. 2A shows a flowchart of a main process (231) for performing main control of the system, which is performed in the process execution unit (101). FIG. 2B shows the processing execution unit (101).
4 shows a flowchart of an interrupt process 1 (201) corresponding to the interrupt event 1 (111) input to the CPU. FIG. 2C illustrates an interrupt process 2 (21) corresponding to the interrupt event 2 (112) input to the process execution unit (101).
The flowchart of 1) is shown. FIG. 2D shows a timer interrupt process (2) corresponding to the interval timer interrupt event (113) input to the process execution unit (101).
21 shows a flowchart of 21).

FIG. 3 is a flowchart showing the operation of the timer selection mechanism in the timer processing means (102) of the interrupt processing system according to the first embodiment of the present invention. The timer processing means (102) shown in FIG. 3 includes a timer selection means (302) for selecting a timer to be processed in the interval timer interrupt processing, and a timer for decrementing a timer value corresponding to each timer for each processing. 1 to timer n (303 to 306) and a timer designation table (10
3).

According to the present embodiment, software for executing the processing shown in the flowcharts shown in FIGS. 2 and 3 is provided. However, this part does not necessarily have to be implemented as software, and may be implemented as hardware.

An example of the configuration according to the present embodiment will be described below.
In FIG. 1, a plurality of interrupt events (111 to 113) for activating a process are collected by a selection unit (106) including an OR logic circuit and input to a process execution unit (101) having a processor. Such a system is generally controlled by operations shown in flowcharts as shown in FIGS. FIG.
The system showing the operations shown in the flowcharts of (a) to (d) performs a main process (23) for performing main control of the system.
1), interrupt processing 1 (201) corresponding to interrupt event 1 (111), and interrupt event 2 (11).
It comprises an interrupt process 2 (211) corresponding to 2) and a timer interrupt process (221) corresponding to the interval timer interrupt event (113).

FIG. 3 is a block diagram showing the operation of the timer selecting mechanism in the timer processing section. The timer selecting means (302) for performing a dispatch process for selecting a timer to be processed by the interval timer interrupt corresponds to each of them. Timer 1 that decrements the set timer value for each process
Timer n (303 to 306) and a timer designation unit (311) including a timer designation table (103) for generating a cyclic integer i for dispatch processing.

The method of dispatch processing performed by the timer selecting means (302) may be such that, for example, timer 1 to timer n (303 to 306) are selected based on the result of decoding the integer i.

Further, the routine addresses of the timers 1 to n are stored in the respective entries of the table, and instead of using the dispatch processing, a pointer pointing to the entry of the table is set, and the integer i is set. Is set in the pointer, and the table origin is added, and the contents of the entry of the table corresponding to the integer i are referred to, whereby the timer i can be called.

Next, with reference to FIGS. 1, 2, and 3, the operation of the interrupt processing system according to the present embodiment will be described with reference to the following example.

When the main processing section (231) of the system uses a timer, a timer value corresponding to a desired timer is set. Here, when an interval timer interrupt occurs, the timer interrupt processing starts and the timer processing unit (22
2) is called. In the timer processing unit (222), the processing of only one timer selected by the value of the cyclic integer i is performed.

The timers 1 to n (303 to 306) check the timer values of the timers 1 to n (303 to 306), respectively. If the result of the decrement is 0, a timeout is returned to the main processing. Next, the value of the integer i is updated by the timer specification unit (311), and the timer specification table (1) is updated.
03), and terminates the timer interrupt processing. The timer designation unit (311) cyclically changes the value of i used for dispatch processing within an integer range from 1 to n, and stores the value of i in the timer designation table (103).

A specific operation example will be described below. Now, it is assumed that the main process of the system sets 9 as the timer value for the timer 1 (303). Thereafter, when an interval timer interrupt occurs 2n times, the timer 1 is processed twice in the timer processing unit (222), and the timer value becomes 7. Here, if the main process sets the timer value of the timer 2 (304) to 7, the timer values of the timer 1 and the timer 2 are both 7. When the timer value of the timer 3 (305) is set to 2 when the interval timer interrupt is further generated 5n times, the timer 1 (303)
The timer value of both the timer 2 (304) and the timer 3 (305) becomes 2.

Subsequently, the interval timer interrupt is n +
When this occurs once, the timer value of the timer 1 (303) becomes 0, and a timeout is returned to the main processing. Similarly, timer 2 (304) is n + 2 times, and timer 3 (305) is n
A timeout is returned to the main processing by +3 interval timer interrupts. Assuming that an interrupt event 1 (111) occurs when the timer 1 (303) times out, an interrupt process 1 (201) is performed before the process for the timer 2 (304) to time out.

When the timer selection algorithm corresponding to the occurrence of the interval timer interrupt event of the interrupt processing method according to the present invention is generalized, the n-th interval counting from the processing start time for the n timers in the processor Until the timer interrupt event occurs,
Any one of the n timers is selected, and for any one of the n timers, the timer is counted from the time immediately after the selection of the timer, and the n-th timer is counted. The algorithm is repeatedly selected upon the occurrence of the interval timer interrupt event.

That is, there is only a restriction that n timers are selected without duplication from the start of processing to the occurrence of the nth interval timer interrupt event, and the selection order is originally arbitrary. Yes, therefore, the order of timer selection from the start of processing to the occurrence of the n-th interval timer interrupt event is independent of the interrupt processing method according to the present invention, and takes into account other design factors in processing. It is also possible to determine.

In the above description, the selection without duplication means that the timer once selected is excluded from the next selection.

(Second Embodiment) The configuration and operation of the interrupt processing system according to the second embodiment of the present invention are the same as those of the interrupt processing system according to the first embodiment of the present invention. However, in the interrupt processing method according to the first embodiment, the processing target selected by the occurrence of one interval timer interrupt event is limited to one timer. In the interrupt processing method according to the embodiment, the selected processing target is a group of m (m <n) timers composed of a plurality of timers.

All the timers belonging to any one of the timer groups are sequentially processed by the occurrence of the above-mentioned interrupt event. That is, inside the processing unit for processing such a timer group, a configuration as shown in FIG. 5 is formed by the timers belonging to the timer group, and the processing for all the timers belonging to the timer group is performed. The required total processing time is estimated in advance.

As described above, in the conventional interrupt processing method in which processing of all the timers is performed at once when one interval timer interrupt event occurs, another interrupt event subsequently occurs at approximately the same time. However, in the worst case where the other interrupt event is released before the reset processing of all the timers that have timed out is completed, the occurrence of the interrupt event cannot be recognized. According to the interrupt processing method of the present invention, the time during which another simultaneous interrupt event is to be maintained is determined by the processing time required for one timer or the total processing time estimated in advance for a specific timer group. Since it is shortened, it is possible to recognize occurrence of the other interrupt event without omission.

[0046]

A first effect of the interrupt processing system according to the present invention is to eliminate a state where a plurality of timers time out simultaneously.

A second effect of the interrupt processing system according to the present invention is that it is possible to suppress the overload of the timer interrupt processing that occurs when the timeouts of a plurality of timers overlap.

Further, a third effect of the interrupt processing system according to the present invention is that it is possible to minimize competition with other interrupts.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram showing an operation environment of an entire system adopting an interrupt processing method according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the entire system employing the interrupt processing method according to the embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of a timer selection mechanism in a timer processing unit of an interrupt processing method according to the embodiment of the present invention.

FIG. 4 is a hardware configuration diagram showing an operation environment of an entire system employing an interrupt processing method according to a conventional technique.

FIG. 5 is a flowchart showing an operation of a timer selection mechanism in a timer processing unit of an interrupt processing system according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Process execution part 102 Timer processing means 103 Timer specification table 104 Device 105 Recording medium 106 Selection part 111 Interrupt event 1 112 Interrupt event 2 113 Interval timer interrupt event 201 Interrupt process 1 211 Interrupt process 2 221 Timer interrupt process 231 Main process 302 Timer Selection means 303 Timer 1 304 Timer 2 305 Timer 3 306 Timer n 311 Timer designator 401 Processor 402 OR logic circuit 411 Interrupt event 1 412 Interrupt event 2 413 Interval timer interrupt event 502 Timer processing 503 Timer 1 504 Timer 2 505 Timer 3 506 Timer n

Claims (9)

[Claims] 1. A system for accepting both a timer interrupt and a normal interrupt, comprising: a plurality of timer counters for counting the number of accepted timer interrupts; and information indicating a timer counter to be updated next among the plurality of timer counters. A timer designation table, a selection unit for selecting a timer counter to be updated next among the plurality of timer counters with reference to information held in the timer designation table when a timer interrupt is accepted, and a selection unit selected by the selection unit Changing means for changing a value of the timer counter by a predetermined value; and when the value of the counter included in the timer counter changed by the changing means satisfies a predetermined value, the change is performed when the timer counter times out. Processing means for performing interrupt processing, and the timer Updating means for updating the designated table with information indicating a timer counter different from the timer counter. 2. Each of the plurality of timer counters further comprises: a predetermined initial value; and means for changing the value of the timer counter to the initial value corresponding to the timer counter when the processing means ends. The interrupt processing system according to claim 1, further comprising: 3. Each of the plurality of timer counters further includes a predetermined processing order, and the updating unit refers to the processing order of each of the plurality of timer counters, and 3. The interrupt processing system according to claim 1, further comprising: means for changing the timer designation table to information indicating a timer counter next to the processed timer counter. 4. A system for accepting both a timer interrupt and a normal interrupt, wherein when the timer interrupt is accepted, the timer designation table having information indicating a timer counter to be updated next among a plurality of timer counters is referred to. A selecting step of selecting a timer counter to be updated, a changing step of adding a predetermined value to the value of the timer counter selected by the selecting step, and a changing step of the timer counter changed by the changing step. When the value satisfies a predetermined value, a processing step of performing an interrupt process performed when the timer counter times out; and an updating step of updating the timer designation table with information indicating a timer counter different from the timer counter. Interrupt handling method. 5. The method further comprising: providing a predetermined initial value to each of the plurality of timer counters in advance; and changing the value of the timer counter to the corresponding initial value at the end of the processing step. The interrupt processing method according to claim 4. 6. The method according to claim 6, further comprising: providing a predetermined processing order to each of the plurality of timer counters; and the updating step performs the processing by referring to the processing order of each of the plurality of timer counters. The interrupt processing method according to claim 4, further comprising: changing the timer designation table to information indicating a timer counter next to the timer counter processed in the step. 7. A system for accepting both a timer interrupt and a normal interrupt, a step of previously securing a plurality of timer counters for counting the number of accepted timer interrupts, and a timer counter for updating the next one of the plurality of timer counters Securing in advance a timer designation table having information indicating the following; and selecting a timer counter to be updated next among the plurality of timer counters with reference to the information possessed by the timer designation table when accepting a timer interrupt. A step of adding a predetermined value to the value of the timer counter selected by the selecting step, and when the value of the timer counter changed by the changing step satisfies a predetermined value, Performed when the timer counter times out A processing step of performing interrupt processing, the timer specification table, the timer counter different recording medium and the update step, recording a program for executing the updating of information indicating the timer. 8. A step of giving a predetermined initial value to each of the plurality of timer counters in advance, and an initializing step of initializing the value of the timer counter to the corresponding initial value at the end of the processing step. The recording medium according to claim 7, further comprising a program to be executed. 9. The method according to claim 9, further comprising: providing a predetermined processing order to each of the plurality of timer counters; and the updating step performs the processing by referring to the processing order of each of the plurality of timer counters. 9. The recording medium according to claim 7, wherein a program for executing the step of: changing the timer designation table to information indicating a timer counter in the next order of the timer counter processed by the step is recorded.