JP2000066897A - Device and method for generating object - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for generating object with which a parameter can be efficiently allocated to a register in optimum manner by coloring. SOLUTION: When one register can be accessed as plural registers of small size, an interference graph and a stack for storing the apex of an interference graph based on this interference graph are generated and from this stack, the interference graph is reconstituted based on a coloring algorithm. Then, it is judged whether each apex can be piled on the stack or not while referring to information showing the correspondence of each apex and the usable register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an object generating apparatus and an object generating method, and more particularly to an object generating apparatus and an object generating method capable of optimally and efficiently allocating variables to registers by coloring. is there.

[0002]

2. Description of the Related Art A typical algorithm for register allocation is coloring (coloring method). The main algorithm of coloring first creates an interference graph for all variables. Next, the vertices (variables) whose frequency (the number of all variables interfering with the variable) is less than k from the interference graph
Are sequentially removed, and are stacked (stack push). Here, k is the total number of available registers of the target machine (ie, microprocessor, etc.).
When all the variables are put on the stack and the graph becomes empty, the variables are sequentially fetched from the stack (stack pop) to re-create the interference graph. At this time, each vertex (variable) is painted in a different color from all other interfering vertices (variables). This is to assign that variable to a register. When all the vertices are removed from the stack and the original interference graph can be reproduced, the register assignment is completed.

The first problem here is that there is a non-deterministic point. That is, in what order the vertices are selected from the interference graph, and how to color the vertices extracted from the stack. For these, it is possible to paint a desired color (assign a register) to some extent by using various rules, but since they are not directly related to the present invention, they are omitted here.

[0004] The next problem is that the algorithm cannot be continued during coloring. In an actual target machine, since the number k of available registers is finite, if the frequency of all vertices of the interference graph becomes larger than k, coloring can no longer be continued. In such a case, a spill-out process is performed.

[0005] The second problem is that the value of k is not determined in actual register allocation. Naturally, the upper limit of k is the total number of registers of the target machine, but for each variable, various restrictions are imposed on code generation,
The number and types of registers that can be assigned to each variable vary. In such a case, for each variable,
Processing is performed by providing the number of registers (maximum frequency) that can be used.

[0006] There are various literatures on the detailed algorithm of coloring, and the details are well known. For example, a book on compilers (co-authored by Aho, Sethi and Ullman, translated by Harada, Compiler Science, ISBN4-7819-0586-
2, or see Sasa, "Programming Language Processing System", Iwanami Shoten, ISBN4-00-010345-8).

If the frequency of all vertices becomes larger than k during the process of stacking, no vertex can be selected, and the process cannot be continued. In such a case, one vertex is removed from the remaining graph. Abandon assigning this vertex to a register,
I will allocate it to memory. Thereby, the processing can be continued on the interference graph again. This is spill-out. As a result, when the vertex cannot be selected again, the processing can be continued by performing spill-out as needed.

[0008] Again, it is indeterminate which variable to select from the remaining interference graphs, but this is also not directly related to the present invention and will not be described.

Further, there is a problem that a code for a variable allocated to a memory may be incorrect due to spill-out, and that complete code generation may not be possible.

In such a case, it is necessary to cope with the problem by, after register allocation, inserting a correction code (spill code) for an illegal code and performing register allocation again.

In a normal compiler, there are restrictions on how to use registers and restrictions on code generation for each code, so that the number of registers that can be allocated to each variable varies. Therefore, when extracting each vertex from the interference graph, it is not realistic to compare k with the frequency of the vertex.

However, for each vertex, the number of registers to which the vertex can be allocated is preset as the maximum frequency, and at the stage of removing the vertex from the interference graph, a vertex whose frequency is less than the maximum frequency is selected. Thus, the processing can be continued. This is because an empty register can always be found when the vertex is taken out of the stack again and added to the interference graph.

The above algorithm is based on the assumption that one register is assigned to one variable as in the RICS processor. However, some target machines have a feature that one register can be accessed as a small-sized register, such as a CISC processor. That is, there is a case where one register can be accessed as a plurality of registers having a small size.

In such a case, the total number of registers (maximum frequency) that can be allocated to a variable having a small size apparently increases. However, the size of a variable that interferes with the variable (vertex) is generally disjoint, and the frequency of interference with a variable of a larger size apparently increases.

As one method, the conventional frequency and the maximum frequency are used, and the maximum frequency is the total number of registers that can be allocated counted by the size of the vertex, and the frequency is the size of a variable that interferes with the vertex. An alternative is to use the total number of values divided by the size.

However, registers that can be assigned to the vertex are limited by the type of instruction having the vertex as an operand. Due to this limitation, the conventional method using frequency and maximum frequency is not perfect. There is a risk of being unassignable or spilling out more than necessary.

[0017]

The problems associated with the above-mentioned conventional method will be described below in terms of the efficiency of a generated object and the compile time. The first is the efficiency of the generated object. In the conventional method, the decision whether to stack the stack is incomplete, so unnecessary spill-out may occur at the stage of creating the stack, or the interference graph is reproduced even though the stack can be emptied The problem of being unable to do so occurs.

When unnecessary spill-out occurs,
Code efficiency deteriorates due to increased memory access and insertion of spill codes. Also, if it becomes impossible to color while extracting the vertices from the stack and reproducing the interference graph, further spill out,
There is a need to avoid this by re-coloring from the beginning. As spillout increases, code efficiency naturally declines.

Next, a problem in terms of compile time will be described. In the conventional method, as described above, when the spill-out is performed more than necessary, the efficiency of the generated object code deteriorates. At the same time, additional processing such as inserting spill code is required in the compilation process,
Compilation speed is also reduced.

In general, since the time spent for register allocation in the processing of the compiler is large, if the compile speed is further reduced by spill-out, usability will be greatly impaired.

It is therefore an object of the present invention to provide an object generating apparatus and method capable of optimally and efficiently allocating variables to registers by coloring.

Another object of the present invention is to provide an object generating apparatus and method capable of generating objects (machine instructions) for reducing code size and execution time at high speed.

[0023]

According to the present invention, when one register can be accessed as a plurality of registers of a small size, a coloring algorithm is used.
An assignable register map is used as a condition for selecting a vertex to be stacked. This achieves the same generation object efficiency as in the case where one variable is assigned to one register.

In the conventional coloring, the comparison of whether or not the frequency is less than the maximum frequency when a certain vertex is removed from the interference graph is to ensure that there is always a space when the interference graph is recreated later. .

If this algorithm is applied when one register can be accessed as a plurality of registers of a small size, in order to guarantee that there is always room, the size of all vertices interfering with that vertex is Can be considered using a register map whose vertices can be used.

Consider the worst case where all the interfering vertices at that point in time fill the available register map in order to make room in the later step of removing that vertex from the stack and adding it to the interference graph. do it.

Since it is not clear in what order the current interference graph will be recreated later, consider the case where the register map is painted on the interfering vertices at that point in time.

As a result, when a vacancy remains in the available register map, the vertex can be selected.

That is, the present invention (claim 1) is an object generating apparatus for a target machine in which one register can be accessed as a plurality of registers having a small size. Means for generating an interference graph from a set of variables and arguments, and temporary variables used temporarily when translating the high-level language into machine instructions, and a stack for storing vertices of the interference graph based on the interference graph Means for reconstructing the interference graph from the stack based on a coloring algorithm, and means for generating information indicating the correspondence between each vertex and its available register, Is determined by referring to information in an available register of the vertex. To provide an object generating device.

Therefore, with such a configuration, the object generation apparatus according to the present invention can quickly and efficiently determine whether or not a certain vertex can be stacked.

According to the present invention (claim 2), in the coloring algorithm in the register allocation processing, whether or not a certain vertex can be stacked on the stack is determined using the frequency of the interfering vertex and an available register map. An object generation device according to claim 1 is provided.

Therefore, with such a configuration, the object generating apparatus according to the present invention determines whether or not a certain vertex can be stacked on the stack by using the frequency of the interfering vertex and an available register map. Provide an object generation method.

According to the present invention (claim 3), in the above-mentioned claim 2, the frequency for determining whether or not a certain vertex can be stacked on the stack can be used in the coloring algorithm in the register allocation processing. The structure of the register is classified, and the information includes information on which classification each of the vertices to interfere belongs to is provided.

Therefore, with such a configuration, the object generation device according to the present invention can reflect the configuration of the register of the processor targeted for the register allocation processing.

According to the present invention (claim 4), in the coloring algorithm in the register allocation processing, the determination as to whether a certain vertex can be stacked on the stack is made by using a register map of an available vertex that interferes with another vertex and a register map of that vertex. An object generating apparatus according to claim 2, wherein the object generating apparatus performs the processing using an available register map.

Therefore, with such a configuration, the object generating apparatus according to the present invention can more effectively determine whether or not a certain vertex can be stacked.

The present invention (claim 5) is a method for generating an object for a target machine in which one register can be accessed as a plurality of registers of a small size. Generating an interference graph from a set of arguments and temporary variables used temporarily when translating the high-level language into machine instructions, and generating a stack for storing vertices of the interference graph based on the interference graph And reconstructing the interference graph from the stack based on a coloring algorithm, and generating information indicating the correspondence between each vertex and its available register. The object is determined by referring to information in an available register of the vertex. To provide a-object generation method.

Therefore, with such a configuration, in the object generation method according to the present invention, it is possible to quickly and efficiently determine whether or not a certain vertex can be stacked.

According to the present invention (claim 6), in the coloring algorithm in the register allocation processing, whether or not a certain vertex can be stacked on the stack is determined using the frequency of the interfering vertex and an available register map. An object generation method according to claim 5 is provided.

Therefore, with such a configuration, in the object generation method according to the present invention, it is possible to more effectively determine whether or not a certain vertex can be stacked on the stack by considering the frequency of the interfering vertex.

According to the present invention (claim 7), in the above-mentioned claim 6, the frequency used for determining whether or not a certain vertex can be stacked on the stack in the coloring algorithm in the register allocation processing can be used. The structure of the register is classified, and the information includes information on which classification each of the vertices to interfere belongs to is provided.

Therefore, with such a configuration, the object generation method according to the present invention can reflect the configuration of the register of the processor targeted for the register allocation processing.

According to the present invention (claim 8), the coloring algorithm in the register allocation processing determines whether or not a certain vertex can be stacked on the stack by using a usable register map of another interfering vertex and a register map of that vertex. An object generation method according to claim 6, wherein the method is performed using an available register map.

Therefore, with such a configuration, in the object generation method according to the present invention, it is possible to more effectively determine whether or not a certain vertex can be stacked.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an object generating apparatus according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a hardware configuration of the object generating apparatus according to the present invention. That is, a computer 1 including an MPU for performing each processing described below, an internal storage unit (not shown) such as a hard disk device, an input unit such as a mouse 5 and a keyboard 6, and an output unit such as a monitor 7 and a printer 9. , And an external storage medium such as a CD-ROM 11 and a flexible disk 13 and a drive 15 for the external storage medium
Consists of These may use a general-purpose computer system. The MPU includes an operation unit that performs each process described below, and a main storage unit that stores instructions for the process.

FIG. 2 shows a configuration based on the processing flow of the compiler. The compiler is a software program that receives a source program described in a high-level language and generates an object code. Source programs such as C language go through a parser (lexical analysis, syntax analysis),
Converted to intermediate code. The intermediate code is converted into a machine language code by allocating registers after optimization, and is output as an object code through optimization again. FIG. 2 shows a configuration of a compiler that generates a code by converting a source program into an intermediate code, but there is also a compiler that generates a code. Here, there is a feature of the present invention in a portion that performs register allocation from the intermediate code. The process is summarized in FIG. Less than,
The contents will be explained step by step.

A feature of the present invention relates to a stack creating section. Until the interference graph of FIG. 3 is created, a brief description will be given below. Here TLCS-900 as a compiler
Take the example of a compiler targeting. Figure 5 shows the TLCS
The register configuration of -900 is shown. In the present invention, the stack pointer is omitted because it is not directly related.

Generally, a compiler converts a C language program as shown in FIG. 6 into an intermediate code as shown in FIG. 7 and processes it. Although the intermediate code itself is not optimized in FIG. 7, there is no problem in the explanation because the present invention is not related to the optimization of the intermediate code.

FIG. 8 shows whether each of the variables (the automatic variable I, the argument P, and the temporary variable T) overlaps in the live range based on the intermediate code shown in FIG. Call it a graph. For each variable in FIG. 8, the number in parentheses is the size of the register to be assigned to that variable (1,
2, 4 bytes). FIG. 9 is a set of registers that can be assigned to each variable, and is hereinafter referred to as an allocatable register map.

Here, the automatic variable I is a variable originally included in the source code of the high-level language, and the temporary variable T is a variable temporarily generated by the compiler when compiling. Needless to say, the automatic variable I is not limited to a variable in a narrow sense, but indicates a location (object) of a data area of a general memory. For example, an instance of a C ++ language class instance is also considered as a variable.

Next, a mounting method of the present invention will be described. Let G be the current interference graph. For a certain vertex x, it is determined whether or not the vertex can be stacked on the stack as follows. Here, a set of all vertices that interfere with the vertex x is assumed to be A. Assume that the size is known for all vertices, and that the register map available for all vertices is known. That is, they are obtained as preprocessing.

Usable register map for x
For all the elements of A with a register map of an equivalent size. In order to fill this method at the highest speed, A is further divided into A1 and A for each size.
2,. . . , An. However,
It is assumed that the size increases in order from A1. Therefore,
In the TLCS-900, processing is performed for each of four groups A1, A2, A3, and A4 (however, in the TLCS-900, there is no 3-byte variable set AB in specifications).

First, for each element (vertex) of An having the largest size, a register map of a corresponding size is used.
I will apply the map. In order to apply the map at the highest speed, the application is performed in such a manner that the percentage of the space in the map is large. That is, consider the worst situation.

When all elements of An have been completed,
In order, An-1,. . . , A2, and m for each element of A1
I will apply the ap. When there is no more space in the map on the way, it is determined that x can no longer be stacked on the stack, and the process ends. At the time when all elements (vertices) have been painted, if there is a space in the map, the vertex x can be stacked on the stack.

Hereinafter, an object generating apparatus according to a second embodiment of the present invention will be described with reference to the drawings. The above (1)
In the algorithm of (1), the register map that can be allocated is expressed by several kinds of maximum frequencies that characterize the register map, so that the algorithm (1) can be operated at high speed. As a result, a high-level compilation speed similar to the case where one variable is assigned to one register is realized.

Although the register map is generally represented by a bitmap, it takes time to paint the bitmap or search for a free bitmap. Because very fast processing is possible using simple arithmetic operations such as the conventional maximum frequency and frequency comparison, several types of maximum frequencies that represent register map information are introduced. Then, whether or not a certain vertex can be stacked on the stack is determined by the determination function f from the value of the frequency. This enables high-speed processing.

Next, a mounting method according to the present embodiment will be described. There is a set A of vertices that interfere with a certain vertex x, and the information of the set A is the number of elements for each size, that is, sets A1, A
2, A3,. . . , An, the number of elements, and the frequencies d1, d
2,. . . , Dn. The value of this frequency is
It should be updated appropriately when vertices are removed from the interference graph to create a stack.

The usable register map m of the vertex x
ap is represented by several types of maximum frequencies (m1, m2,... mi). At this time, whether the vertex x having the size j can be stacked on the stack is determined by an arithmetic function fj (d1, d2, ..., dn, m1, m
2, ..., mi). As described below, in the case of TLCS-900, N = 4 (however, d3 is not used), and i = 5 at the maximum.

The method of counting the maximum frequency and the method of determining the function f depend on the register configuration of the target machine. Each is non-deterministic, but for TLCS-900, it can be formulated as follows:

In the case of TLCS-900, the size is 1, 2,
There are three types of 4 bytes. Subscripts for these are denoted by 1, 2, and 4, respectively. First, the frequencies of the vertex x of the size j (j = 1, 2, 4) are d1, d2, and d4. Next, the maximum frequency for each vertex size is set as follows.

The usable register map in the case of j = 4 indicates whether XWA (or XBC or the like) can be used or not, and can be expressed only by whether there is a free space or no free space. Therefore, the maximum frequency can be represented by one type of m1 (= msingle).

The usable register map when j = 2 has two types, such as a case where both WA and QWA (or BC and QBC) can be used, and a case where QWA cannot be used but WA can be used. Conceivable. The pattern like the former is m2 (= mdouble), and the pattern like the latter is m1 (= ms
ingle).

When j = 1, the available register map can use three QA, W, A when four QW, QA, W, A (or QB, QC, B, C, etc.) can be used. If only QW cannot be used, QW and W can be used and Q
When A and A cannot be used, W and A can be used but QW and QA cannot be used, and when only A can be used, a total of five patterns can be considered. The maximum frequency for each pattern is m5 (= mquad), m4 (= mtriple), m3 (= mseparate), m2 (= mdou
ble) and m1 (= msingle).

The single, double, and separa related to the register map and the maximum frequency described above.
FIG. 16 is a conceptual diagram of te (separate), triple (triple), and quad (quad).

FIG. 10 shows the information obtained by replacing the information of the interfering vertices and the usable register map shown in FIGS. 8 and 7 with the frequency and the maximum frequency by the above setting method.

Next, the decision function f is formulated. When considering other vertices that interfere with vertex x of size j (j = 1, 2, 4), all vertices of a size smaller than that size have one free space of size j in the available register map of vertex x. The function f is formalized in consideration that it can be considered as the same frequency because it is possible to fill in each time.

When j = 4, all the vertices are equal regardless of the size, and the available register map can be painted with the size of j = 4. Therefore, f4 (d1, d2, d4, msi
The value of ngle) is true if d1 + d2 + d4 <msingle, false otherwise.

In the case of j = 2, in order to paint the register map quickly, paint is performed from the interference vertex of j = 4 size. At this time, you should paint from the place where there is a double space. j =
After filling all the vertices of 4 sizes, if doubles remain, they are replaced with two single vacancies. Vertices of size j = 1 can be considered to interfere as vertices of size j = 2. Formulating the above, the value of f2 (d1, d2, d4, mdouble, msingle) is d4 <mdo
For uble, true if d1 + d2 <msingle + (mdouble-d4) * 2, false otherwise. When d4> = mdouble, d
True if 1 + d2 + d4 <msingle + mdouble, false otherwise.

When j = 1, the size is the smallest, and it is necessary to consider the interfering vertices of the three sizes. First, the largest size j
= 4 interfering vertices. At this time, the space is filled in the order of priority of quad, triple, separate, double, and single. Except for separate and double, empty maps have an inclusive relationship in this order, so the correctness of priority can be intuitively understood, but the reason for the priority of separate is higher than double is as follows . For both vertices of size j = 4, there is no difference in painting the register map at the same ratio. Size j =
This results in the problem of whether to leave a separate or double for the vertex of No. 2, but the vertex of size j = 2 can be painted quickly as a double, and the double should be left behind. Therefore, for the size j = 4, the paint must be applied first from the separate. Size j = 4
It is false if there is no free space during painting at the top. Up to this point, since it cannot be defined as a mathematical expression, it is defined as a processing flow in FIG. After the processing for j = 4, the size of the interfering vertex is j
= 1 and 2 and can be reduced to the function f2 described above.

F1 (d1, d2, d4, mquad, mtriple, msepara
The values of te, mdouble, msingle) are d4 == 0 after performing the above processing, and mquad, mtriple, mseparate, mdoubl
It is assumed that e and msingle have been updated. If false is not determined at this stage, the function value is f2 (0, d1, d2, mquad *
2 + mtriple + mdouble, mtriple + mseparate * 2 + msingle). A stack is created from FIG. 10 using this judgment function, and the result is shown in FIG. 12 in association with the result of register allocation by the graph reproduction unit.

Hereinafter, an object generating apparatus according to a third embodiment of the present invention will be described with reference to the drawings. If it is necessary to spill out while the stack is being created at high speed by the method of the second embodiment, it is possible to spill out by determining whether vertices can be stacked on the stack by another method. It is desirable to avoid as much as possible.

The judgment processing according to the second embodiment is the main processing in the register allocation processing, and the processing time is effective when the total number of allocated variables is equal to or larger than the square. Therefore, although high speed is required, spill-out which occurs relatively rarely is re-determined as to whether or not the spill-out can be stacked on the stack in order to avoid spill-out as much as possible. According to the present embodiment, avoidable spillout is avoided, and the efficiency of generated objects is improved. Unlike the second embodiment, the present invention is applied to a case where the operation is performed relatively rarely, and it is assumed that no problem occurs even at a low speed.

Hereinafter, a mounting method of the present embodiment will be described. Here, similarly to the judgment function f, a new judgment function g is formulated.

Usable register map ma of a certain vertex x
Fill p with the available register map of all other interfering vertices. After painting all the interfering vertices, if there is a space in the usable register map map at the size of the vertex x, the function g returns true. That is,
Vertex x is placed on the stack.

Since the remaining space is not available at any of the interfering vertices, it is guaranteed that only the space will remain unpainted when the interference graph is reproduced later. FIG. 15 shows a processing flow for the judgment function g.

As an example, it is assumed that an interference graph and an available register map as shown in FIG. 13 are given. In this case, even if the judgment function f is used, no vertices can be stacked on the stack, and spill-out must be caused. However, when the judgment function g of the present invention is used, the vertex I0 can be first stacked on the stack as shown in FIG.

As a result, without causing spill-out, FIG.
4 can be performed. The processing of the present invention described above is summarized as a processing flow of FIG. This can be summarized as in FIG.

That is, the stack creation unit according to the present invention calculates the frequency in step 401. In step 403,
Calculate the maximum frequency. In step 405, the first candidate x
Take out. In step 407, it is determined using the determination function f whether the candidate x can be stacked on the stack. If you can
At step 409, the stack is pushed to update the interference graph. In step 411, it is determined whether or not the interference graph is empty. If not, the process returns to step 405. If empty, reconstruct the interference graph.

If it is determined in step 407 that the candidate x cannot be stacked on the stack, it is determined in step 413 whether any more candidates remain. If left, step 405
Return to If not, in step 415, the process returns to the first candidate x, and it is determined in step 417 whether the candidate x can be stacked on the stack using the determination function g. If you can stack it, push it to the stack at step 409,
Update the interference graph.

If it is determined in step 417 that the candidate x cannot be stacked on the stack, it is determined in step 419 whether any more candidates remain. If there are, the process returns to step 415. If not, the process proceeds to spill-out processing.

[0082]

As described above, according to the present invention, in an object generating apparatus for translating a high-level language into machine instructions, a target machine which can access one register as a plurality of registers having a small size is provided. When register allocation is performed using an algorithm with coloring, object efficiency such as code size and execution time of generated code can be improved by performing efficient register allocation.

In addition, in the stack push in the coloring algorithm, a high-speed register allocation can be performed by performing a high-speed determination of selecting a vertex to be selected.

FIG. 17 shows the effect of the present invention. The performance of a generated object and the compile time when register allocation is performed by the conventional method and the method of the present invention using the benchmark program Stanford (C language) are shown. The effects of the present invention described above can be recognized from the results of FIG.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration diagram of an object generation device according to the present invention.

FIG. 2 shows a processing flow of a compiler to which the present invention is applied.

FIG. 3 shows a process from the intermediate code to register allocation according to the present invention.

FIG. 4 shows a processing flow of the present invention.

FIG. 5 shows a register configuration of the TLCS-900.

FIG. 6 shows an example of a simple C language program.

FIG. 7 shows an example in which the program of FIG. 6 is represented by a language-independent intermediate code.

8 is an interference graph to be created when registers are assigned by coloring to each variable on the intermediate code in FIG. 7;

FIG. 9 shows an available register map for each vertex of the interference graph of FIG.

FIG. 10 shows information obtained by replacing the information in FIGS. 8 and 7 with information necessary for the present invention.

FIG. 11 shows a decision function f equation of the present invention.

12 shows an example in which a stack is created from the information in FIG. 10 using the decision function f formula of the present invention and an example in which a graph is reproduced based on the stack (result of register allocation).

FIG. 13 shows an example in which the judgment function g of the present invention operates.

14 shows an example in which a graph is reproduced from a result obtained by testing the judgment function g with respect to the example in FIG. 13 and a stack.

FIG. 15 is a processing flow for a judgment function g of the present invention.

FIG. 16 is a conceptual diagram of single, double, separate, triple, and quad as examples of frequency types showing the configuration of a register that can be used according to the present invention.

FIG. 17 shows evaluation results of the present invention based on the Stanford benchmark.

[Explanation of symbols]

 1 Computer 5 Mouse 6 Keyboard 7 Monitor 9 Printer 13 Flexible Disk 15 Drive Drive

Claims (2)

[Claims] 1. An object generating apparatus for a target machine which can access one register as a plurality of registers of a small size, comprising: a set of automatic variables and arguments included in a high-level language source code; Means for generating an interference graph from temporary variables used temporarily when translating the language into machine instructions; means for generating a stack for storing vertices of the interference graph based on the interference graph; and Means for reconstructing the interference graph based on a coloring algorithm,
Means for generating information indicating the correspondence between each vertex and its available register, and determining whether each vertex can be stacked on the stack by referring to the information of the available register of that vertex. An object generation device that is a feature. 2. A method for generating an object for a target machine in which one register can be accessed as a plurality of registers having a small size, comprising: a set of automatic variables and arguments included in a high-level language source code; From a temporary variable used temporarily when translating the language into machine instructions, generating an interference graph, generating a stack for storing vertices of the interference graph based on the interference graph, Reconstructing the interference graph based on a coloring algorithm;
Generating information indicating the correspondence between each vertex and its available register, and determining whether each vertex can be stacked on the stack by referring to the information of the available register of that vertex. An object generation method that is a feature.