JP2000059781A - Wavelet transformer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a wavelet transformer capable of fast processing. SOLUTION: This transformer is provided with a storing part 102 consisting of a shift register 102 capable of shifting data in the directions of rows and columns, a line memory 104 for temporarily retaining a part of data for writing to a storing part, a filter part 101 for horizontal processing and vertical processing of wavelet transformation, a row direction control part 106 for controlling row direction access to a storing part, a columnar direction control part 108 for controlling columnar direction access to the storing part, and a main control part 100 which controls writing and reading of data, with respect to the storing part through the row-direction control part and the column- direction control part, controlling the wiring and reading of data with respect to the line memory and controlling the writing and reading of data with respect to an external memory 110, to successively execute wavelet transforming processing for at least one level in the inside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the field of data compression / expansion of image data and the like, and more particularly, to a wavelet transform device used for such data compression / expansion.

[0002]

2. Description of the Related Art Data compression is a very useful tool for storing and transmitting large amounts of data. For example, the time required for facsimile transmission of a document or transmission of an image such as the World Wide Web can be dramatically reduced by using compression to reduce the number of bits required to reproduce the image.

[0003] Conventionally, there are many various data compression methods. Among them, a wavelet is included.
There is a pyramid processing method.

When a wavelet transform is applied to a two-dimensional signal such as an image signal, an input signal is converted into a horizontal low-pass filter HL (Horizontal Low) and a horizontal high-pass filter HH (Horizontal High). Is separated into a horizontal low-pass signal (S (smooth) coefficient) and a horizontal high-pass signal (D (detail) coefficient), and a vertical low-pass filter VL for the S coefficient and the D coefficient. (Ve
rtical Low) and vertical high-pass filter VH (Ve
rtical High), a horizontal low band-vertical low band signal (SS coefficient), a horizontal low band-vertical high band signal (SD coefficient), a horizontal high band-vertical low band signal (DS
Coefficient), and a high-frequency signal in the horizontal direction—a high-frequency signal in the vertical direction (DD coefficient). The above series of processing is called a level.
The output that has been subjected to the horizontal processing and the vertical processing is referred to as a level 1 output. Further, the above four types of signals are called frequency band signals. When an output of level 2 or higher is desired, this processing is performed recursively on the SS coefficient. At the output of level 2, SS coefficient, 1SD coefficient and 2SD coefficient, 1DS coefficient
7 of coefficient and 2DS coefficient, 1DD coefficient and 2DD coefficient
Two frequency band signals are obtained. In the above description, the filter is applied first in the horizontal direction, and then the filter is applied in the vertical direction. However, the order may be reversed.

FIG. 14 shows a conventional configuration for performing processing up to level 4. In the figure, 1000 is a wavelet transform unit, 1001 is an interface, and 1002 is an external memory.

In the wavelet transform unit 1000,
filter1H, filter2H, filter3H, filter4H
This is a horizontal filter including a horizontal low-pass filter HL and a horizontal high-pass filter HH. Numbers 1 to 4 in these filter names represent levels, and H means a horizontal filter. Similarly, filter1
V1 and filter1V2, filter2V1 and filter2V2, fi
lter3V1 and filter3V2, filter4V1 and filter4V
Reference numeral 2 denotes a vertical filter including a vertical low-pass filter VL and a vertical high-pass filter VH.
V in these filter names means a vertical filter, numbers 1-4 before V indicate levels, and number 1 after V indicates that a horizontal low-pass signal (S coefficient) is input. Numeral 2 after V indicates that the filter receives a horizontal high-frequency signal (D coefficient) as an input. The above filter may have any configuration, but in the following description, the horizontal low-pass filter HL is used.
As the vertical low-pass filter VL, a two-tap filter that performs an operation using two sets of data is used. Also, as the horizontal high-pass filter HH and the vertical high-pass filter VH, of the S coefficient or D coefficient output from the low-pass filter HL or VL, It is assumed that a 6-tap filter that performs an operation using a total of three sets of data after the filter is used.

FIG. 15 shows an example of a calculation using such a filter. However, it should be noted that the data mapping in this figure is for explaining the operation method, and the actual mapping to the memory is as shown in FIGS. 17 to 20, for example. FIG. 15A illustrates the process of the horizontal direction filter, where [00] is 0.
It means the data of the 0th pixel of the line, and [12] means the data of the 2nd pixel of the first line (in this way, both the line and the pixel are counted from the 0th). Output of pixel 0 of horizontal low-pass filter HL [S00]
Is obtained from data [00] and data [01],
The output [S01] of the first pixel is obtained from the data [02] and the data [03]. On the other hand, the output [D00] of the 0th pixel of the horizontal high-pass filter HH
Is obtained from data (not existing) immediately before and after data [00], data [00], data [01], data [02], and data [03]. Here, a process called a mirror is performed in order to obtain data two before and one before the non-existent data [00]. Specifically, a process of turning the data back in a mirror image relationship is performed. As a result, the two preceding data and the immediately preceding data become data [01] and data [00]. In this way, [D00] is calculated from the data of six pixels.

FIG. 15B illustrates the processing of a vertical filter. This processing is performed in the vertical direction using the S coefficient and the D coefficient by the vertical filter processing. Non-existent coefficients are subjected to mirror processing in the same manner as in the horizontal filter processing.

FIG. 16 shows image data stored in the external memory 1002 in raster order. 17 to 20
The following describes an example of a method of storing the operation results up to level 2 of the wavelet processing. The wavelet transform unit 1000
First, the image data stored as shown in FIG. 16 is read from the external memory 1002 and subjected to horizontal processing.
The result is written into the external memory 1002 again. In order to avoid overwriting unprocessed data at the time of this writing, the S coefficient and D
Write the coefficients. In FIG. 17, [1S00]
Means the S coefficient of the level 00 address 00. FIG.
Shows an example of mapping at the time of writing each coefficient after performing vertical processing. The above is the method of storing each coefficient of level 1. FIG. 19 shows an example of a method of storing each coefficient of the level 2 in the horizontal direction. It should be noted that the level 2 processing is performed only on the 1SS coefficient, so that the shaded data is not used. Next, each coefficient of level 2 is stored by mapping as shown in FIG.
Is completed. The above processing is repeated up to level 4.

FIG. 21 is a timing chart for the configuration shown in FIG. However, it should be noted that this timing chart is used for explaining the processing procedure, and the scale of the horizontal axis (time axis) is not linear. In the following description, the number of pixels or the number of lines is counted from 0, such as the 0th pixel or the 0th line. The input image data (raster data) is 32 pixels x
There are 32 lines (from the 0th pixel to the 31st pixel, from the 0th line to the 31st line), and one data segment (× =
X) corresponds to one line.

From time t0, data on the 0th line is sequentially input from the 0th pixel.
Data [1S00] of the 0th pixel is output from 1H.
Next, when the data [1S01] is output, three sets of S coefficients ([1S00], [1S0]
0] and [1S01]) (the immediately preceding data is obtained by mirror processing), and the D coefficient [1D00] is output. This is repeated for one line. It should be noted that although shown in the timing chart in units of time of one line, if it is enlarged, a shift occurs in units of pixels.

The input of the data of the first line starts at time t1, and [1S10], [1D10],
And the S coefficient and the D coefficient are sequentially output. When [1S10] is output, [1SS00] is output from filter1V1 of the vertical direction filter, and [1DS00] is output from filter1V2. Next, when [1S11] is output, fi
In the lter1V1 and the filter1V2, three sets of data necessary for calculating the D coefficient are prepared. That is, in filter1V1, [1S10], [1S10], [1S11], fi
[1D10], [1D10],
[1D11] are obtained (the immediately preceding data is obtained by mirror processing), and the output data of level 1 [1SS00],
[1SD00], [1DS00] and [1DD00] are obtained. This is repeated for one line.

At time t2, 2V first line input is started, and 2V processing is started. Thereafter, the processing is repeated until time t9 with the same timing relationship, and each frequency band signal up to level 4 is output. The frequency band signal decomposed through the above wavelet transform process is written to the external memory 1002 and used for various processes. In addition,
The frequency band signal decomposed by the wavelet transform is
The original data can be restored by the inverse wavelet transform of the inverse procedure.

Next, the processing time for the wavelet transform will be described. Here, it is assumed that a general semiconductor memory is used as storage of each frequency band signal generated by the wavelet transform unit 1000, that is, as the external memory 1002 in FIG.

As described with reference to the timing chart of FIG. 21, since each frequency band signal is output in parallel at the same time, writing to an external memory must be performed in parallel. In the memory, only one data can be read or written at one time. The lower left range of FIG. 21
Are 1H, 1 corresponding to times t0 to t9.
V,. . . , 4V processing time range ←
This is indicated by →. r / w cycle under range
s is the number of memory accesses required for each range (← →) of range, and is the sum of the number of times of writing and the number of times of reading within that range. The total number of times for each level is shown. The numerical values shown on the right side of FIG. 21 are the number of memory accesses (the total number of writing and reading) required for horizontal processing or vertical processing of each level. This value is the same at the time of the inverse wavelet transform. Regarding the number of times of memory access, in each level, both horizontal processing and vertical processing always read all data once, and all data are rewritten with filter output data. Write / write times are required.

As described above, the present invention relates to a wavelet transform device related to the present invention and an encoding / decoding device or a wavelet transform filter using the same.
For more detailed information, refer to JP-A-8-139935. Japanese Patent Application Laid-Open Nos. 3-27687 and 5-1 describe similar known prior arts.
67997 and JP-A-5-183386.

[0017]

As described above, the output of the wavelet transform needs to be temporarily stored in a storage, and there is a problem that the processing time is several times longer than the time required for simply inputting data. . In the case of the above-described conventional technology, when the size of input image data is 32 pixels × 32 lines and the number of levels is 4, the number of cycles required for inputting image data is 1024 = 32 × 32, The required processing time is 5 times or more, ie, 5440 cycles. Obviously, as the size of the input data increases, the processing time further increases. For example, in the case of 64 pixels × 64 lines, as shown by the dotted line in FIG. 21, the 1H process is performed until time t10,
Since the number of sections output in parallel increases, the processing time greatly increases. Similarly, when the number of levels increases, the processing time significantly increases.

Further, since each frequency band signal of each level is output at the same time, pipeline processing is required. That is, since the data input timing is different for each filter, it is necessary to individually design each filter by incorporating a controller corresponding to the place where the filter is used. In addition, these controllers can cope only with the combination of the number of pixels and the level of only one condition, and there is a problem that it is difficult to cope when one or both of the number of pixels and the level are changed. .

The present invention has been made in view of the above problems, and a main object of the present invention is to provide a wavelet transform device capable of performing high-speed wavelet transform processing without using pipeline processing. Another object of the present invention is to reduce the storage capacity required for realizing such a high-speed wavelet transform device.

[0020]

According to a first aspect of the present invention, there is provided a wavelet transform apparatus comprising: a storage unit including a shift register capable of shifting data in a row direction and a column direction; and temporarily storing a part of data to be written in the storage unit. A line memory for temporarily storing, a filter unit for performing horizontal processing and vertical processing of wavelet transform, a row direction control unit for controlling access to the storage unit in a row direction, and a storage unit for the storage unit. A column direction control unit for controlling access in a column direction, and controlling writing and reading of data to and from the storage unit via the row direction control unit and the column direction control unit;
A main control unit that controls writing and reading of data to and from the line memory, controls writing and reading of data to and from an external memory, and controls input and output of data to and from the filter unit. The configuration is such that one or more levels of wavelet transform processing are continuously performed on the obtained data.

According to a second aspect of the present invention, there is provided a wavelet transform apparatus comprising: a storage unit including independent storage elements; a line memory for temporarily storing a part of data written to the storage unit; A row address decode / data selector for controlling access in the row direction, a column address decoder / data selector for controlling access to the storage unit in the column direction, and a row address decoder / data selector. A row direction filter unit for performing horizontal processing of wavelet transform on data input via the data selection unit, and a vertical processing of wavelet transform on data input via the column direction address decode / data selection unit. A column direction filter unit for performing the operation, the row direction address decode / data selection unit, and the column direction address decode / Controlling the writing and reading of data to and from the storage unit via the data selection unit and the input and output of data to and from the row direction filter unit and the column direction filter unit, and controlling the writing and reading of data to and from the line memory; A main control unit that controls writing and reading of data to and from an external memory, and continuously executes one or more levels of wavelet transform processing on data input from the external memory, and transfers the resulting data to the external memory. It is a configuration to output.

A feature of the wavelet transform device according to the third aspect is that, in the configuration of the wavelet transform device according to the first or second aspect, horizontal processing of the wavelet transform is executed in parallel with the data input from the external memory.

According to a fourth aspect of the present invention, in the configuration of the first, second or third aspect of the present invention, the data to be written into the line memory is not input original data but intermediate data for processing. That is.

According to a fifth aspect of the present invention, in the configuration of the wavelet transform apparatus of the first, second, or third aspect, not the input original data but the intermediate data for processing is written in the overlap area of the storage unit. That is.

According to a sixth aspect of the present invention, in the configuration of the wavelet transform apparatus according to any one of the first to fifth aspects, the storage unit stores all levels of wavelet transform processing up to the required maximum level. The purpose is to have a storage capacity necessary for continuous execution internally.

[0026]

FIG. 1 is a block diagram showing a first embodiment of the present invention. The wavelet transform device of the present embodiment includes a main control unit 100 having a built-in filter unit 101 for horizontal and vertical processing of wavelet transform, a storage unit 102, a line memory 104, a row direction control unit 106, and a column direction control unit 108. Become. Reference numeral 110 denotes an external memory connected to the present wavelet transform device. The row direction control unit 106 controls access to the storage unit 102 in the row direction (x direction), and the column direction control unit 108 controls the storage unit 10.
The access to the column 2 (y direction) is controlled. The main control unit 100 controls writing and reading of data to and from the storage unit 102 via the row direction control unit 106 and the column direction control unit 108,
, Controlling writing and reading of data to and from the external memory 110, and controlling input and output of data to and from the filter unit 101.

The storage unit 102 comprises a shift register capable of shifting data in the row direction (x direction) and the column direction (y direction). Here, it is assumed that the size of the storage unit 102 is 20 rows × 20 columns (20 pixels × 20 lines). FIG. 2 illustrates a configuration of a storage cell of the storage unit 102.

Hereinafter, this embodiment will be described in detail with reference to FIG. 1, FIG. 2, FIG. 3 to FIG. FIG. 3 illustrates an example of a method of writing data to the storage unit 102.
FIG. 4 shows an example of how to write data after horizontal processing in the storage unit 102. FIG. 5 shows an example of how the storage unit 102 and the line memory 104 are allocated (tiling) to the external memory 110, and FIG. 6 is a diagram for explaining the movement and copying of data related to the storage unit 102 and the line memory 104. FIG. FIG. 7 is a diagram illustrating an example of the mapping in the storage unit 102 at the time when the processing is completed up to the level 2. FIG. 8 is a timing chart of the conversion processing operation up to level 2 for one block. It should be noted that the content of each drawing is merely an example, and may take various forms without departing from the gist of the present invention.

Each part surrounded by a dotted line in FIG.
Of one storage cell. As shown, the storage unit 102
Is composed of one shift register SR and one multiplexer MUX. To the data input of the shift register SR of each storage cell, the output data of the preceding storage cell in the row direction (right side) or the output data of the preceding storage cell in the column direction (lower side) is input via the multiplexer MUX. You. Switching of the input data, that is, switching between data shift in the row direction and data shift in the column direction,
The control input hvb (horizontal) to the multiplexer MUX
/ vertical bar). As is clear from the above description, the data shift in the row direction (x direction) is performed from right to left, and the data shift in the column direction (y direction) is performed from bottom to top. become.

When performing the wavelet transform, first, the data of the 0th line of the image data stored in the external memory 110 is read under the control of the main control unit 100, and this is read out by the storage unit via the row direction control unit 106. 102
Are input to the forefront (right end) of the j-th row (see FIG. 4) at the bottom and are sequentially shifted to the left. However, the 0th pixel and the 1st pixel
Since a mirror process is required for the pixel, the data is written in the storage unit 102 in that order from the beginning. The shaded portions in FIG. 3 indicate the data of the mirror-processed pixels. When all the data on the 0th line is written as shown in FIG. 3B, this data is shifted to the next higher row. Next, data of the first line is similarly read from the external memory 100, input to the bottom row of the storage unit 102 by the row direction control unit 106, and sequentially shifted to the left. In addition, horizontal processing is executed by the filter unit 101 in parallel with the data input, and the S coefficient and the D coefficient calculated for the data of the 0th line are output to the 0 line of the storage unit 102 via the row direction control unit 106. The data is input to the line where the eye data is written and sequentially shifted to the left. FIG. 3 (c)
This shows a state in the middle of the horizontal processing of the 0th line and the input processing of the data of the 1st line. By inputting the same image data and performing the horizontal processing repeatedly in parallel, the result of the horizontal processing is finally stored in the storage unit 102 in FIG.
Is mapped as shown in The line memory 1
Writing and reading of data with respect to the data 04 are also performed, which will be described later.

It should be noted that, in FIG. 4, the same data as the third and second rows is written in the 0th and 1st rows of the storage unit 102. This is a mirror process in the vertical direction. Specifically, at the stage when the processing up to the j-th row is completed, the data of the third row is written to the 0-th row under the control of the row direction control unit 106, and Row data is written to the first row. It should be noted that the same data is written in the i-th column and the j-th column of each row, as in the g-th column and the h-th column. This is performed under the control of the row direction control unit 106 in the course of the horizontal processing. The reason will be described later.

Now, vertical processing is performed on the S coefficient and the D coefficient on the storage unit 102 mapped as shown in FIG. However, it should be noted that the 0th column and the 1st column are not processed. In the case of vertical processing, the column direction control unit 10
8, the data in the second column is sequentially shifted in the column direction (upward), and the shifted out data is input to the filter unit 101 in the main control unit 100, where the SS coefficient, S
D coefficients are calculated, and the coefficients are sequentially input to the second column of the storage unit 102 and shifted by the control of the column direction control unit 108. Similarly, the data in the third column is shifted in the column direction, and the shifted-out data is input to the filter unit 101 to calculate the DS coefficient and the DD coefficient, which are input to the third column and shifted. By repeating the same processing up to the h-th column, the level 1 wavelet transform ends.

The level 2 wavelet transform is performed only on the level 1 SS coefficient (1SS) in the storage unit 102. That is, the data of each row is shifted in the row direction under the control of the row direction control unit 106, the shifted 1SS coefficient is sent to the filter unit 101, and the 2S coefficient and the 2D coefficient are calculated. This coefficient is shifted out. Level 1 data (1SD coefficient, 1DS coefficient, 1D
D coefficients), and are input to the row in an order such that the mapping as shown in FIG.
This repetition ends the level 2 horizontal processing. Note that the 0th row and the 1st row are not subject to processing. Further, the data in the i-th column and the j-th column in each row are also excluded from the processing. Next, level 2 vertical processing is performed. For each column from the second column to the g-th column, data is sequentially shifted in the column direction under the control of the column direction control unit 108, and the shifted 2S
The coefficient or 2D coefficient is input to the filter unit 101 and
The S coefficient and the 2SD coefficient, or the 2DS coefficient and the 2DD coefficient are calculated, and these coefficients are input to the corresponding column together with the shifted out data in the order shown in FIG. 20 and sequentially shifted. . This process is repeated, and the level 2 process ends. Thus, the results of the wavelet transform up to level 2 are mapped on the storage unit 102 as shown in FIG. This 16 pixels x 1
The six lines of data are written to the external memory 110.
When performing level 3 or higher conversion, the external memory 110
Only the above SS3 coefficient is read into the storage unit 102, and the same processing is performed.

FIG. 5 shows a tiling method when the size of the external memory 110 is larger than the size of the storage unit 102. B00 means a block (horizontal 0, vertical 0). Here, the size of the storage unit 102 is 20 pixels × 2
Since it is 0 line, x0 in FIG.
2x0 is the 31st pixel (counted from 0), y0 is the 15th line, and 2y0 is the 31st line (x0 = y0
= 15, 0). Therefore, 32 pixels x
When processing an image of 32 lines (from the 0th pixel to the 31st pixel, from the 0th line to the 31st line), it is necessary to divide the image into four blocks B00, B01, B10, and B11 as shown in the figure. (This diagram is for comparison with the prior art). Next, the processing of each block will be described with reference to FIG. <Process of Block B00: FIG. 6 (a)> This Block B
For 00, image data of 18 pixels × 18 lines from the 0th pixel to the 17th pixel and the 0th line to the 17th line are read into the storage unit 102. FIG.
Since the data shown in FIG. 7A does not actually exist, the data is supplemented by mirror processing. A part that is necessary for the processing of the block B10 on the lower side but is overwritten by the converted data of the block B00 (g in FIG. 4)
Row, the h-th row) is stored in the line memory 10 in advance.
4 In addition, a portion that is overwritten by the converted data of the block B00 (the g-th column in FIG. 4,
The data of the (h-th column) is copied in advance to the right end (the i-th column and the j-th column in FIG. 4) of the storage unit 102 so that the data can be used in the processing of the lower adjacent block B01. The conversion for the block B00 is performed, and the converted data (data of 16 pixels × 16 lines shown in FIG. 7) is written to the 0th to 15th pixels and the 0th to 15th lines of the external memory 110. It is. Next, block B01 is processed. <Process of Block B01: FIG. 6 (b)> This Block B
For 01, image data of 18 pixels × 18 lines from the 16th pixel to the 33rd pixel and the 0th line to the 17th line are read into the storage unit 102. At this time, the data at the right end of the storage unit 102 is moved to the left end (the 0th and 1st columns in FIG. 4). The data in the portion where no data exists is supplemented by mirror processing. The data (corresponding to the g-th row and the h-th row in FIG. 4) necessary for the processing of the block B11 below but overwritten by the converted data of the block B01 is copied to the line memory 104 in advance. . The conversion data for the block B01 is written in the region from the 16th pixel to the 31st pixel and the 0th line to the 15th line of the external memory 110. The process proceeds to block B10. <Block B10: FIG. 6 (c)> In this block B10, image data from the 0th pixel to the 17th pixel and the 16th line to the 33rd line are stored in the storage unit 102.
Is read in. The data in the portion where no data exists is supplemented by mirror processing. Is overwritten with the converted data of the upper adjacent block B00, so that the data of that part saved in the line memory 104 is written. Is stored in the storage unit 10 so that it can be used in the processing of the block B11 on the right.
2 is copied to the right end. The data of the part overwritten by the converted data of the block B10 is stored in the line memory 10
4 The converted data of the block B10 is stored in the external memory 110 from the 0th pixel to the 15th pixel,
Data is written to the area from the 31st line to the 31st line.
Next, the process proceeds to block B11. <Process of Block B11: FIG. 6D> External Memory 11
The image data of the 0th pixel from the 16th pixel to the 33rd pixel and from the 16th line to the 33rd line are written to the storage unit 102. At this time, the data of the portion at the right end of the storage unit 102 is moved to the left end. The data saved in the line memory 104 is written in the section of. Is copied to the line memory 104. The conversion data for the block B11 is stored in the external memory 110 from the 16th pixel to the 31st pixel.
Data is written to the area from the 31st line to the 31st line.

FIG. 8 is a timing chart when the wavelet transform up to level 2 is performed on each block described above. The period from time t0 to time t1 is a period during which data is read from the external memory 110 to the storage unit 102 and the level 1 horizontal processing is performed.
The period from time t4 to time t5 is a period during which converted data is written to the external memory 110. The number of cycles for reading and writing data to and from the external memory 110 is 400 cycles (= 20 × 20) and 256 cycles (= 16 × 16), respectively. Internal operations without access to external memory 110 can be much faster than external memory access,
Here, when the number of cycles in the period from time t1 to time t4 is calculated assuming that the internal operation has the same operation speed as the external memory access, 800 cycles are obtained. Therefore, the total number of cycles from time t0 to time t5 is 145
This is six cycles.

The same processing is performed for B00, B01, B10, and B1.
This is repeated for four blocks of 1 to obtain level 2 conversion data. To obtain level 4 conversion data, SS coefficients (2SS) included in four blocks B00 to B11 are collected and processed as one block. In this processing, there are 9 pixels and 9 lines (counting from 0), so the number of cycles is 1/4 of the processing of the block B00, that is, 364 cycles. Therefore, the total time required for the wavelet transform processing up to level 4 is (400 + 256 + 800) * (4 + ／) = 618
8 However, this limits the speed of internal operation to external memory
The numerical value is assumed to be the same as that of the access. Actually, it is easy to speed up the internal operation several times as compared with the external memory access, so that the total time can be further reduced. For example, assuming that the speed of the internal operation is twice that of the external memory access, the total time is (400 + 256 + 800/2) * (4 + ／) = 4
Decreases to 488 cycles. The speed of the internal operation
Assuming four times the access, the total time is (400 + 256 + 800/4) * (4 + ／) = 3
Decreases to 638 cycles. Thus, according to the present invention,
Total time 544 when performing similar processing in the prior art
It is clear that the total time can be shortened from zero cycle.

FIG. 9 is a block diagram showing a second embodiment of the present invention. The wavelet transform device of the present embodiment
Main control unit 200, storage unit 202, line memory 204,
A row direction filter unit 206 for horizontal processing of wavelet transform, a column direction filter unit 207 for vertical processing,
A row direction address decode / data selection unit 208;
It comprises a column direction address decode / data selection unit 209. Reference numeral 210 denotes an external memory connected to the present wavelet transform device. The row direction address decode / data selection unit 208 controls access to the storage unit 202 in the row direction, and the column direction address decode / data selection unit 209 controls access to the storage unit 202 in the column direction. Things. The main control unit 200 writes and reads data to and from the storage unit 200 and inputs and outputs data to the filter units 206 and 207 via the row-direction address decode / data selection unit 208 and the column-direction address decode / data selection unit 209. It controls writing and reading of data to and from the line memory 204, and also controls writing and reading of data to and from the external memory 210. The line memory 204 is used for the same purpose as the line memory 104 in the first embodiment. In FIG.
4 shows one storage cell in the storage unit 202.

In the wavelet transform device of this embodiment, as described above, the filter unit for wavelet transform is separated into the row direction filter unit 206 for horizontal processing and the column direction filter unit 207 for vertical processing. Have been. At the time of horizontal processing, data necessary for the filter operation is input to the row direction filter unit 206 via the row direction address decode / data selection unit 208, and the operation result is stored via the row direction address decode / data selection unit 208 to the storage unit 202. Is written to. At the time of the vertical processing, data necessary for the filter operation is input to the column direction filter unit 207 via the column direction address decode / data selection unit 209, and the operation result is stored in the storage unit via the column direction address decode / data selection unit 209. 202 is written. Except for the configuration related to such a filter unit, the overall operation of the wavelet transform device of this embodiment is basically the same as that of the first embodiment, and the method of using the line memory 204 is also the same. is there.

However, in the storage unit 202, each storage cell is completely independent as shown in FIG.
The address issued from 0 is decoded in the row direction address /
By decoding by the data selection unit 206 and the column address decode / data selection unit 209, writing / reading can be directly performed on an arbitrary storage cell. Therefore, the storage unit 202 is stored in the external memory 210.
Immediately after the end of data transfer to, all row-direction processing (horizontal processing) can be repaired in a few cycles.
Immediately after the completion of the horizontal processing, the processing in the column direction (vertical processing) can be completed in several cycles. That is, the first
The operation of internal processing can be made much faster than in the embodiment.

FIG. 11 is a timing chart of the wavelet transform apparatus of this embodiment in the same tiling processing as in the first embodiment. In FIG. 11, a period from time t0 to time t1 is a period of data reading from the external memory 210 and the level 1 horizontal processing.
A period from 1 to time t4 is an internal period of level 1 vertical processing, level 2 horizontal processing and vertical processing. A period from time t4 to time t5 is a period for writing data to the external memory 210. Reading and writing data to and from the external memory 210 are 400 cycles and 256 cycles, respectively. As described above, time t1 to time T of the internal processing
In the period up to 4, if the internal operation is faster than the access to the external memory 210, it can be almost neglected.
When the number of cycles is calculated assuming 00 cycles, the time t
The total number of cycles from 0 to time t5 is 756 cycles. This processing is performed for four blocks B00, B01, and B1.
0 and B11 (see FIG. 5) are repeated to obtain level 2 conversion data. To obtain level 4 conversion data, SS coefficients (2SS) included in four blocks B00 to B11 are collected and processed as one block.
In this processing, 9 pixels and 9 lines (counting from 0) are used, so that the number of cycles is 1/4 of the processing of the block B00,
That is, 189 cycles are required. Therefore, level 4
The total time required for the wavelet transform processing up to (400 + 256 + 100) * (4 + 1/4) = 321
Three cycles. Assuming that the internal processing is 50 cycles, the total time is reduced to (400 + 256 + 50) * (4 + ／) = 3000 cycles. As described above, according to the present embodiment, it is clear that the total time can be significantly reduced as compared with 5440 of the prior art, and further higher speed processing is possible as compared with the first embodiment. It will be understood.

In the first or second embodiment, the line memories (104, 204) are
Although the original data input from the outside is written as it is, according to the third embodiment of the present invention, in the wavelet transform device having the same configuration, the characteristic of the filter of the wavelet transform is utilized to process the line memory. (In the present invention, the output of the low-pass filter of the filter unit) is written. As a result, if the other conditions are the same as those of the above embodiments, as shown in FIG. 12, the size X of the line memories (104, 204) in the row direction is the same as that of the above embodiments. , 210) in the row direction, but the size Y in the column direction can be halved from 2 in the above embodiments to 1. Such an effect of reducing the capacity of the line memory is more remarkable as the size of the external memory in the row direction is larger and the number of taps of the high-pass filter is larger.

According to a fourth embodiment of the present invention, the first
In a configuration similar to the embodiment, the second embodiment or the third embodiment, as shown in FIG. 13, the size of the storage unit (102, 204) can be reduced by two rows and two columns. This corresponds to the overlap area of the storage unit (FIG. 1)
3 (shaded area), utilizing the characteristics of the filter, the intermediate data of the processing (the output of the low-pass filter in the present invention)
(In the above embodiments, the original data input from the outside is written in the overlap area as it is.) The effect of reducing the capacity of the storage unit according to this embodiment is more remarkable as the number of taps of the high-pass filter increases.

In each of the above embodiments, the size of an image that can be processed at one time is limited by the size of the storage units (102, 202). Therefore, when the number of required wavelet levels increases, the number of wavelet levels up to a certain level is reduced. The result is temporarily written to the external memory (110, 210), and the S
It is necessary to deal with this by a recursive processing method of reading and processing the S coefficient again.

According to the fifth embodiment of the present invention, if the maximum level of the required wavelet transform is known in advance in the same configuration as the above embodiments, the wavelet of all levels up to the maximum level is obtained. The storage units (102, 202) have a storage capacity necessary for continuously executing the conversion process internally. For example, when a wavelet transform up to level 6 is required, the size of the storage unit (102, 204) is determined to be (64 rows × 64 columns + overlap area). If the size is set to such a value, the wavelet transform of all levels from level 1 to level 6 is performed by internal processing on the read data without performing the recursive processing as described above. Since the result can be written to the external memory, the number of times of reading and writing to the external memory, which is slower than the internal processing, is reduced, and the processing speed can be further increased.

The above-described wavelet transform device according to the present invention can be incorporated in an encoding / decoding device. For example, the wavelet transform device according to the present invention and the encoder / decoder can be integrated on the same chip. According to such an encoding / decoding device,
It is possible to perform compression / expansion of image data using a wavelet transform at a higher speed than before.

[0046]

As described in detail above, the wavelet transform apparatus according to the first aspect can perform wavelet transform processing at a higher speed than that of the prior art, and does not require pipeline processing unlike the prior art. Configuration,
It is possible to easily cope with a change in the number of processing pixels and levels in the wavelet transform. The wavelet transform device according to claim 2 can perform higher-speed processing than the wavelet transform device according to claim 1, and can easily cope with a change in the number of pixels to be processed and the number of levels similarly. In the wavelet transform device according to the third aspect, further speeding up is possible by parallelizing the data input from the outside and the horizontal processing of the wavelet transform. The wavelet transform device according to claim 4 or 5 can reduce the storage capacity of the line memory and / or the storage unit. According to the wavelet transform apparatus of the sixth aspect, since the processing of the wavelet transform of all levels up to the required maximum level can be continuously executed internally, it is possible to obtain effects such as higher speed processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a storage cell of a storage unit according to the first embodiment.

FIG. 3 is an explanatory diagram of a data flow in a row direction in a storage unit.

FIG. 4 is a diagram showing mapping of a storage unit at the stage of ending level 1 horizontal processing.

FIG. 5 is a diagram illustrating an example of how a storage unit and a line memory are allocated to an external memory;

FIG. 6 is a diagram illustrating a data flow relating to a storage unit and a line memory during each block processing.

FIG. 7 is a diagram illustrating mapping of a storage unit when a wavelet transform up to level 2 is completed.

FIG. 8 shows level 2 for one block in the first embodiment.
6 is a timing chart when performing the wavelet transform up to.

FIG. 9 is a block diagram showing a second embodiment of the present invention.

FIG. 10 is a diagram illustrating one storage cell of a storage unit according to the second embodiment.

FIG. 11 is a timing chart when a wavelet transform up to level 2 is performed on one block in the second embodiment.

FIG. 12 is a diagram for explaining a third embodiment of the present invention.

FIG. 13 is a diagram for explaining a fourth embodiment of the present invention.

FIG. 14 is a block diagram showing a conventional example.

FIG. 15 is an explanatory diagram of a calculation method of horizontal processing and vertical processing of wavelet transform.

FIG. 16 is a diagram showing a memory map of image data.

FIG. 17 is a diagram showing a memory map of an S coefficient and a D coefficient of level 1;

FIG. 18 is a diagram showing a memory map of an SS coefficient, an SD coefficient, a DS coefficient, and a DD coefficient of level 1;

FIG. 19 is a diagram showing a memory map of an S coefficient and a D coefficient of level 2;

FIG. 20 is a diagram showing a memory map of an SS coefficient, an SD coefficient, a DS coefficient, and a DD coefficient of level 2;

FIG. 21 is a timing chart of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Main control part 101 Filter part 102 Storage part 104 Line memory 106 Row direction control part 108 Column direction control part 110 External memory 200 Main control part 202 Storage part 204 Line memory 206 Row direction filter part 207 Column direction filter part 208 Row direction address Decode / Data Selector 209 Column Direction Address Decode / Data Selector 210 External Memory

Claims (6)

[Claims] 1. A storage unit comprising a shift register capable of shifting data in a row direction and a column direction, a line memory for temporarily storing a part of data written to the storage unit, A filter unit for horizontal processing and vertical processing, a row direction control unit for controlling access to the storage unit in a row direction, and a column direction control unit for controlling access to the storage unit in a column direction And controlling writing and reading of data to and from the storage unit via the row direction control unit and the column direction control unit, controlling writing and reading of data to and from the line memory, and writing and reading data to and from an external memory. And a main control unit for controlling the input and output of data to the filter unit. A wavelet transform apparatus which continuously executes one or more levels of wavelet transform processing and outputs the result data to the external memory. 2. A storage unit including independent storage elements, a line memory for temporarily storing a part of data written to the storage unit, and controlling access to the storage unit in a row direction. , A column direction address decode / data selection unit for controlling access to the storage unit in the column direction, and an input via the row direction address decode / data selection unit. Row direction filter unit for performing horizontal processing of wavelet transform on data to be processed, and column direction filter unit for performing vertical processing of wavelet transform on data input through the column direction address decoder / data selector. And data to the storage unit via the row direction address decode / data selection unit and the column direction address decode / data selection unit. Control the writing and reading of data, and the input and output of data to the row direction filter unit and the column direction filter unit, control the writing and reading of data to and from the line memory, and write and read data to and from the external memory. A main control unit for controlling the data, and continuously executing one or more levels of wavelet transform processing on the data input from the external memory, and outputting the result data to the external memory. apparatus. 3. The wavelet transform apparatus according to claim 1, wherein horizontal processing of wavelet transform is executed in parallel with data input from said external memory. 4. The wavelet transform device according to claim 1, wherein the data written to the line memory is intermediate data for processing. 5. The wavelet transform apparatus according to claim 1, wherein intermediate data for processing is written in an overlap area of said storage unit. 6. The wavelet transform device according to claim 1, wherein the storage unit is necessary for continuously executing internally all levels of wavelet transform processing up to a required maximum level. Wavelet transform device having a large storage capacity.