JP2000059242A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a DC offset generated at the analog circuit of a receiver executing digital signal processing. SOLUTION: A carrier wave including an information signal received by a receiving part 31 is demodulated by a demodulation part 33 and A/D converted by an A/D converter to become a digital signal. This receiver extracts a DC component from the digitized signal outputted from this part 19 by a digital low-pass filter 39 and executes feedback by using this DC component which can be regarded to be directly reflecting the DC offset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver,
The present invention relates to a receiver in which a DC offset generated in an analog circuit is reduced.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the size and performance of a receiver, a part of a signal processing circuit constituted by an analog circuit has been replaced with a digital signal processing circuit. For example, in a dual-mode mobile phone capable of performing both digital and analog communication, a part of the analog communication processing function previously constituted by an analog circuit is partially replaced by a DSP (Digital Signal).
Processor and ASIC (Applicati)
on Specific IntegratedCir
The number of components has been reduced by replacing the digital signal processing device with a digital signal processing device such as a digital signal processing device (circuit). in this way,
2. Description of the Related Art In receivers, analog circuits have been replaced with digital circuits to reduce the size and performance of receivers.

FIG. 5 is a diagram schematically showing a configuration of a receiving circuit portion (receiver) of a transceiver using a general super-heterodyne system in a conventional analog portable telephone which performs digital signal processing. . As shown in FIG. 5, a received signal that is a modulated wave from the antenna 11 is supplied to an FM demodulator (a part that demodulates a modulated wave by FM)
The signal is demodulated in 27. Specifically, for example, the received signal is mixed with the oscillation output from the local oscillator 15 by the mixer 13 and becomes an IF band (intermediate frequency band) signal, which is input to the wavelength discriminator 17 and the like. Demodulated to a band signal. The demodulated baseband signal is converted from an analog signal to a digital signal so that digital signal processing can be performed. This conversion is performed by the A / D converter 19 provided at the subsequent stage of the FM demodulator 27. The baseband signal converted into a digital signal by the A / D converter 19 is a DS signal.
Appropriate signal processing is performed by a digital signal processing unit 21 such as P or ASIC. The signal subjected to the digital signal processing is returned to an analog signal again by the D / A converter 23, and is output from the output unit 25 as an audio output.

[0004]

However, in the above-mentioned receiver, a DC offset occurs when the A / D converter converts an analog signal into a digital signal. For example, when the input analog signal has a value representing a zero point, the A / D converter is expected to output a digital signal representing zero correspondingly. However, it was actually difficult to obtain a completely corresponding output. This is because the characteristics of the components constituting the A / D converter, which is an analog circuit, vary due to manufacturing deviations. This is because, even in the case of parts whose numerical values indicate the same characteristics, actually, there is a certain degree of characteristic deviation between these parts. Therefore, a DC offset has occurred in the A / D conversion unit in combination with a characteristic change caused by aging.

[0005] Further, not only the A / D conversion section itself has a problem, but a similar problem also occurs in its peripheral circuits. For example, in a circuit that supplies a reference potential to the A / D conversion unit (reference potential generation circuit), a reference potential having a deviation from an ideal value is supplied to the A / D conversion unit due to a deviation in characteristics of constituent components. In some cases. Such a shift in the reference potential, which is to be a reference point for conversion, causes the above-described DC offset.

In particular, when the reference potential generation circuit and the A / D conversion circuit are of a type in which power is supplied by a single power supply,
It has been difficult to generate an accurate reference potential. Also in such a case, a shift in the reference potential occurs, and thus a DC offset occurs. Also, in order to suppress this DC offset, if an attempt is made to supply a highly accurate reference potential,
A large-scale reference potential generation circuit is required.

On the other hand, the FM demodulation unit is also formed of an analog circuit, like the above-mentioned A / D conversion unit. As described above, the components of the FM demodulation unit have characteristic deviations for each product. Therefore, the DC is also used in the FM demodulation unit.
Offsets could occur. The occurrence of the DC offset is not limited to the demodulation unit that performs the FM demodulation, and the same applies to the demodulation unit that demodulates the modulated wave by the analog modulation. For example, it also occurs when demodulating a PM (phase modulated) modulated wave.

[0008] In addition to the superheterodyne communication used in the description of the conventional configuration in the illustrated example, the communication in other systems is not limited to the superheterodyne communication as long as the demodulation unit and the A / D conversion unit are constituted by analog circuits. , DC offset often occurs.

Therefore, there has been a demand for a receiver capable of reducing the DC offset which has been inevitably generated in a demodulator, an A / D converter, etc., that is, capable of compensating for the DC offset.

[0010]

According to the present invention, there is provided a receiver for receiving a modulated wave subjected to analog modulation, and demodulating the modulated wave into a baseband signal which is an original analog signal. A demodulation section, an A / D conversion section for converting the baseband signal into a digital signal, a digital signal processing section for performing desired digital signal processing on the baseband signal which has become a digital signal, and a digital signal processing section. A D / A converter for converting the output digital signal into an analog signal, and an output unit for externally outputting the analog signal from the D / A converter are provided. And
According to the configuration of the present invention, in this receiver, the feedback circuit having the digital low-pass filter is provided with the aforementioned A / A
It is provided between a branch point in the middle of a path from the D conversion unit to the above-mentioned digital signal processing unit and a feedback point on the previous stage side of this branch point and after the demodulation unit. I have. A feedback circuit provided by branching from the branch point is a circuit that performs feedback for reducing a DC offset by using a DC component extracted by the above-described digital low-pass filter.

According to such a configuration, the feedback circuit is branched from a branch point in the middle of a path from the A / D conversion section to the digital signal processing section at the subsequent stage, and the demodulation section is provided before the branch point. Thereafter, feedback is performed in a circuit in a subsequent stage. This feedback is based on the DC component of the baseband signal transmitted through a digital low-pass filter (hereinafter sometimes abbreviated as digital LPF) among the baseband signals that are converted into digital signals from the RF circuit and transmitted to the logic circuit. Perform using As will be described later, feedback is performed to an RF circuit or a logic circuit using a DC component that directly reflects the magnitude of the DC offset. Therefore, appropriate control according to the magnitude of the DC offset becomes possible, and the DC offset can be reduced. The RF circuit referred to here is A /
This means a circuit that drives a signal before being converted into a digital signal by the D conversion unit, that is, an analog circuit that is configured by the reception unit and the demodulation unit and a part of the A / D conversion unit. On the other hand, a logic circuit means a circuit that drives a digital signal, that is, a digital circuit formed by a part of an A / D converter and a digital signal processor.

Note that the DC offset is a direct current component which constantly occurs in an RF circuit and which should not be ideally included. The DC component transmitted by the digital LPF is considered to be a component directly reflecting the magnitude of the DC offset to be eliminated.
The direct current component may be fed back to directly control the element that can be a source of the DC offset, or the deviation of the potential in the circuit due to the DC offset may simply be eliminated.

Here, it is considered that the circuit for compensating for the DC offset generated in the RF circuit can be constituted by an analog circuit. However, the configuration using the digital circuit is limited as described above for the following two reasons. The first reason is that if a circuit for compensating for a DC offset is configured by an analog circuit, the number of components of the receiver increases. When the number of parts increases, the size of the receiver device increases, and the manufacturing cost increases. The second reason is that in a digital circuit such as a digital filter, the above-described demodulator or A / D
This is because, unlike an analog circuit constituting a conversion unit or the like, there is no variation in characteristics of each product due to a manufacturing deviation, and further, there is no aging. For this reason, in the present invention, the circuit for compensating for the DC offset is constituted by a digital circuit.

In practicing the present invention, preferably, a D / A converter is provided in the feedback circuit as a subsequent stage of the digital low-pass filter, and the DC component is controlled by the D / A converter. The signal is converted into an analog DC component (a DC component converted into an analog signal), and the feedback circuit is preferably a circuit that feeds back the analog DC component as a control signal to the A / D converter.

According to this configuration, the DC component extracted by the digital LPF is converted into an analog DC component by the D / A converter, and the analog DC component is fed back to the A / D converter as a control signal. And R
Control is performed to reduce the DC offset generated in the F circuit. That is, since the A / D converter that can be a source of the DC offset can be directly controlled, the DC offset can be effectively reduced.

In practicing the present invention, preferably, a D / A converter is provided in the above-mentioned feedback circuit as a stage subsequent to the above-mentioned digital low-pass filter, and the above-mentioned DC component is converted by the D / A converter. The analog DC component is converted into an analog DC component (DC component converted into an analog signal), and the feedback circuit is preferably a circuit that feeds back the analog DC component as a control signal to the demodulation unit.

According to this configuration, the DC component extracted by the digital LPF is converted into an analog DC component by the D / A converter, and the analog DC component is fed back to the demodulator as a control signal. Then, control is performed to reduce the DC offset generated in the RF circuit. As a result, the demodulation unit that can be a source of the DC offset can be directly controlled.
C offset can be effectively reduced.

In practicing the present invention, preferably, the DC component is used as a digital DC component (the DC component as a digital signal), and the feedback circuit is provided by the A / D converter. It is preferable that the digital DC component is subtracted from the above-described baseband signal converted into a digital signal, and the digital DC component is fed back into the logic circuit.

According to this configuration, the DC component extracted by the digital LPF is fed back as a digital signal, and is fed back into the logic circuit so as to subtract a DC offset included in the digitally converted baseband signal. Let me. Thereby, D / A as described above
Without using a converter or the like, it becomes possible to perform DC offset compensation by closing the logic circuit. That is, by branching from the logic circuit and feeding back to the logic circuit, noise generated by the connection between the logic circuit and the RF circuit can be reduced.

In practicing the present invention, preferably, the digital low-pass filter is a digital low-pass filter that averages and outputs the input baseband signal.

According to this configuration, a digital LPF can be realized by a simple program.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement relationship of each component are only schematically shown to the extent that the present invention can be understood. It should also be understood that the numerical conditions and equations described below are merely exemplary.

FIG. 1A is a block diagram schematically showing the configuration of a receiver according to the present invention. FIG. 1 (B)
FIG. 4 is a diagram illustrating the generation of a DC offset with an example. Hereinafter, a receiver according to the present invention will be described with reference to FIG.

First, a portion of the receiver according to the present invention which has the same configuration as the conventional configuration will be described. FIG. 1 (A)
In the receiver shown in (1), the receiving unit 31 is an element for receiving a modulated wave that has been subjected to analog modulation. This receiver 3
1 may be used for either a wireless communication method or a wired communication method. In general communication, a carrier used for information transmission is modulated by a baseband signal, which is information to be transmitted, in response to a request for multiplexing. The carrier modulated by the baseband signal in this way is called a modulated wave. Further, analog modulation refers to modulation by an analog signal having a continuous value in time. Such analog modulation includes FM (Frequency Modulatio).
n: frequency modulation) or PM (Phase Modulat)
ion: phase modulation).

The modulated wave received by the receiver 31 is demodulated by the demodulator 33 into a baseband signal which is an original analog signal. Then, the baseband signal is converted into a digital signal by being input to the A / D converter 19. As already mentioned, the circuits before and after this point of analog-digital conversion are:
These are called an RF circuit 35 and a logic circuit 37, respectively. The baseband signal is converted into a digital signal and then input to the digital signal processing unit 21. The digital signal processing unit 21 includes a CPU, a DSP, an ASIC,
It is composed of In a mobile phone or the like, reception of a SAT signal or detection of a WBD signal
This is performed by the digital signal processing unit 21. In the digital signal processing section 21, the signal subjected to appropriate signal processing is input to the D / A conversion section 23 and returned to an analog signal. Then, it is externally output from the output unit 25 by an appropriate output method according to the transmission information.

As already described in the conventional example, the RF circuit 3
5, a DC offset occurs due to a manufacturing deviation or the like. For example, FIG.
FIG. 3 is a diagram schematically illustrating a DC offset generated in an A / D conversion unit. Here, a case will be described in which the A / D conversion unit 19 is a type of an A / D conversion unit having a reference potential generation circuit that internally generates a reference potential. A /
It is assumed that the baseband signal input to the D conversion unit 19 is represented by a waveform α. When the true reference potential V _BAS of the waveform α differs from the externally applied reference potential V _REF , the A / D converter recognizes the wrong reference potential as the reference potential and performs A / D conversion. . At this time, in the A / D converter, the DC offset V having a magnitude of | V _BAS −V _REF |
_OFFSET will occur. As already explained, A
The occurrence of the DC offset not only in the / D conversion unit but also in the RF circuit may be caused by various factors caused by the manufacturing deviation, in addition to the above-described deviation of the reference potential in the A / D conversion unit.

Next, a feedback circuit, which is a feature of the present invention, for reducing the DC offset generated in the RF circuit 35 will be described. Digital low-pass filter (digital LPF) as shown in FIG.
A feedback circuit 41 having a circuit 39 is provided so as to be branched from a connection midpoint (referred to as a branch point) between the A / D conversion unit 19 and the digital signal processing unit 21. This feedback circuit 4
1, the baseband signal output from the A / D converter 19 and converted into a digital signal is input. Then, the digital LPF 39 extracts a DC component from the band of the baseband signal. The digitized DC component obtained here is considered to directly reflect the DC offset generated in the RF circuit.

In an ideal state, that is, in a state where no DC offset has occurred, the DC component of the baseband signal is expected to exhibit a zero level (predetermined reference value). As described above, by detecting the deviation of the DC component from the zero level in the state of being converted into a digital signal, D
Only the digital signal corresponding to the C offset component can be effectively extracted.

The digital LPF 39 may be a digital filter that transmits only a band lower than a band irrelevant to information transmission. Since the purpose is to reduce the DC offset generated in the RF circuit, the band extracted by the digital LPF is a low band as shown by the temporal variation of the DC offset generated in the RF circuit, or a band lower than that band. What is necessary is to transmit only the band.

It is preferable that the configuration of the digital LPF is a digital filter for averaging and outputting the input baseband signal. The description is given below. That is, in designing a digital filter that transmits the above-described band, it may be designed as a digital filter that averages an input baseband signal. Thus, the configuration of the digital LPF can be simplified without substantially impairing the DC offset compensation function. There are various well-known digital filters that take an average value for an input signal and output the average value.

Here, a specific example of a digital LPF that averages and outputs an input baseband signal will be described.

(Design Example 1 of Digital LPF) For example,
In the digital LPF, if the input signal sequence is {x _n }, the output signal sequence is {y _n }, and the number of signals from the start of input for averaging is n (n is a natural number of 0 or more), the signal The relationship can be represented by the following difference equation (1).

Y _n = (n−1) / n × y _n−1 + 1 / n × x _n (1) In this way, it is possible to configure a recursive digital filter that takes an average of infinite time. The digital LPF represented by the equation (1) has an input signal x _n
The average is taken.

FIG. 2A is a circuit diagram of the digital low-pass filter of the equation (1). In this circuit configuration example, the input signal x _n input from the input terminal 51 is multiplied by a coefficient of 1 / n by the first coefficient multiplier 53 to be (1 / n) x _n . The signal of (1 / n) _xn is input to the adder 55. At the same time, the signal y _n-1 delayed by one cycle of the sampling time by the delay unit 59 is
The second coefficient multiplier 61 multiplies the coefficient by (n−1) / n to obtain ｛(n−1) / n｝ yn ₋₁ , which is input to the adder 55. These two signals is the output signal y _n are added by the adder 55. Then, the output signal y _n is outputted from the output 57.

(Design Example 2 of Digital LPF) The components of the baseband signal related to information transmission can be regarded as alternating current. Therefore, the DC component included in the baseband signal can be detected by taking the sum of the baseband signals oscillating in time. For example, in a digital LPF, an input signal sequence is {x _n },
The output signal sequence {y _n}, when the number of the input signal x the sum is N, the relationship between both signals is configured as a non-recursive digital filter that can be represented by the following difference equation (2) You can also.

[0036]

(Equation 1)

The digital LPF represented by the equation (2) is
Each time N times the sampling period elapses, n =
It is configured to take the sum from 0 to n = N. In addition,
In general, the band through which the digital filter represented by the equation (2) passes becomes lower as N increases. Regarding the magnitude of N, the condition described above, that is, D
It is sufficient that the magnitude is large enough to follow the electrical fluctuation due to the temperature change of the C offset.

FIG. 2B is a circuit diagram of the digital low-pass filter of the equation (2). The input signal _xn input from the input terminal 71 is supplied to a delay unit 73 (1)
(2),..., Delayed by the delay unit 73 (N-1), respectively, x _{n− 1} , x _n−2 ,.
_The signal becomes _nN . These signals, the output y _n are added are inputted to the adder 75. Then, the output signal y _n is outputted from the output 77.

The feedback circuit 41 performs feedback for reducing a DC offset by using the DC component obtained as described above. Therefore, the feedback point of the feedback circuit 41 is a point before the branch point and a circuit point after the demodulation unit 33 and downstream. In FIG. 1A, the range in the circuit where the feedback point is provided is indicated by an arrow t. And which point in the range this return point should be
It can be set arbitrarily according to the design. Therefore, the feedback circuit 41 branched from the logic circuit 37 feeds back this DC component to the element which is the source of the DC offset, and controls the element directly to reduce the DC offset. The configuration of the mold may be used. Alternatively, the feedback circuit 41 may have a subtraction type configuration in which the DC component is fed back to a point in the circuit where the DC offset is generated, and is subtracted from the DC offset at that point, thereby reducing the DC offset.

As described above, in the receiver, the feedback circuit 41 returns to the above-described A / D converter.
A point in the circuit closer to the receiving unit 31 than a point where the feedback circuit between the conversion unit 19 and the digital signal processing unit 21 branches may be used. In this case, a DC component is detected at the starting point of the feedback circuit near the output unit, and the DC component is fed back to the receiving unit side from the starting point, for example, control is performed to reduce the DC component. As a result, a DC component that could not be completely reduced by one control can be fed back again to perform control to reduce the DC component. Therefore, control for further reducing the DC offset generated in the RF circuit becomes possible.

The DC component extracted by the digital LPF 39 is represented as a digital signal. In the above two configurations, that is, both the control type configuration and the subtraction type configuration, the DC component may be used as a digital signal as it is, or may be used after being converted into an analog signal.

For example, the above-mentioned feedback circuit can be realized by a configuration in which a simple circuit is added to such a digital LPF. That is, the feedback circuit compares a low-band output signal, which is a digital signal extracted from the baseband signal by the digital LPF, with an output value (the above-described predetermined reference value) to be ideally realized. A configuration may be adopted in which a 1-bit digital signal depending on the magnitude relation is output. Then, a control signal corresponding to the magnitude relationship may be fed back to the RF circuit or the logic circuit as a digital signal to control the elements constituting them. As described above, the feedback for reducing the DC offset can be easily performed simply by using the simple additional circuit for the digital LPF.

Needless to say, in this application, the term “receiver” is used merely as a generic term for a means for receiving. Therefore, it is clear that the same effect can be expected for a widely used transceiver by providing the receiving circuit having the feedback circuit as described above.

(First Embodiment) Here, a first embodiment will be described. The receiver according to the first embodiment is one mode included in the receiver described in the above embodiment.

FIG. 3A is a block diagram schematically showing the configuration of the receiver of this embodiment. In this receiver, a characteristic part of the receiver described in the above embodiment will be described. The features of this receiver are
The D / A converter 43 is provided in the feedback circuit 41 as a subsequent stage of the digital LPF 39. Therefore, the DC component extracted by the digital LPF 39
The digital signal is converted into an analog signal by the / A converter 43. Further, the feedback circuit 41 is a circuit that feeds back the analog component DC component as a control signal to a feedback point, that is, the A / D converter 19.

In this receiver, the DC component extracted by the digital LPF 39 is converted from a digital signal into an analog signal, and then converted into a control signal for controlling the A / D conversion section 19, and transmitted to the A / D conversion section 19. It is configured to return. Therefore, as already described, DC
Since the A / D converter 19 that can be a source of the offset can be directly controlled, the DC offset can be efficiently reduced.

The digital LPF 39 used in the first embodiment can be the digital LPF described in the previous embodiment. Also, the D / A converter 4
Reference numeral 3 may be a configuration used for ordinary digital / analog conversion, such as a D / A converter 23 for converting an output from the digital signal processor 21 into an analog signal,
The following simplified configuration may be adopted.

For example, the D / A converter 43 converts the digital signal output from the digital LPF 39 into a PD signal.
It is preferable that the signal modulated by M (pulse density modulation) is smoothed by an analog low-pass filter.

Here, the case where the baseband signal from the digital LPF 39 is subjected to PDM by the D / A converter 43, smoothed by an analog low-pass filter, and then fed back as a signal for controlling the A / D converter 19 Will be described. In particular, here, the A / D converter 19 that performs A / D conversion based on the supplied reference potential as described in the above embodiment will be described.

FIGS. 3B and 3C show how signals are converted in a D / A converter that performs PDM. When the DC component extracted by the digital LPF 39 is larger than an expected value (predetermined reference value), the PDM modulates the DC component into a pulse having a large pulse duty ratio. It has a configuration. That is, as shown in FIG. 3B, when a DC offset V _OFFSET occurs due to the fact that the reference potential V _BAS in the A / D converter 19 is higher than the reference potential V _REF (see FIG. )-(A)), digital LPF3
The digital signal extracted by 9 is subjected to modulation such that the H section of the PDM waveform becomes large and the L section becomes small (FIG. 3 (B)-(b)).
Note that the H section indicates a temporal section in which the pulse has a convex shape in a pulse having a high / low value (convex and concave). Similarly, the L section indicates a time section in which the pulse takes a concave shape in a pulse having high and low values (convex and concave). Then, the obtained PDM waveform is smoothed by an analog low-pass filter (FIGS. 3B to 3C). Thereby, the voltage can be increased. The increase in the voltage can be used as a signal for directly increasing the value of the reference potential V _REF of the A / D converter 19 and controlling it to become the reference potential V _BAS (FIG. 3B- (d)). )). Note that the pulse duty ratio is given by the ratio between the convex portion and the concave portion of the pulse.

Conversely, when the DC component is smaller than an expected value (predetermined reference value), the DC component is modulated so that the pulse has a small pulse duty ratio. That is, as shown in FIG.
When the DC offset V _OFFSET is generated due to the fact that V _BAS is smaller than V _REF in the / D converter 19 (FIG. 3C- (a)), the digital signal extracted by the digital LPF 39 is Modulation is performed so that the H section of the PDM waveform becomes smaller and the L section becomes larger (FIG. 3 (C)-(b)). Then, as described above, the obtained PDM waveform is smoothed by an analog low-pass filter (FIGS. 3C to 3C). As a result, an output that reduces the voltage can be performed (FIGS. 3C to 3C). This voltage decrease can be used as a signal for directly controlling the reference potential V _REF of the reference potential generation circuit inside the A / D converter 19 (FIG. 3C- (d)). )). As the above-mentioned analog low-pass filter, it is also possible to use an integrating circuit composed of a simple LC circuit as conventionally known.

As already described, the control signal is
It reflects a deviation from a predetermined reference value, that is, a DC offset component. Such a control signal is
The signal may indicate the magnitude (for example, the magnitude of the voltage) and the shift direction (positive or negative of the voltage), or may be a signal that detects only the shift direction.

Such a reference potential generating circuit is a kind of a voltage stabilizing circuit for supplying a stable voltage. Such a voltage stabilizing circuit having a structure using feedback has been widely used. Feedback circuit 41 described above
Control of a reference potential generating circuit (voltage stabilizing circuit) having a unique feedback system by a control signal from the control system, for example, a control system capable of adjusting the height of the reference potential simply in proportion to the control signal May be added to the reference potential generation circuit.

As described above, the feedback circuit 41 converts the DC component extracted by the digital LPF 39 into an analog signal by the D / A converter 43 having a simple structure, and then controls the reference potential in the A / D converter. You can make it go back as you do. This makes it possible to more easily and accurately reduce the DC offset. Also,
When performing PWM or the like, it can be performed in the same manner as in the case of the PDM described above.

(Second Embodiment) Next, a second embodiment will be described. The receiver according to the second embodiment is one mode included in the receiver described in the above embodiment.

FIG. 4A is a block diagram schematically showing the configuration of the receiver of this embodiment. In this receiver, only the characteristic features of the receiver described in the above embodiment will be described. As a characteristic portion of this receiver, the feedback circuit 41 includes a digital LPF 39 and an adder / subtractor 45 connected to a subsequent stage. This adder / subtracter is connected to the digital LPF 3 inside the logic circuit 37.
It is provided between 9 and the branch point. Therefore, the feedback point of the feedback circuit 41 is an intermediate point between the digital LPF 39 and the branch point. This configuration converts the low-band signal of the digital representation extracted by the digital LPF 39 to A
The adder / subtractor 45 subtracts the digital signal from the baseband signal converted by the / D converter 19.

This subtraction is performed by the digital LPF 39
The DC component extracted by the above is compared with a value to be ideally realized, and only the DC offset component may be subtracted. The adder / subtractor 45 may be configured to subtract components fed back before the digital signal processing unit 21 in the logic circuit 37 performs signal processing.

As described above, the DC component extracted by the digital LPF 39 is closed and fed back to the logic circuit 37 as a digital signal. Therefore, D / D required in the receiver according to the first embodiment described above is required.
The A converter 43 (see FIG. 3A) can be omitted. Further, since wiring of the feedback circuit 41 to the RF circuit 35 is not required, noise can be reduced.

(Third Embodiment) Next, a third embodiment will be described. The receiver according to the third embodiment is one mode included in the receiver described in the above embodiment.

FIG. 4B is a block diagram schematically showing the configuration of the receiver of this embodiment. In this receiver, a characteristic part of the receiver described in the above embodiment will be described. The features of this receiver are
As in the first embodiment, a D / A converter 43 is provided in the feedback circuit 41 as a subsequent stage of the digital LPF 39. Therefore, the DC component extracted by the digital LPF 39 is converted by the D / A converter 43 into
It is converted from a digital signal to an analog signal. Furthermore,
In this embodiment, unlike the first embodiment, the feedback circuit 41
Is a circuit for feeding back the DC component, which has been converted into an analog signal, to the demodulation unit 33 as a control signal.

In this receiver, the DC component extracted by the digital LPF 39 is converted from a digital signal to an analog signal, and then fed back to the demodulation unit 33 as a control signal for controlling the demodulation unit 33. I have. Therefore, since the demodulation unit 33 that can be a source of the DC offset can be directly controlled, the DC offset can be efficiently reduced.

The digital LPF used in the third embodiment can be the digital LPF described in the first embodiment. Also, the D / A converter is
A configuration used for ordinary digital / analog conversion, such as a D / A converter for converting an output from the digital signal processing unit to an analog signal, may be used. Or D / A
The converter may be configured to control using the signal modulated by PWM or PDM described in the first embodiment.

As for the control of the demodulation unit, various methods are conceivable as in the control of the A / D conversion unit in the first embodiment. For example, when the demodulation unit demodulates a modulated wave, the demodulation unit needs to input a signal for demodulation from a local oscillator or the like (see FIG. 5 having a conventional configuration).
The control may be performed by controlling the voltage of the local oscillator.

[0064]

As is apparent from the above description, according to the receiver of the present invention, the feedback circuit having the digital LPF is provided by branching from the path from the A / D converter to the digital signal processor. This feedback circuit performs feedback using the DC component extracted by the digital LPF. Therefore, it is possible to perform appropriate feedback according to the magnitude of the DC component that directly reflects the DC offset, and it is possible to reduce the DC offset. Further, since the DC offset compensation is performed by the digital circuit, the number of components can be reduced, the size of the device can be reduced, and the aging of the compensation function does not change as compared with the case where the DC offset compensation is performed by the analog circuit.

According to the receiver of the present invention, D / A
A converter is provided in the feedback circuit as a subsequent stage of the digital LPF, and a DC component extracted by the digital LPF is converted into an analog DC component by the D / A converter, and the feedback circuit controls the analog DC component. It is a circuit that feeds back the signal to the A / D converter. Therefore, after the DC component directly reflecting the DC offset is converted into an analog signal by the D / A converter, feedback for controlling the A / D converter that can be a source of the DC offset is performed. it can. Thereby, the DC offset generated in the A / D converter can be effectively reduced.

According to the receiver of the present invention, D / A
A converter is provided in the feedback circuit as a subsequent stage of the digital LPF, and a DC component extracted by the digital LPF is converted into an analog DC component by the D / A converter, and the feedback circuit converts the analog DC component. It is a circuit that feeds back to the demodulation unit as a control signal.
Therefore, after the DC component directly reflecting the DC offset is converted into an analog signal by the D / A converter, it is possible to perform control feedback to a demodulation unit that can be a source of the DC offset. Thereby, the DC offset generated in the demodulation unit can be effectively reduced.

According to the receiver of the present invention, the DC component extracted by the digital LPF is used as it is as the digital DC component, and the feedback circuit converts the digital signal into a digital signal by the A / D converter. The digital DC component is subtracted from the band signal and fed back into the logic circuit. Therefore, it is possible to reduce the DC offset included in the digitalized baseband signal. Further, unlike the above-described configuration, since the circuit is closed in the logic circuit, the DC offset can be reduced without generating noise due to the connection between the RF circuit and the logic circuit.

According to the receiver of the present invention, the digital LPF is a digital LPF that averages and outputs the input baseband signal. Therefore,
The DC offset can be reduced by using a digital LPF that can be realized by a simple program of averaging.

[Brief description of the drawings]

FIG. 1 is a diagram provided for explanation of an embodiment.

FIG. 2 is an exemplary circuit diagram of the digital low-pass filter according to the embodiment;

FIG. 3 is a diagram provided for description of a first embodiment;

FIG. 4 is a diagram provided for explanation of second and third embodiments.

FIG. 5 is a diagram of a receiver having a conventional configuration.

[Explanation of symbols]

 11: Antenna 13: Mixer 15: Local Oscillator 17: Wavelength Discriminator 19: A / D Converter 21: Digital Signal Processor 23: D / A Converter 25: Output 27: FM Demodulator 31: Receiver 33: Demodulation unit 35: RF circuit 37: Logic circuit 39: Digital low-pass filter 41: Feedback circuit 43: D / A converter 45: Adder / subtractor 51, 71: Input terminal 53: First coefficient multiplier 55, 75: Adder 57 , 77: output terminal 59: delay device 61: second coefficient multiplier 73 (1) to 73 (N-1): delay device

Claims (5)

[Claims] 1. A receiving unit that receives a modulated wave that has been subjected to analog modulation, a demodulation unit that demodulates the modulated wave into a baseband signal that is an original analog signal, and an A that converts the baseband signal into a digital signal. / D conversion unit, a digital signal processing unit for performing desired digital signal processing on the baseband signal converted into a digital signal, and a D / A conversion for converting a digital signal output from the digital signal processing unit into an analog signal And an output unit for externally outputting an analog signal from the D / A conversion unit, comprising: a connection midpoint (referred to as a branch point) between the A / D conversion unit and the digital signal processing unit; A feedback circuit connected to a circuit point (referred to as a feedback point) after the demodulation section and upstream of the branch point and including a digital low-pass filter; Cage, said feedback circuit uses the DC component extracted by said digital low-pass filter, the receiver, which is a circuit for performing feedback to reduce the DC offset. 2. The receiver according to claim 1, wherein a D / A converter is provided in the feedback circuit as a stage subsequent to the digital low-pass filter, and the DC component is converted into an analog DC signal by the D / A converter. Wherein the feedback circuit is a circuit that feeds back the analog DC component as a control signal to the A / D converter. 3. The receiver according to claim 1, wherein a D / A converter is provided in the feedback circuit as a subsequent stage of the digital low-pass filter, and the DC component is converted into an analog DC signal by the D / A converter. A receiver, wherein the feedback circuit is a circuit that feeds back the analog DC component as a control signal to the demodulation unit. 4. The receiver according to claim 1, wherein the DC component is used as a digital DC component, and the feedback circuit converts the baseband signal converted into a digital signal by the A / D converter. A receiver characterized in that it is a circuit for feeding back the logic DC circuit so as to subtract the digital DC component. 5. The receiver according to claim 1, wherein the digital low-pass filter is a digital low-pass filter that averages and outputs the input baseband signal. Receiver.