JP2000058849A - Thin film semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower costs of a capacitive load drive device such as an AC drive PDP or the like and contrive to operate at a high speed. SOLUTION: A high voltage output buffer circuit is constituted by a CMOS circuit composed of a both-side sub-gate poly-SiTFT, and also the both-side sub-gate structural TFT is provided together with a drain electrode 6 with respect to a gate electrode 2 and each of sub-gate electrodes 7, 8 in a direction of a source electrode 5, and the length LS2 of a channel formed by the sub-gate electrode 8 located on a side of the source electrode 5 out of the sub-gate electrodes 7, 8 is set shorter than a length LS1 of a channel formed by the sub-gate electrode 7 located on a side of the drain electrode 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film semiconductor device, and more particularly to an AC-driven plasma display (hereinafter referred to as PD).
The present invention relates to a thin-film semiconductor device used for driving a matrix display or the like that requires high-voltage operation, such as P (abbreviated as P) or an electroluminescent display (hereinafter abbreviated as EL).

[0002]

2. Description of the Related Art A liquid crystal display, PDP, or E
Flat panel displays such as L have already appeared in the world. In recent years, in particular, the screen of PDPs has become larger,
CRTs such as 40 and 50 inches, which are not technically possible with CRTs, have been put into practical use.
It has attracted great expectations as a display replacing T. However, on the other hand, it is still more expensive than CRTs, and the fact is that significant cost reduction is required to spread PDPs to ordinary households.

[0003] Light emitting cells are arranged in a matrix in a PDP, and there are an AC driving type and a DC driving type as a method for driving these cells to emit light. Among them, the AC type is currently the mainstream. FIG. 10 is a block diagram showing a configuration of a panel of an AC drive type PDP and a drive circuit portion thereof. The PDP panel 21 is k × n
A glass plate on which the data electrodes 22 are formed;
3 and a glass plate formed with L × m sustain electrodes 24 are bonded to each other and sealed. A space region surrounded by these three types of electrodes is a light emitting cell, and adjacent cells are separated by a partition. A mixed gas composed of a rare gas or the like is sealed in the cell,
By applying a voltage to these electrodes, a discharge occurs inside the cell to emit light. Note that all the electrodes are isolated from the discharge space by the insulating layer.
The DP panel 21 becomes a capacitive load, and discharge is performed only in a transient state in which electric charges are charged from the drive circuit to the capacitance. This is why it is called the AC drive type. Output terminals D1 to Dkn of data drivers 25a to 25k are connected to k × n data electrodes 22, and output terminals S1 to SLm of scan drivers 26A to 26L are connected to L × m scan electrodes 23. Have been. A sustain pulse generator 27 is connected to the L × m sustain electrodes 24,
Further, the sustain pulse generator 27 is connected to the power input terminals of the scan drivers 26A to 26L via a changeover switch (not shown).
Is connected. In the above configuration, the data drivers 25a to 25k and the scanning drivers 26A to 26L have already been integrated.

In the PDP, one field of a screen is divided into a plurality of subfields in order to display a halftone image. FIG. 12 is a driving waveform diagram of each section of the PDP shown in FIG. 10 in one subfield period. First, in the writing period, each of the scan electrodes S from the scan drivers 26A to 26L is used.
Scan pulse signals (amplitude Vs-Vb =
-80 to -90 V) are sequentially applied, and in synchronization with this, the data electrodes D1 to Dk are supplied from the data drivers 25a to 25k.
A data pulse signal as a display signal is applied to n. As a result, a display signal is applied to the cell on the intersection between each data electrode 22 and the selected scanning electrode 23, and the PDP panel 2 is scanned by scanning all the scanning electrodes 23.
The display signal is written to all the cells of No. 1. The output drive voltage VD of the data pulse signal takes a binary value between the high-potential power supply Vdd (= 60 to 80 V) and the low-potential power supply Vss, and the write information is held in each cell.

Next, in the sustain period, the sustain pulse generator 27
, A common continuous sustain pulse (amplitude Vc−Vss = −160 to −180 V) is applied to all the sustain electrodes 24. For all the scanning electrodes 23, by switching a changeover switch (not shown) connected to the power supply input terminals of the scanning drivers 26 A to 26 L to the sustain pulse generator 27 side, all the scans from the sustain pulse generator 27 are performed. A common continuous sustain pulse is applied to the electrode 23. However, the sustain pulse applied to the scan electrode 23 has a phase opposite to that of the sustain pulse applied to the sustain electrode 24. In this sustain period, Vdd is applied to data electrode 22 in the writing period.
Only the cells to which the level signal has been written emit a light to emit light. In addition, since the number of times of light emission of the cell changes by changing the number of continuous output pulses of the sustain pulse for each subfield, the light emission luminance visually looks like a change, and halftone display is possible.

Lastly, in the pre-discharge period, a pre-discharge pulse and a pre-discharge erase pulse are applied to all scan electrodes 23 and all sustain electrodes 24 to erase the data pulse signal held in each cell. , To the next one subfield period.

In the above-described series of operations, the display signal to be applied to each data electrode 22 is input to the data drivers 25a to 25k as logic signals of DAT1 to DATk from outside the range shown in FIG.

FIG. 11 shows data drivers 25a to 25a.
It is a block diagram which shows the internal structure of k. In the figure,
The n-bit shift register 28 synchronizes with the clock pulse CLK and outputs the serial display signal DAT
k are sequentially fetched and converted into parallel signals Q1 to Qn. The n-bit latch 29 outputs these parallel signals Q1-
After taking in Qn, the parallel signals S1 to Sn are output at the same timing at the timing of the latch signal LE synchronized with the scanning pulses 1 to Lm shown in FIG. The signal processed so far is a low-voltage logic signal having an amplitude of about 3.3 to 5 V. Next, the level shifter 30 individually converts the levels of the parallel signals S1 to Sn into high-voltage logic signals having an amplitude of 60 to 80 V or more. Then, the output buffer 31 converts the output signal of the level shifter 30 into a large current capacity and outputs it, and drives each data electrode 22.

In the above PDP configuration and operation, the number of display pixels is 1365 × 768 and the number of data electrodes is RGB3 in recent 50-inch class high definition color specifications.
The total number of colors reaches 4095. Since the number of output terminals of generally used data driver ICs and scanning driver ICs is 40 to 96, the number of data driver ICs to be used is as large as 43 to 102. Further, in a high-definition PDP, the processing speed of a display signal in the data driver is increased, and the capacity per data electrode serving as a driver load is also increased. The operating frequency inside the driver can be reduced by adopting a method of dividing the data electrode into two parts at the center of the direction and pulling them up and down and driving them separately, or a method of pulling out every other electrode vertically and driving them separately. , Driving load is reduced. However, if such a method is adopted, the number of data driver ICs used will further increase, and the
This is a major obstacle to reducing the cost of P. Therefore, cost reduction of the data driver IC has become a very important issue.

Here, the device structure of the above-described data driver IC will be described. Although low-voltage and high-voltage logic signals are handled inside the data driver IC, a high-voltage MOSFET is used in the circuit especially for high voltages. Specifically, LDD (Lightly Dope)
d Drain) structure and sub-gate structure.
In any of these methods, a region having the above structure is provided on the drain electrode side so that a potential gradient is provided between the drain end of the channel region below the gate electrode and the drain electrode, thereby reducing the high electric field of the drain. FIG.
FIG. 12 is a cross-sectional view showing an example in which a CMOS inverter circuit is configured using a high-voltage MOSFET having a structure and used as an output buffer 31 in FIG. 11. As an example of the manufacturing process, first, an n-well 1 is formed on a semiconductor substrate 14 by implanting impurity ions.
6, and an N-side low-concentration impurity layer 17 serving as a drain region;
The P-side low concentration impurity layers 18 are sequentially formed. After that, a field oxide film 15 is formed. Next, the N-side gate electrode 2
a and a P-side gate electrode 2b are formed, and then a source-side n-type impurity layer 3a serving as a source region and a protection diode is formed.
A source side p-type impurity layer 3b is formed. Then, after opening the source-side contact 5 and the drain-side contact 6, an N-side source electrode 9 made of a metal thin film of aluminum or the like is formed.
a, a P-side source electrode 9b and a drain electrode 10 are formed. When a CMOS inverter using a high-breakdown-voltage MOSFET is to be manufactured through the above manufacturing steps, the required number of masks PR is 8 PR. However, in an actual driver IC, it is common to form a MOSFET for a low-voltage logic circuit on the same substrate or to perform a connection layout of an internal circuit by two-layer aluminum wiring. The number of mask PRs is at least 10 PR or more.

By the way, the present inventors have discussed the driver I described above.
As one method for meeting the cost reduction demand for C, a thin film transistor (Thin Film Tra) made of polycrystalline silicon (hereinafter abbreviated as poly-Si) is used.
Research for realizing a data driver IC using an nsistor (hereinafter abbreviated as TFT) has been repeated. Previously, a poly-Si thin film was mainly formed at a high temperature of about 1000 ° C., which is similar to a semiconductor manufacturing process. A quartz substrate has been used as a substrate material that can withstand such conditions. However, in recent years, a so-called low-temperature poly-Si thin film that can be formed at a process temperature of 500 ° C. or less has become mainstream, and an inexpensive alkali-free glass substrate can be used as a substrate material. Cost can be reduced. The manufacturing process is amorphous silicon TFT used for liquid crystal display.
Since it can be shared to some extent with a substrate for use, and a substrate having a larger area than a semiconductor substrate can be used, manufacturing costs can be reduced by batch mass production. On the other hand, from the viewpoint of device characteristics, technical development has been particularly advanced recently, and a high-quality low-temperature poly-Si thin film can be obtained.
The mobility as T has been greatly improved. further,
Since the TFTs are formed on an insulating substrate, the TFT elements are completely separated from each other. Therefore, like a MOSFET formed on a conventional semiconductor substrate, a latch-up phenomenon via a parasitic element in the substrate is prevented. It does not occur fundamentally. this is,
In particular, this is a great advantage for a high-voltage IC such as a data driver, and reliability can be improved. further,
For the same reason, since there is no parasitic capacitance between the transistor and the substrate, it is possible to speed up the device operation. For these reasons, the data driver IC of PDP
The possibility of application of a thin film semiconductor device using a poly-Si TFT has been opened.

In order to realize a data driver IC, it is indispensable to commercialize a high breakdown voltage TFT as described above.
A well-known example of a high-breakdown-voltage TFT is a sub-gate TFT, which is disclosed by Tiao-Yuan Huang et al. (“A Simpler 100-V Polysil”).
icon TFT with ImprovedTur
n-ONaracteristics ", IEEE
Electron Device Letters, vo
l. 11, No. 6, June, 1990). FIG. 17 is a sectional view of a conventional sub-gate structure TFT. A poly-Si layer 1 is deposited on an insulating substrate and serves as a channel region. A gate electrode 2 is formed on the poly-Si layer 1 via a first gate insulating layer 12. A second gate insulating layer 11 is further formed on the gate electrode 2, and a second gate electrode 7 is formed thereon.
Are formed. Sub-gate structure TFT with this configuration
Can be regarded as a series connection of a TFT formed under the gate electrode 2 and a TFT formed under the second gate electrode 7. Note that the gate electrode 2 and the second gate electrode 7 slightly overlap. poly-Si
In the layer 1, regions located under these two gate electrodes are non-doped, and a source-side impurity layer 3 and a drain-side impurity layer 4 are formed at both ends thereof. By changing the gate voltage Vg applied to the gate electrode 2, T
FT on / off control is performed. Also, the second gate electrode 7
By applying a predetermined positive bias voltage Vfp to the gate electrode, a potential gradient is provided between the source end and the drain-side impurity layer 4 in the channel region of the TFT formed below the second gate electrode 7 so that the gate is The electric field between the drain end and the source-side impurity layer 3 in the channel region of the TFT formed below the electrode 2 is relaxed. This realizes a high breakdown voltage between the drain and source electrodes as a whole of the sub-gate structure TFT.

FIG. 18 is a circuit diagram reported as an example in which a CMOS inverter circuit is formed using a conventional sub-gate structure TFT. PTFT35 and NTFT36
Are connected to the Vss and Vdd terminals, respectively, so that a constant voltage is applied. Also,
The logic state of the output Vout of the inverter circuit is controlled by applying a gate pulse voltage Vg having an amplitude of Vdd-Vss to each gate electrode. In this example, the gate electrodes of the PTFT 35 and the NTFT 36 are connected in common. However, the present invention is not limited to this, and independent gate voltages may be applied. In this case, the amplitude of each gate voltage may be smaller than Vdd-Vss.

However, there is no case where the above-described sub-gate TFT is applied to a display driving driver IC.

Here, consider the case where an actual PDP is driven. FIG. 13 shows an output buffer of the data driver shown in FIG. 10 which is constituted by TFTs and one circuit is extracted therefrom, and a data electrode Dn, adjacent data electrodes Dn-1, Dn + 1, and a scanning electrode connected thereto. 23 is an equivalent circuit showing a coupling capacitance between the storage capacitor 23 and a storage electrode 24. CD is a coupling capacitance between adjacent data electrodes, Cs is a coupling capacitance between one data electrode Dn and all scan electrodes crossing it, and Cc is a coupling capacitance between one data electrode Dn and all sustain electrodes crossing it. Is the coupling capacity between. When such a coupling capacitance exists, when the driving voltage level of the adjacent data electrode, or the scanning electrode or the sustain electrode changes,
The voltage of the data electrode Dn varies through these coupling capacitors.

FIG. 14 is a waveform diagram showing a state of voltage fluctuation of data electrode Dn during the writing period of the waveform diagram shown in FIG. In FIG. 12, the driving output state of the data electrode Dn becomes Vs in synchronization with the timing at which the driving output state of the scanning driver changes from, for example, FIG.
s, and the data electrode Dn−1 adjacent to Dn,
Assuming a display pattern in which the drive output state of Dn + 1 changes from Vdd to Vss, the drive voltage VDn of the data electrode Dn is originally Vss, but ΔVD in the negative direction.
After the fluctuation of n occurs, the fluctuation voltage is absorbed by Vss via the ON resistance of NTFT 36, and returns to the original voltage. The value of the coupling capacitance in an actual PDP is CD, C
Both s and Cc are about 15 pF. The peak value of the variation voltage ΔVDn at this time is about 30V.

When the voltage fluctuation described above occurs, FIG.
In the NTFT 36, the voltage on the drain electrode side becomes lower than that on the source electrode side. In this case, in the case of the conventional sub-gate structure TFT as described with reference to FIG. 17, if the potential relationship between the drain and source electrodes is reversed, the withstand voltage becomes extremely low because there is no electric field relaxation effect on the source electrode side of the TFT. However, there is a problem that the device is easily broken down to cause device destruction.

To solve this problem, the LD shown in FIG.
In the case of the D-structure high breakdown voltage MOSFET, the source side n-type impurity layer 3
a, by providing the source side p-type impurity layer 3b and forming the output protection diode inside the MOSFET. FIG. 16 shows a MOSFET having a protection diode formed therein.
It is an equivalent circuit diagram of the inverter circuit by T. PFET
A protection diode 34 is inserted between the drain and the source of the NFET 32 and the NFET 33, and when a reverse voltage is applied between the drain and the source, the diode conducts. At this time, since the diode current flows in the direction of the substrate, the current capacity is larger than that of the MOSFET, and most of the current accompanying the reverse voltage passes through the diode, so that the transistor can be prevented from being destroyed.

On the other hand, the poly-Si TFT is formed on an insulating substrate, and the poly-Si layer 1 shown in FIG.
Is generally as thin as 1000 angstroms or less, it is impossible to form a protection diode with an impurity profile in the thickness direction as shown in the sectional view of the high breakdown voltage MOSFET in FIG. Therefore, the protection diode must have a lateral structure and be formed on the substrate as an element independent of the TFT. However, in that case, there is a problem that the element layout area becomes large. And p
The poly-Si thin film has crystal grain boundaries, and therefore has a large leakage current therethrough. Even if a diode is formed, it has a drawback that rectification characteristics are poor, and at present it is difficult to use this as a diode. Therefore, a method of using a separately provided TFT as a protection element by diode connection is generally adopted.

FIG. 19 shows a PTFT protection element 37 and an N-type TFT separately from PTFT 35 and NTFT 36 for an output buffer.
FIG. 3 is a circuit diagram showing an example of a high-breakdown-voltage output buffer provided with a TFT protection element 38. The data electrode of the PDP panel is connected to the output terminal Vout. If the voltage of Vout fluctuates through the above-described coupling capacitance, the fluctuation is absorbed through these protection elements 37 and 38. What you want to do. However, in the configuration of FIG. 19, the necessity of securing the withstand voltage on the drain side of the protection elements 37 and 38 is not different from the case of the output buffer TFTs 35 and 36, so that the sub-gate electrode is inserted on the drain side. However, this has no effect of relaxing the electric field on the source electrode side, and does not solve the problem of element destruction when a reverse voltage is applied between the drain and source.

As a solution to the above problem, a so-called double-sided sub-gate structure in which a sub-gate electrode of the output buffer TFT is newly provided on the source electrode side in addition to the drain electrode side, thereby improving the reverse breakdown voltage between the drain and the source. A method is conceivable.

FIG. 20 is a cross-sectional view of a conventional double-sided sub-gate TFT disclosed in Japanese Patent Application Laid-Open No. 5-251702. A source electrode 9 and a drain electrode 10 made of an aluminum thin film are formed on an insulating substrate 13, and a source-side n-type impurity layer 3 a, a source-side p-type impurity layer 3 b, and a drain-side n-type impurity layer 4 a are further formed thereon. And a drain-side p-type impurity layer 4b. poly-Si
The layer 1 is formed so as to cover the impurity layer, and a gate electrode 2 is formed thereover via a first gate insulating layer 12. Further, the second gate insulating layer 11
A gate electrode 7 and a third gate electrode 8 are formed.

FIG. 21 shows a conventional MOSF having a double-sided sub-gate structure disclosed in Japanese Patent Application Laid-Open No. 5-90587.
It is sectional drawing of ET. A field oxide film 15 is formed on a semiconductor substrate 14, and a first gate insulating layer 12 and a gate electrode 2 are sequentially formed in a region surrounded by the field oxide film 15. Further, a source-side contact 5 and a drain-side contact 6 are opened in the first gate insulating layer 12. And
The second gate electrode 7 and the third gate electrode 8 are formed on the first gate insulating layer 12 with the second gate insulating layer 11 interposed therebetween.

[0024]

SUMMARY OF THE INVENTION A double-sided sub-gate TFT or an M-type TFT disclosed in these publications is disclosed.
The OSFET has a third gate electrode 8 having the same length in the channel direction as the second gate electrode 7 when viewed from the diagram of the invention.
It is described that it has. Therefore, such T
If the FT is used, the reverse breakdown voltage between the drain and the source of the TFT can be secured as much as that in the forward direction. FIG. 5 is a characteristic diagram showing the relationship between the drain current Id and the drain-source reverse voltage −Vds when the bias voltage applied to the sub-gate electrode is constant in the sub-gate structure TFT. In the figure,
(A) The reverse breakdown voltage BVdsa between the drain and the source of the one-sided sub-gate structure is low, but (c) the breakdown voltage is improved like BVdsc by using the both-sided sub-gate structure, which is the forward direction between the drain and the source in the one-sided sub-gate structure. It corresponds to the withstand voltage. However, while the withstand voltage is improved, the on-current is limited. FIG. 6 is an on-current characteristic diagram of a sub-gate structure TFT. In the figure, (c) the on-state current is significantly reduced by using the double-sided sub-gate structure as compared with the single-sided sub-gate structure. Therefore, in order to ensure a desired driving capability as a driver, the size of the output buffer TFT must be increased. Then, there is a problem that the area of the driver IC chip is increased and the cost is increased.

Therefore, the present invention provides a capacitive load driving device,
In particular, it is assumed that the drive voltage of the drive output terminal is fluctuated by the coupling capacity of the load while reducing the cost of the display drive device for driving the AC drive type PDP and the like, and suppressing the reduction in the drive capability caused by the cost. Another object of the present invention is to provide a thin-film semiconductor device capable of preventing element destruction due to breakdown.

[0026]

The present invention for solving the above problems has a P-channel and N-channel thin film transistor (TFT), and a source electrode of the P-channel thin film transistor (PTFT) is connected to a high potential side power supply. The thin film semiconductor device includes a circuit in which a source electrode of an N-channel thin film transistor (NTFT) is connected to a low potential side power supply, and a drain electrode of the PTFT and a drain electrode of the NTFT are commonly connected.

The TFT comprises a polycrystalline silicon (p-Si) layer, a source-side impurity layer formed at one end of the p-Si layer, and a drain-side impurity layer formed at the other end of the p-Si layer. Structure T having a layer and a first gate electrode provided on the p-Si layer via a first insulating layer
The circuit by FT, a polycrystalline silicon (p-Si) layer, a source-side impurity layer formed at one end of the p-Si layer, and a drain-side impurity layer formed at the other end of the p-Si layer; A first gate electrode provided on the p-Si layer via a first insulating layer; and a first gate electrode provided between the first gate electrode and the drain-side impurity layer via a second insulating layer. A circuit having a second structure TFT having a second gate electrode and a third gate electrode provided between the first gate electrode and the source-side impurity layer and provided with the second insulating layer interposed therebetween; A polycrystalline silicon (p-Si) layer; a source-side impurity layer formed at one end of the p-Si layer; a drain-side impurity layer formed at the other end of the p-Si layer; A fourth gate provided through the first insulating layer and the second insulating layer. And a fifth gate electrode provided between the fourth gate electrode and the drain-side impurity layer via a third insulating layer, and a fourth gate electrode and the source-side impurity layer. A third structure T having a sixth gate electrode interposed therebetween with the third insulating layer interposed therebetween.
The circuit by FT, a polycrystalline silicon (p-Si) layer, a source-side impurity layer formed at one end of the p-Si layer, and a drain-side impurity layer formed at the other end of the p-Si layer; A first gate electrode provided on the p-Si layer via a first insulating layer; and a first gate electrode provided between the first gate electrode and the drain-side impurity layer via a second insulating layer. Four types of circuits of a fourth structure TFT having a second gate electrode and a sixth gate electrode located between the first gate electrode and the source side impurity layer and provided with a third insulating layer interposed therebetween And at least one of the circuits is selected.

Further, a sub-gate (third or sixth gate electrode) located between the main gate (first or fourth gate electrode) and the source side impurity layer has a channel length LS2 formed in the p-Si layer. Is made shorter than the length LS1 of the channel formed in the p-Si layer by the sub-gate (second or fifth gate electrode) located between the main gate (first or fourth gate electrode) and the drain-side impurity layer. ing.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a double-sided sub-gate TFT constituting a thin film semiconductor device according to the present invention. As shown in FIG. 1, the thin-film semiconductor device of the present invention includes a polycrystalline silicon (p-Si) layer 1, a source-side impurity layer 3 formed at one end of the p-Si layer 1, and a p-Si layer. A drain-side impurity layer 4 formed at the end and a first gate electrode (Vg) provided on the p-Si layer 1 via a first insulating layer (not shown)
2, a second gate electrode (Vsg1) 7 provided between the first gate electrode (Vg) 2 and the drain-side impurity layer 4 via a second insulating layer (not shown), and a first gate electrode (Vsg1). Vg) A sixth gate electrode (Vg) located between 2 and the source-side impurity layer 3 and provided via a third insulating layer (not shown).
sg2) 8 and the sixth TFT
The length LS2 of the channel formed in the p-Si layer by the gate electrode (Vsg2) 8 is changed to the second gate electrode (Vsg2).
1) Due to 7, the length of the channel formed in the p-Si layer is shorter than the length LS1.

FIG. 2 is a circuit diagram of a thin-film semiconductor device according to the first embodiment of the present invention using the double-sided sub-gate TFT shown in FIG. The source electrode of PTFT 35 is connected to power supply Vdd, and the source electrode of NTFT 36 is Vs
s. On the other hand, the drain electrodes of the TFTs are commonly connected to form an output Vout, and a capacitive load such as a data electrode of a PDP is connected to the load. The signal input terminals are Vgp and Vgn, respectively, which are the gate electrode of PTFT 35 and the gate electrode of NTFT 36.
Is applied. Further, PTFT 35 and N
Vsgp is applied to the sub-gate electrode of the TFT 36, respectively.
1, a bias voltage of Vsgp2, Vsgn1, and Vsgn2 is applied.

When the thin-film semiconductor device having the above structure is used as a data driver for a PDP or the like, when the driving voltage level of the adjacent data electrode, or the scanning electrode or the sustain electrode changes, the coupling capacitance CD between the adjacent data electrodes, one Of the data electrode Dn via the coupling capacitance Cs between the data electrode Dn and all the scanning electrodes crossing the data electrode Dn, or the coupling capacitance Cc between one data electrode Dn and all the sustaining electrodes crossing the data electrode Dn. Assume that the voltage fluctuates by ΔVDn. At this time, in the sectional structure of FIG. 2, the channel length LS2 of the TFT formed below the second sub-gate electrode 8 is LS2 <LS.
1 and the magnitude of the reverse breakdown voltage BVdsb between the drain and the source is BVds> ΔV, as shown in FIG.
LS2 is set within the range where Dn is obtained, and a double-sided sub-gate structure TFT is formed. As a result, FIG.
As shown in (1), the required reverse breakdown voltage between the drain and the source can be secured while suppressing the drain current from decreasing more than in the conventional double-sided sub-gate TFT.

Therefore, according to the present embodiment, the driving capability of the thin film semiconductor device is reduced by the conventional double-sided sub-gate TFT.
, And even if the drive voltage of the drive output terminal fluctuates due to the coupling capacitance of the load, it is possible to prevent element breakdown due to breakdown. As a result, it is possible to reduce the size of the device using the conventional double-sided sub-gate TFT while securing the required breakdown voltage. In addition, since the TFT is formed on an insulating substrate, the TFT elements are completely separated from each other. Therefore, like a conventional MOSFET formed on a semiconductor substrate,
The latch-up phenomenon via the parasitic element in the substrate does not occur fundamentally, and the reliability is improved. Furthermore, since there is no parasitic capacitance between the MOSFET and the semiconductor substrate, if the mobility of the poly-Si thin film is improved to the same level as that of crystalline silicon due to future technology development, the circuit formed by the MOSFET on the semiconductor substrate will not work. Can also be operated at high speed.

FIG. 3 is a circuit diagram of a thin-film semiconductor device according to a second embodiment of the present invention. PTFT35 and NTFT3
6 forms a CMOS inverter circuit. Also, P
The two sub-gate electrodes of the TFT 35 are commonly connected, and apply a bias voltage of Vsgp. NTFT
The bias voltage Vsgn is similarly applied to the two sub-gate electrodes 36. The bias voltage is TFT
Of the voltage between the drain and source electrodes applied to the channel region of the TFT formed under the gate electrode 2 in the poly-Si layer 1 in FIG. Set to be. By adopting the method of applying a bias as in the present embodiment, the types of required bias voltages can be reduced, and the cost of the mounting apparatus including an external power supply can be reduced.

FIG. 4 is a circuit diagram of a thin-film semiconductor device according to a third embodiment of the present invention. In the present embodiment, P
The two sub-gate electrodes of the TFT 35 are commonly connected, and apply Vss as a bias voltage. On the other hand, N
Similarly, Vdd is applied to the two sub-gate electrodes of the TFT 36 as a bias voltage. In this case, since it is not necessary to newly provide a bias voltage source, the cost can be further reduced as a whole of the device on which the thin film semiconductor device of the present invention is mounted. However, of the voltages between the drain and source electrodes applied to the TFT, poly-S in FIG.
The channel length L, the channel length LS1, and the channel length are set so that the voltage divided into the channel region of the TFT formed under the gate electrode 2 in the i-layer 1 is within the breakdown voltage of the channel region. It is necessary to appropriately set the ratio of LS2 and the ratio of the first gate insulating layer 12 and the second gate insulating layer 11.

The right half of FIG. 8 is a sectional view of the thin-film semiconductor device according to the fourth embodiment of the present invention, which is composed of a TFT formed by a high breakdown voltage N-side gate electrode 19a and a high breakdown voltage P-side gate electrode 19b. Insulating substrate 1 such as non-alkali glass
A poly-Si layer 1 is formed on 3, and a source-side n-type impurity layer 3 a and a drain-side n-type impurity layer 4 a are formed at both ends of the poly-Si layer 1 serving as NTFT at both ends thereof. Similarly, a source side p-type impurity layer 3b and a drain side p-type impurity layer 4b are formed on the PTFT side. Then, a high-breakdown-voltage N-side gate electrode 19a and a high-breakdown-voltage P-side gate electrode 19b are formed thereon with a first gate insulating layer 12 interposed therebetween, and the second gate insulating layer 11 and the third gate A sub-gate electrode 7 and a sub-gate electrode 8 are formed on both sides of the gate electrodes 19a and 19b with the insulating layer 20 interposed therebetween. Further, the source-side n-type impurity layer 3a, the drain-side n-type impurity layer 4a, the source-side p-type impurity layer 3b, and the drain-side p-type impurity layer 4
Above b, a source-side contact 5 and a drain-side contact 6 are opened, and a source electrode 9 and a drain electrode 10 are drawn out from the openings. here,
Channel length L of TFT formed below sub-gate electrode 8
S2 is shorter than the channel length LS1 of the TFT formed below the sub-gate electrode 7. When the N- and P-sided sub-gate structure TFTs are to be formed by the above-described procedure, the required number of masks PR is 6 PR, and the N and P LDD structure high breakdown voltage MOSFETs are formed on the semiconductor substrate.
Is formed, the number of masks PR can be reduced as compared with the case of forming. Therefore, the conventional LDD structure high breakdown voltage MOSFE
The cost can be lower than T.

FIG. 7 is a sectional view of a thin-film semiconductor device according to a fifth embodiment of the present invention. PDP Data Driver I
When trying to configure C, a low voltage logic circuit,
And the high voltage circuit must be formed on the same substrate. A poly-Si layer 1 is formed on an insulating substrate 13, and an N-side gate electrode 2 a and a P-side gate electrode 2 b of a low-voltage logic circuit TFT are formed thereon via a first gate insulating layer 12. Have been. Poly- to be NTFT
A source-side n-type impurity layer 3a and a drain-side n-type impurity layer 4a are formed at both ends of the Si layer 1, and a source-side p-type impurity layer 3b and a drain-side p-type impurity layer 4b are similarly formed on the PTFT side. Is formed. And on top of it is the second
The source-side contact 5 and the drain-side contact 6 are opened through the gate insulating layer 11, and the source electrode 9, the drain electrode 10, the high-breakdown-voltage N-side gate electrode 19a, and the high-breakdown-voltage P-side gate electrode 19b are simultaneously formed thereon. Have been. On these electrodes, a sub-gate electrode 7, a sub-gate electrode 8, and an upper wiring layer 40 are simultaneously formed via a third gate insulating layer 20, and if necessary, a second gate insulating layer 20 is formed on the third gate insulating layer 20. By opening the contact 40, an electrical connection with the lower wiring can be obtained. Here, the channel length of the TFT formed below the second sub-gate electrode 8 is shorter than the channel length of the TFT formed below the sub-gate electrode 7. According to the present embodiment, the TFT for forming the low-voltage logic circuit can be formed on the same substrate together with the double-sided sub-gate structure TFT forming the thin film semiconductor device of the present invention. The chip size can be reduced by increasing the integration of the driver IC. Further, the number of mask PRs required for manufacturing is only 8 PR. Therefore, the manufacturing cost can be reduced as compared with the MOSFET formed on the semiconductor substrate. Furthermore, according to the present embodiment, the gate insulating layers of the double-sided sub-gate structure TFT can be made thicker, so that the gate electrodes 19a and 19b can be driven by a high-voltage logic signal, which constitutes an output buffer circuit. The driving capability of the double-sided sub-gate structure TFT can be improved.

FIG. 8 is a sectional view of a thin film semiconductor device according to a sixth embodiment of the present invention. Po on the insulating substrate 13
The ly-Si layer 1 is formed, and the poly-
A source-side n-type impurity layer 3a and a drain-side n-type impurity layer 4a are formed at both ends of the Si layer 1, and a source-side p-type impurity layer 3b and a drain-side p-type impurity layer 4b are similarly formed on the PTFT side. Is formed. On top of them, through the first gate insulating layer 12, the N of the TFT for the low-voltage logic circuit is set.
Side gate electrode 2a, P side gate electrode 2b, and high breakdown voltage N
The side gate electrode 19a and the high breakdown voltage P side gate electrode 19b are formed simultaneously. A source-side contact 5 and a drain-side contact 6 are opened in the upper part via the second gate insulating layer 11, and the source electrode 9 is further formed on the upper part.
A drain electrode 10 is formed. On these electrodes, a sub-gate electrode 7, a sub-gate electrode 8, and an upper wiring layer 40 are simultaneously formed via a third gate insulating layer 20, and if necessary, a second gate insulating layer 20 is formed on the third gate insulating layer 20.
By opening the contact 40, an electrical connection with the lower wiring can be obtained. According to the present embodiment, the double-sided sub-gate structure T constituting the thin-film semiconductor device of the present invention is provided.
Together with FT, T for configuring a low-voltage logic circuit is used.
The FT can also be formed on the same substrate, and the chip size can be reduced by the high integration of the data driver IC. Further, the number of mask PRs required for manufacturing is only 8 PR. Therefore, the manufacturing cost can be reduced as compared with the MOSFET formed on the semiconductor substrate. further,
According to the present embodiment, the gate electrodes 19a and 19b of the double-sided sub-gate TFT can be driven by a low-voltage logic signal, so that the configuration of the circuit for driving the gate electrode of the output buffer circuit is simplified. be able to.

FIG. 9 is a sectional view of the thin-film semiconductor device according to the seventh embodiment of the present invention. In the present embodiment, the gate electrode 19a of the NTFT of the two-sided sub-gate structure TFT is used.
Are formed simultaneously with the gate electrodes 2a and 2b of the low-voltage logic TFT, and the gate electrode 19b of the PTFT of the two-sided sub-gate TFT is formed simultaneously with the source electrode 9 and the drain electrode 10. According to the present embodiment, a TFT for forming a low-voltage logic circuit can be formed on the same substrate together with a double-sided sub-gate structure TFT forming the thin-film semiconductor device of the present invention. It is possible to reduce the chip size by the integration. The number of mask PRs required for manufacturing is 8 PR
Only needs to be done. Therefore, the MOSFE formed on the semiconductor substrate
The manufacturing cost can be reduced as compared with T. Further, according to the present embodiment, for example, a combination of driving the gate electrode 19a of the NTFT with a low-voltage logic signal and driving the gate electrode 19b of the PTFT with a high-voltage logic signal becomes possible. The degree of freedom for the circuit design of the level shifter to be driven can be improved. The configuration of this embodiment is PT
The same can be realized when the FT and the NTFT are exchanged.

In the above embodiment, the source-side n-type impurity layer 3a, the drain-side n-type impurity layer 4a, the source-side p-type impurity layer 3b, and the drain-side p-type impurity layer 4b of the low-voltage logic circuit TFT are formed. At the time of formation, the N-side gate electrode 2a and the P-side gate electrode 2b are used as shielding layers, and impurities are introduced from above the substrate, whereby the TFT for a low-voltage logic circuit can have a self-aligned structure. Thus, the overlap capacitance between the gate electrode and the drain electrode and between the gate electrode and the source electrode can be reduced, so that the low-voltage logic circuit can operate at high speed. Also in this case, the number of masks PR required for manufacturing the device does not increase in each of the above embodiments, and the advantage of cost reduction can be fully utilized.

According to the data driver IC configured using the thin film semiconductor device of the present invention as described above, the device structure of the TFT is arbitrarily combined so as to be most suitable for the circuit configuration of the designed high-voltage logic circuit. It can be used, and the degree of freedom in circuit design is greatly improved.
In addition, no matter which combination is used, the number of mask PRs required for manufacturing a device is still 8 PR,
It is possible to make full use of the advantage of cost reduction.

Although it is advantageous to use an alkali-free glass as the insulating substrate used in the above embodiments in order to reduce the cost, an opaque ceramic insulating substrate or an insulating layer is formed on the surface of the semiconductor substrate. It is also possible to configure the display driving device of the above-described embodiment by using the one formed with.

Further, in the above embodiment, although not shown in the figure, the level shifter 30 described in the block diagram of FIG. 11 is not affected by the drive voltage fluctuation via the coupling capacitance of the load. A one-sided sub-gate structure TFT as described above may be used. Also in this case, the number of manufacturing steps does not increase at all with respect to the thin film semiconductor device of the present invention described above, and the advantage of cost reduction can be fully utilized.

[0044]

According to the first embodiment of the present invention described above, the drive capability of the thin-film semiconductor device is reduced by the coupling capacitance of the load while reducing the reduction of the drive capability as compared with the case of using the conventional double-sided sub-gate TFT. Even if the drive voltage of the output terminal fluctuates, it is possible to prevent element breakdown due to breakdown. This has the effect that it is possible to reduce the size of the device using the conventional double-sided sub-gate TFT while securing the required breakdown voltage.

Further, since the TFT is formed on the insulating substrate, the TFT elements are completely separated from each other. Therefore, like a MOSFET formed on a conventional semiconductor substrate, the TFT is formed through a parasitic element in the substrate. The latch-up phenomenon does not occur fundamentally, and has the effect of improving reliability.

Further, since there is no parasitic capacitance between the MOSFET and the semiconductor substrate as in the case of the MOSFET, p.
If the mobility of the poly-Si thin film is improved to the same level as that of crystalline silicon, there is an effect that the operation can be performed at a higher speed than a circuit constituted by MOSFETs on a semiconductor substrate.

Further, according to the thin-film semiconductor device of the second embodiment of the present invention, the types of bias voltage required are small, so that the cost of the mounting device including the external power supply can be reduced. Having.

Further, according to the thin-film semiconductor device according to the third embodiment of the present invention, it is not necessary to newly provide a bias voltage source, so that the cost as a whole including the thin-film semiconductor device of the present invention is further reduced. Is possible.

Further, according to the thin-film semiconductor device according to the fourth embodiment of the present invention, both sides of the N and P sub-gate structures T
When an FT is to be formed, the required number of masks PR is 6
PR, so that the number of masks PR can be reduced as compared with the case where N and P LDD structure high breakdown voltage MOSFETs are formed on the semiconductor substrate. Therefore, there is an effect that the cost can be reduced as compared with the conventional LDD structure high breakdown voltage MOSFET.

Further, according to the thin-film semiconductor device according to the fifth embodiment of the present invention, a TFT for forming a low-voltage logic circuit can be formed on the same substrate together with a double-sided sub-gate structure TFT. The chip size can be reduced by increasing the degree of integration of the formed data driver IC. Further, the number of mask PRs required for manufacturing is only 8 PR. Therefore, the MO formed on the semiconductor substrate
This has the effect that the manufacturing cost can be reduced as compared with the SFET. Furthermore, according to the present embodiment, it is possible to drive the gate electrodes of the two-sided sub-gate structure TFT with a low-voltage logic signal, thereby simplifying the configuration of the circuit for driving the gate electrodes of the output buffer circuit. It has the effect that can be done.

According to the thin-film semiconductor device of the sixth embodiment of the present invention, the gate insulating layer of the double-sided sub-gate TFT can be made thicker.
a and 19b can be driven by a high-voltage logic signal, which has the effect of improving the drive capability of the double-sided sub-gate TFTs constituting the output buffer circuit.

According to the thin-film semiconductor device of the seventh embodiment of the present invention, for example, a combination of driving the gate electrode of the NTFT with a low-voltage logic signal and driving the gate electrode of the PTFT with a high-voltage logic signal is possible. Thus, the degree of freedom in circuit design of the level shifter for driving the gate electrode of the output buffer circuit can be improved.

Further, in the thin-film semiconductor device of the present invention, the TFT for the low-voltage logic circuit has a self-aligned structure, so that the low-voltage logic circuit can operate at high speed, and the number of masks PR required for manufacturing the device can be increased. Is 8
There is no change in PR, and there is an effect that the advantage of cost reduction can be fully utilized.

Further, according to the thin-film semiconductor device of the present invention, the use of low-cost members, the mass-production effect of a large-area substrate, and the reduction of the number of PRs in the manufacturing process can be achieved as compared with the conventional semiconductor device having a MOSFET formed on a semiconductor substrate. Can reduce the cost of the device, and the reliability is not fundamentally reduced due to the latch-up phenomenon via the parasitic element in the substrate.Furthermore, there is no parasitic capacitance between the semiconductor substrate and high-speed operation It has an excellent effect that it can be converted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a double-sided sub-gate TFT constituting a thin film semiconductor device of the present invention.

FIG. 2 is a circuit diagram of the thin-film semiconductor device of the present invention.

FIG. 3 is a circuit diagram showing an embodiment of the thin-film semiconductor device of the present invention.

FIG. 4 is a circuit diagram showing another embodiment of the thin-film semiconductor device of the present invention.

FIG. 5 is a characteristic diagram showing a relationship between a drain current and a reverse voltage between a drain and a source in a sub-gate TFT.

FIG. 6 is an ON-current characteristic diagram of a sub-gate structure TFT.

FIG. 7 is a sectional view showing an embodiment of a device structure of a data driver IC using the thin film semiconductor device of the present invention.

FIG. 8 is a sectional view showing another embodiment of the device structure of the data driver IC using the thin film semiconductor device of the present invention.

FIG. 9 is a sectional view showing another embodiment of the device structure of the data driver IC using the thin film semiconductor device of the present invention.

FIG. 10 is a block diagram showing a configuration of a panel of an AC drive type PDP and a drive circuit portion.

FIG. 11 is a block diagram showing an internal configuration of a data driver.

FIG. 12 is a driving waveform diagram of each section of the AC drive type PDP in one subfield period.

FIG. 13 shows adjacent data electrodes Dn-1 and Dn which are capacitively coupled to data electrodes Dn of an AC-driven PDP.
An equivalent circuit showing n + 1, scan electrodes, and sustain electrodes.

FIG. 14 is a waveform chart showing a state of a voltage change of a data electrode Dn during a writing period.

FIG. 15 is a cross-sectional view of an LDD-structure high breakdown voltage MOSFET.

FIG. 16 is an equivalent circuit diagram of an inverter circuit including a MOSFET in which a protection diode is formed.

FIG. 17 is a sectional view of a conventional sub-gate structure TFT.

FIG. 18 is a CMO using a conventional sub-gate structure TFT.
The circuit diagram of S inverter.

FIG. 19 is a circuit diagram showing an example of a high-breakdown-voltage output buffer provided with a TFT protection element separately from an output buffer TFT.

FIG. 20 is a cross-sectional view of a conventional double-sided sub-gate TFT.

FIG. 21 is a sectional view of a conventional double-sided sub-gate MOSFET.

[Explanation of symbols]

 Reference Signs List 1 poly-Si layer 2 gate electrode 2a N-side gate electrode 2b P-side gate electrode 3 source-side impurity layer 3a source-side n-type impurity layer 3b source-side p-type impurity layer 4 drain-side impurity layer 4a drain-side n-type impurity layer 4b Drain-side p-type impurity layer 5 Source-side contact 6 Drain-side contact 7 Subgate electrode 8 Subgate electrode 9 Source electrode 9a N-side source electrode 9b P-side source electrode 10 Drain electrode 11 Second gate insulating layer 12 First gate insulating layer 13 Insulation Functional substrate 14 Semiconductor substrate 15 Field oxide film 16 N well 17 N side low concentration impurity layer 18 P side low concentration impurity layer 19a High breakdown voltage N side gate electrode 19b High breakdown voltage P side gate electrode 20 Third gate insulating layer 21 PDP panel 22 Data electrode 23 Scan electrode 24 Sustain electrode 25a, 2 b to 25k Data driver 26A to 26L Scan driver 27 Sustain pulse generator 28 n-bit shift register 29 n-bit latch 30 level shifter 31 high voltage output buffer 32 P-channel FET 33 N-channel FET 34 protection diode 35 PTFT 36 NTFT 37 PTFT protection element 38 NTFT protection element 39 second contact 40 upper wiring layer

Claims (16)

[Claims] 1. A P-channel and N-channel thin film transistor (TFT) having a thin film transistor (TFT), a source electrode of the P-channel thin film transistor (PTFT) is connected to a high potential side power supply, and a source electrode of the N-channel thin film transistor (NTFT) is low potential side. A thin-film semiconductor device including a circuit connected to a power supply and commonly connecting the drain electrodes of the PTFT and the NTFT, comprising: a polycrystalline silicon (p-Si) layer; and a source formed at one end of the p-Si layer. -Structured TFT having a side impurity layer, a drain side impurity layer formed at the other end of the p-Si layer, and a first gate electrode provided on the p-Si layer via a first insulating layer. The polycrystalline silicon (p-Si) layer, a source-side impurity layer formed at one end of the p-Si layer, and the p-Si layer. And the drain-side impurity layer formed on the p-Si
A first gate electrode provided on the layer via a first insulating layer; and a second gate electrode provided between the first gate electrode and the drain-side impurity layer and provided via a second insulating layer. And a circuit having a second structure TFT having a third gate electrode provided between the first gate electrode and the source-side impurity layer and provided with the second insulating layer interposed therebetween. The length of the channel formed in the p-Si layer by the third gate electrode is increased by the second gate electrode.
-A thin film semiconductor device, wherein the bias voltage is applied to the second gate electrode and the third gate electrode, the bias voltage being shorter than the length of a channel formed in the Si layer. 2. The thin-film semiconductor device according to claim 1, wherein a common bias voltage is applied to said second gate electrode and said third gate electrode. 3. The method according to claim 1, wherein the second gate electrode and the third gate electrode of the NTFT are connected to a high potential side power supply, and
2. The thin film semiconductor device according to claim 1, wherein the second gate electrode and the third gate electrode of the FT are connected to a low potential side power supply terminal. 4. A P-channel and N-channel thin film transistor (TFT), a source electrode of the P-channel thin film transistor (PTFT) is connected to a high potential side power supply, and a source electrode of the N-channel thin film transistor (NTFT) is low potential side. A thin-film semiconductor device including a circuit connected to a power supply and commonly connecting the drain electrodes of the PTFT and the NTFT, comprising: a polycrystalline silicon (p-Si) layer; and a source formed at one end of the p-Si layer. A side impurity layer; a drain side impurity layer formed at the other end of the p-Si layer; a first gate electrode provided on the p-Si layer via a first insulating layer; A second gate electrode provided between the first gate electrode and the drain-side impurity layer and provided via a second insulating layer;
A circuit having a second structure TFT having a third gate electrode provided between the first gate electrode and the source-side impurity layer and provided with the second insulating layer interposed therebetween, wherein the third gate The length of the channel formed in the p-Si layer by the electrode is increased by the second gate electrode.
-A thin film semiconductor device, wherein the bias voltage is applied to the second gate electrode and the third gate electrode, the bias voltage being shorter than the length of a channel formed in the Si layer. 5. The thin-film semiconductor device according to claim 4, wherein a common bias voltage is applied to said second gate electrode and said third gate electrode. 6. The method according to claim 6, wherein the second gate electrode and the third gate electrode of the NTFT are connected to a high potential side power supply,
5. The thin film semiconductor device according to claim 4, wherein the second gate electrode and the third gate electrode of the FT are connected to a low potential side power supply terminal. 7. A P-channel and N-channel thin-film transistor (TFT), a source electrode of the P-channel thin-film transistor (PTFT) is connected to a high-potential power supply, and a source electrode of the N-channel thin-film transistor (NTFT) is connected to a low-potential side. A thin-film semiconductor device including a circuit connected to a power supply and commonly connecting the drain electrodes of the PTFT and the NTFT, comprising: a polycrystalline silicon (p-Si) layer; and a source formed at one end of the p-Si layer. -Structured TFT having a side impurity layer, a drain side impurity layer formed at the other end of the p-Si layer, and a first gate electrode provided on the p-Si layer via a first insulating layer. The polycrystalline silicon (p-Si) layer, a source-side impurity layer formed at one end of the p-Si layer, and the p-Si layer. And the drain-side impurity layer formed on the p-Si
A fourth gate electrode provided on the layer via a first insulating layer and a second insulating layer; and a fourth gate electrode located between the fourth gate electrode and the drain-side impurity layer via a third insulating layer. A third structure TFT having a fifth gate electrode provided and a sixth gate electrode provided between the fourth gate electrode and the source side impurity layer and provided with the third insulating layer interposed therebetween; A circuit formed in the p-Si layer by the sixth gate electrode;
-A thin film semiconductor device, wherein a bias voltage is applied to the fifth gate electrode and the sixth gate electrode, the bias voltage being shorter than the length of a channel formed in the Si layer. 8. The thin film semiconductor device according to claim 7, wherein a common bias voltage is applied to said fifth gate electrode and said sixth gate electrode. 9. The method according to claim 9, wherein the fifth gate electrode and the sixth gate electrode of the NTFT are connected to a high potential side power supply,
8. The thin film semiconductor device according to claim 7, wherein the fifth gate electrode and the sixth gate electrode of the FT are connected to a low potential side power supply terminal. 10. A P-channel and N-channel thin-film transistor (TFT), a source electrode of the P-channel thin-film transistor (PTFT) is connected to a high-potential power supply, and a source electrode of the N-channel thin-film transistor (NTFT) is connected to a low-potential side. A thin-film semiconductor device including a circuit connected to a power supply and commonly connecting the drain electrodes of the PTFT and the NTFT, comprising: a polycrystalline silicon (p-Si) layer; and a source formed at one end of the p-Si layer. -Structured TFT having a side impurity layer, a drain side impurity layer formed at the other end of the p-Si layer, and a first gate electrode provided on the p-Si layer via a first insulating layer. A polycrystalline silicon (p-Si) layer, a source-side impurity layer formed at one end of the p-Si layer, and another end of the p-Si layer. A drain-side impurity layer formed, a first gate electrode provided on the p-Si layer via a first insulating layer, and a second gate electrode located between the first gate electrode and the drain-side impurity layer. A second gate electrode provided via an insulating layer;
A circuit having a second structure TFT having a third gate electrode provided between the first gate electrode and the source side impurity layer and provided with the second insulating layer interposed therebetween, and the polycrystalline silicon (p -Si) layer; a source-side impurity layer formed at one end of the p-Si layer; a drain-side impurity layer formed at the other end of the p-Si layer;
A fourth gate electrode provided on the layer via a first insulating layer and a second insulating layer, and provided between the fourth gate electrode and the drain-side impurity layer via a third insulating layer; A third structure TFT having a fifth gate electrode provided and a sixth gate electrode provided between the fourth gate electrode and the source side impurity layer and provided with the third insulating layer interposed therebetween. And the length of the channel formed in the p-Si layer by the third gate electrode is set by the second gate electrode.
A bias voltage is applied to the second gate electrode and the third gate electrode, and a channel formed in the p-Si layer by the sixth gate electrode. The length of the p by the fifth gate electrode.
A thin film semiconductor device, wherein the bias voltage is shorter than the length of a channel formed in the Si layer, and another bias voltage is applied to the fifth gate electrode and the sixth gate electrode. 11. A common bias voltage is applied to the second gate electrode and the third gate electrode, and another common bias voltage is applied to the fifth gate electrode and the sixth gate electrode. The thin film semiconductor device according to claim 10, wherein 12. The method according to claim 12, wherein the second gate electrode and the third gate electrode of the NTFT are connected to a high potential side power supply,
The second gate electrode and the third gate electrode of the TFT are connected to a low potential side power supply terminal, the fifth gate electrode and the sixth gate electrode of the NTFT are connected to a high potential side power supply, and the PTFT of the PTFT is connected. The thin film semiconductor device according to claim 10, wherein the fifth gate electrode and the sixth gate electrode are connected to a low potential side power supply terminal. 13. A P-channel and N-channel thin film transistor (TFT), wherein a source electrode of the P-channel thin film transistor (PTFT) is connected to a high potential side power supply, and a source electrode of the N-channel thin film transistor (NTFT) is low potential side. A thin-film semiconductor device including a circuit connected to a power supply and commonly connecting the drain electrodes of the PTFT and the NTFT, comprising: a polycrystalline silicon (p-Si) layer; and a source formed at one end of the p-Si layer. A side impurity layer; a drain side impurity layer formed at the other end of the p-Si layer; a first gate electrode provided on the p-Si layer via a first insulating layer; A second gate electrode provided between the first gate electrode and the drain-side impurity layer and provided via a second insulating layer;
The circuit including a fourth structure TFT having a sixth gate electrode provided between the first gate electrode and the source-side impurity layer and provided with a third insulating layer interposed therebetween; The length of the channel formed in the p-Si layer is increased by the second gate electrode.
-A thin film semiconductor device, wherein the bias voltage is applied to the second gate electrode and the sixth gate electrode, the bias voltage being shorter than the length of a channel formed in the Si layer. 14. The thin film semiconductor device according to claim 13, wherein a common bias voltage is applied to said second gate electrode and said sixth gate electrode. 15. The method according to claim 15, wherein the second gate electrode and the sixth gate electrode of the NTFT are connected to a high potential side power supply, and
14. The TFT according to claim 13, wherein the second gate electrode and the sixth gate electrode of the TFT are connected to a low potential side power supply terminal.
The thin film semiconductor device according to the above. 16. The self-aligned structure of the first gate electrode, the source side impurity layer, the drain side impurity layer, and the p-Si layer of the first structure TFT. The thin-film semiconductor device according to any one of 1, 7, and 10.