JP2000058844A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrict interference by electrical noise between an analogue circuit and a digital circuit in a semiconductor device in which both circuits are included. SOLUTION: An insulated layer 26 composed of a buried oxide film is provided on a support substrate 25 composed of a silicon substrate, and an element forming monocrystal semiconductive layer 27 composed of monocrystal silicon is provided on the insulated layer 26. An element such as a MOSFET 28 or the like is formed in each region insulated and isolated in the monocrystal semiconductor layer 27, and an analogue circuit 22 and a digital circuit 23 are constituted. In response to the entire region constituting the analogue circuit 22 in the insulated layer 26, a shielding buried electrode 34 to which polycrystal silicon is annexed at a high concentration is provided. The buried electrode 34 is connected to a ground via a contact and a wiring 35 to obtain a ground potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an analog circuit for handling a high frequency such as an RF band and a digital circuit for forming a logic circuit are formed on the same substrate, and a single crystal semiconductor. The present invention relates to a method for manufacturing a semiconductor device having first and second embedded electrodes in an insulating layer below a layer.

[0002]

For example, in an electronic circuit of a portable information communication device such as a cellular phone, an RF section (analog signal processing circuit) operating at a very high speed of, for example, several tens of GHz is conventionally provided on a GaAs substrate. Was made using On the other hand, in recent years, there has been a demand for a single chip in which all circuits including the RF unit are mounted on one silicon substrate due to demands for miniaturization, weight reduction, and cost reduction.

However, in a semiconductor device in which an analog circuit for handling such a high frequency and a digital signal processing circuit are integrated, as shown in FIG. 19, transistors constituting the analog circuit formed on the silicon substrate 1 are used. (MO
An SFET) 2 and a transistor (MOSFET) 3 forming a digital circuit section are in a state where they are connected via a capacitor and a resistor (shown by an equivalent circuit in FIG. 19). Therefore, the digital circuit unit (transistor 3)
There is a problem that the electrical noise of the above interferes with the analog circuit section (crosstalk), and the literature (for example, "NIKKEI MICRODE
VICES February 1997 ”) also points out that such a reduction in crosstalk will be an issue for the future.

To solve this problem, as shown in FIG. 20, an SOS is used instead of the bulk type silicon substrate 1.
(Silicon on Saphire) It is conceivable to use a substrate. In this device, MOSFETs 5 and 6 are formed in a single crystal silicon layer grown on a sapphire substrate 4 which is an insulator, and the respective devices are separated by an insulating film 7 such as SiO2. However, the SOS substrate has many crystal defects and poor substrate quality, so there is a problem in terms of element performance, reliability, and the like, and there is a disadvantage that the cost is high.

As another solution, it has been proposed to adopt a triple well structure as shown in FIG. This is, for example, an n-well 9, a P-type substrate 8
Wells 10 are formed in order, and a MOS is formed in each of the wells 9 and 10.
By forming the FETs 11 and 12, element isolation is achieved. However, in this triple well structure, although the elements 11 and 12 are separated, the effect of preventing crosstalk is hardly complete, and the number of manufacturing steps increases, resulting in high costs. .

Meanwhile, an SOI (Silicon on Insulator) in which a single crystal semiconductor layer is provided on a supporting substrate via an insulating layer.
In a semiconductor device having a structure in which a MOSFET is formed in the single crystal semiconductor layer, a buried electrode (back gate) is provided in an insulating layer, and a gate operates by a potential applied to the buried electrode. There is one that controls a threshold voltage. However, in this case, the embedded electrode may be affected by noise due to the capacitance between the embedded electrode and the support substrate, and the operation of the MOSFET may be unstable.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide an apparatus in which an analog circuit section and a digital circuit section coexist. An object of the present invention is to provide a high-quality and low-cost semiconductor device that can suppress interference. A second object of the present invention is to form a transistor in a single crystal semiconductor layer provided on a supporting substrate via an insulating layer and to provide a buried electrode in the insulating layer. An object of the present invention is to provide a semiconductor device capable of fixing a potential and protecting the semiconductor device from noise, and a method for manufacturing a semiconductor device suitable for manufacturing the semiconductor device.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device comprising a plurality of elements such as transistors formed in a single crystal semiconductor layer provided on a semiconductor substrate via an insulating layer. In an integrated circuit in which an analog circuit section and a digital circuit section coexist, embedded electrodes are provided on an insulating layer corresponding to circuit blocks of the integrated circuit to electrically shield the circuit block area. However, it has features.

According to this, an SOI in which an insulating layer is interposed between an element forming region of a single crystal semiconductor layer and a semiconductor substrate.
Because of the (Silicon on Insulator) structure, a high-quality thin single crystal semiconductor layer can be obtained, element isolation can be easily performed, and the cost can be reduced as compared with the SOS substrate. Further, the element isolation width can be reduced, and high-density integration can be achieved. Then, the circuit block of the integrated circuit in which the analog circuit part and the digital circuit part coexist is electrically fixed by the embedded electrode for shielding embedded in the insulating layer below the integrated circuit block, and noise is reduced. You will be shielded. Note that a transistor (MOSFET) using an SOI structure has a small junction capacitance at a pn junction of a source / drain electrode and a high insulation resistance, so that it consumes a small amount of power, can operate at high speed, and can handle high frequencies. It will be suitable.

As a result, according to the semiconductor device of the first aspect of the present invention, the analog circuit section and the digital circuit section coexist, and interference between the two circuit sections due to electrical noise is suppressed. This is an excellent effect that high quality and low cost can be achieved.

In this case, the circuit block can be divided into an analog circuit section and a digital circuit section (the invention of claim 2), and the analog circuit section can be protected from noise of the digital circuit section. At this time, it is needless to say that the embedded electrodes may be provided corresponding to both of the circuit blocks, and the embedded electrodes may be formed at the positions corresponding to the entire area constituting the analog circuit section or the digital circuit section. Even if it is provided at a position corresponding to the entire region (the invention of claim 3), the same shielding effect can be obtained.

Also, the buried electrode is not formed in a large shape extending over a plurality of elements, but is provided in a form divided at a position corresponding to the channel region of the transistor. The embedded electrodes may be connected to each other by wiring (the invention of claim 4). According to this, the buried electrode is provided only in the necessary part, the load capacitance of the wiring can be reduced, the power consumption can be reduced, and the high-speed operability can be further improved. If the embedded electrode is set to the ground potential (the invention of claim 5), a reliable shielding effect can be obtained.

According to the semiconductor device of the present invention, an element including a transistor is formed in a single crystal semiconductor layer provided on a supporting substrate with an insulating layer interposed therebetween.
A first buried electrode corresponding to the transistor, wherein the insulating layer has a second buried electrode for electrically fixing the first buried electrode and the entire element formation region. The feature is that the contact surface of the first buried electrode and the contact surface of the second buried electrode are located on the same plane.

According to this, the operating threshold voltage of the gate can be controlled by the potential applied to the first embedded electrode. Since the first embedded electrode and the second embedded electrode for electrically fixing the whole of the element formation region are provided between the first embedded electrode and the support substrate, It is possible to prevent the buried electrode 1 and the element from being affected by noise, and to stabilize the operation of the transistor. Here, in order to make contact with the first and second embedded electrodes, an etching step of opening corresponding contact holes in the insulating layer is required. If the contact surfaces are located on the same surface, these contact holes can be formed simultaneously in one etching step.

Therefore, according to the semiconductor device of claim 6,
A transistor in which a transistor is formed in a single crystal semiconductor layer provided on a supporting substrate with an insulating layer interposed and a buried electrode is provided in the insulating layer, and the entire potential is fixed to protect the device from noise. And the reliability of the contact can be improved, and the manufacturing process can be simplified.

At this time, if the contact surfaces of the first and second buried electrodes are located at a height between the first buried electrode and the single crystal semiconductor layer in the insulating layer, (7) The depth of the contact hole is reduced,
The amount of etching and thus the etching time can be reduced. Alternatively, if the contact surfaces of the first and second embedded electrodes are located on the same plane as the surface of the single crystal semiconductor layer (the invention of claim 8), the contact holes have the same depth. Therefore, the etching process is completed at the same time, and the working process can be further simplified.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a surface of a first semiconductor substrate; and forming a first buried electrode on the first insulating film. Providing a first conductor, forming a second insulating film on the surface of the first conductor, and providing a second conductor serving as a second embedded electrode on the first insulating film and the second insulating film; Depositing a planarizing material on the second conductor and planarizing the surface thereof, and bonding a support substrate on the planarizing material;
Removing the first semiconductor substrate to expose the first insulating film; and performing ion implantation at a predetermined depth on the second semiconductor substrate made of a single crystal semiconductor to form a defect layer for separation. It is characterized in that it includes a step of bonding the surface of the second semiconductor substrate on the ion implantation side to the surface of the first insulating film, and a step of peeling the second semiconductor substrate at the defect layer.

According to this, the planarizing material and the insulating layer composed of the second insulating film and the first insulating film are provided on the supporting substrate, and the insulating layer is formed on the insulating layer by the defect layer of the second semiconductor substrate. An SOI structure in which the surface side portion is bonded as a single crystal semiconductor layer is obtained. In the insulating layer, a first conductor is buried as a first buried electrode, and a second conductor is buried as a second buried electrode located on the back side thereof. It is said. At this time, both the surface portion of the first embedded electrode and the surface portion of the second embedded electrode that are not located on the back side of the first embedded electrode are the first embedded electrode.
The insulating film is located on the same surface on the back side.

Therefore, according to the method of manufacturing a semiconductor device of the ninth aspect, as described above, the entire potential can be fixed to protect from noise, and the contact hole can be formed by a simple etching process. The semiconductor device according to claim 6 can be easily manufactured. In addition, since the single crystal semiconductor layer is obtained by bonding, a single crystal semiconductor layer having high quality, a small thickness, and a uniform thickness can be obtained.

In this case, in the method of manufacturing a semiconductor device according to the ninth aspect, the first insulating film formed on the first semiconductor substrate is required to have at least a region corresponding to a channel region of the transistor. An etching step of reducing the thickness of the remaining portion while keeping the film thickness may be performed (the invention of claim 10). According to this, both the surface portion of the first embedded electrode and the surface portion of the second embedded electrode that are not located on the back surface side of the first embedded electrode have the thickness of the first insulating film. It will be located on the same plane in the middle of the direction,
The semiconductor device according to claim 7 can be easily obtained.

The method of manufacturing a semiconductor device according to claim 11 of the present invention includes the steps of: etching a surface portion of a semiconductor substrate made of a single crystal semiconductor in a concave shape excluding at least a predetermined region corresponding to an element formation region; Forming a first insulating film on the surface of the semiconductor substrate, forming an opening in the first insulating film at a position corresponding to a contact portion of the first embedded electrode, and forming a first insulating film on the first insulating film; Providing a first conductor serving as a first buried electrode, forming a second insulating film on the surface of the first conductor, and corresponding to a contact portion of the second buried electrode in the first insulating film. Forming an opening at the set position, providing a second conductor to be a second embedded electrode on the first insulating film and the second insulating film, and depositing a planarizing material on the second conductor. Flattening the surface and supporting on the flattening material Characterized in place comprising the steps of: is laminated plate, and removing the back surface side of the semiconductor substrate until the space left by the etching process is exposed.

According to this, the planarizing material and the insulating layer composed of the second insulating film and the first insulating film are provided on the supporting substrate, and the insulating layer is left on the insulating layer in the etching step of the semiconductor substrate. An SOI structure in which the formed region is provided as a single crystal semiconductor layer is obtained. In the insulating layer, a first conductor is buried as a first buried electrode, and a second conductor is buried as a second buried electrode located on the back side thereof. It is said. At this time, the surface portion of the first embedded electrode, the surface portion of the second embedded electrode that is not located on the back surface side of the first embedded electrode, and the surface of the single crystal semiconductor layer are flush with each other. Will be positioned above.
Therefore, the semiconductor device according to claim 8 can be easily manufactured.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to FIGS.

(1) First to Third Embodiments First, a first embodiment (corresponding to claims 1, 2, 3, and 5) of the present invention will be described with reference to FIGS. 1 and 2 schematically (schematically) show the configuration of a semiconductor device 21 according to the present embodiment.
Reference numeral 1 denotes, for example, an analog circuit unit 22 including an RF unit operating at a very high speed of several tens of GHz and a digital circuit unit 23 forming a logic circuit, which is used in a portable information communication device such as a mobile phone. An integrated circuit integrated on the individual SOI substrates 24 is configured. In this case, as shown by a broken line in FIG. 2, the entire integrated circuit is located such that the entire region constituting the analog circuit section 22 is located on the left side in the figure and the entire region constituting the digital circuit section 23 is located on the right side in the figure. It is divided into two circuit blocks.

The SOI substrate 24 has an insulating layer 26 made of a buried oxide film on a support substrate 25 made of, for example, a silicon substrate, and a single crystal for element formation made of single crystal silicon is formed on the insulating layer 26. It has a semiconductor layer 27. The single crystal semiconductor layer 27 is insulated and separated into regions for each element by forming an oxide film, for example, and an element such as a MOSFET 28 as a transistor is formed in each region.

In this case, in the MOSFET 28, a gate electrode 30 made of polycrystalline silicon is formed on a single crystal semiconductor layer 27 via a gate oxide film 29.
The source 31 and the drain 32 (and the channel region 33 between them) are formed in the single crystal semiconductor layer 27. Although not shown, an interlayer insulating film (protective film) is formed on the single crystal semiconductor layer 27, and a wiring of, for example, aluminum or tungsten is formed after the opening of the contact hole. It has become.

A buried electrode 34 for shielding is provided in the insulating layer 26. This embedded electrode 34
Is made of polycrystalline silicon to which impurities such as phosphorus and boron are added at a high concentration, and is provided at a position corresponding to the entire region constituting the analog circuit section 22 in this embodiment. The buried electrode 34 is connected to the ground by a contact and a wiring 35, and is set to a ground potential.

In the semiconductor device 21 having the above structure, S
Since the OI structure is adopted, a high-quality thin single-crystal semiconductor layer 27 can be obtained and the cost can be reduced as compared with the conventional one using the SOS substrate shown in FIG. Also, unlike the triple well structure shown in FIG. 31, element isolation can be easily performed, the element isolation width can be reduced, and high-density integration is possible. Further, the MOSFET 28 using the SOI structure has a source 3
1. Since the junction capacitance at the pn junction of the drain 32 is small and the insulation resistance is high, power consumption is low, high-speed operation is possible, and the device is suitable for handling high frequencies.

In an integrated circuit in which the analog circuit section 22 and the digital circuit section 23 coexist, electric noise generated in the digital circuit section 23 interferes with the analog circuit section 22 via the support substrate 25. (Cross talk). However, in the present embodiment, the circuit block of the analog circuit section 22 is electrically fixed by the buried electrode 27 buried in the insulating layer 26 thereunder, and noise generated in the digital circuit section 23 is embedded. It is canceled by the electrode 27 and no longer reaches the analog circuit section 22. In addition, at this time, since the embedded electrode 34 is set to the ground potential, a reliable shielding effect can be obtained.

Therefore, according to the first embodiment, the analog circuit section 22 and the digital circuit section 23 coexist, and they correspond to the entire area of the insulating layer 26 that constitutes the analog circuit section 22. Since the buried electrode 34 is provided at the position and this is set to the ground potential, interference due to electrical noise between the two circuit portions 22 and 23 can be reliably suppressed, and high quality and low cost can be achieved. It is possible to obtain an excellent effect of being able to do so.

FIGS. 3 and 4 show a second embodiment (corresponding to claim 4) of the present invention. The semiconductor device 36 according to the second embodiment is different from the first embodiment in that the shield embedded electrode 37 provided at a position corresponding to the circuit block of the analog circuit section 22 is replaced by an individual MOSFET 2.
It is provided in a form divided for every eight, and the whole of the plurality of embedded electrodes 37 is connected to each other by a wiring 38. In this case, each embedded electrode 37 is formed corresponding to the channel region 33 of the MOSFET 28 in the insulating layer 26. These embedded electrodes 37 are set to the ground potential.

According to this configuration, as in the first embodiment, the provision of the buried electrode 37 ensures that interference due to electrical noise between the digital circuit section 23 and the analog circuit section 22 is ensured. It is possible to obtain an excellent effect that it can be suppressed, and high quality and low cost can be achieved. Note that the embedded electrode 37 is M
It can be used as a so-called back gate for controlling the operating threshold voltage of the gate of the OSFET 28.

As shown in FIG. 4, when the wiring 39 for each element is arranged between the adjacent MOSFETs 28, in the case of the large buried electrode 34 as in the first embodiment, FIG. As shown in FIG.
The capacitance between the wiring 39 and the buried electrode 34 is equal to that of the buried electrode 37 of the second embodiment. As shown in FIG. 25. Therefore, in this embodiment, in addition to the above-described effects, the load capacitance of the wiring 39 can be reduced as compared with the first embodiment, and the overall power consumption can be further reduced and the high-speed operation can be improved. The advantage that it can be obtained can also be obtained.

FIG. 5 shows the configuration of a semiconductor device 40 according to the third embodiment of the present invention (only the analog circuit section 22 is shown). In this embodiment, similar to the first embodiment,
A buried electrode 41 is provided in the insulating layer 26 at a position corresponding to the entire region constituting the analog circuit section 22, and the buried electrode 41 is formed so as to surround a peripheral portion of the analog circuit section 22. The peripheral part is formed in an upright form. According to this, the side surface of the element such as the MOSFET 28 constituting the analog circuit section 22 is also shielded by the embedded electrode 41, so that the shielding effect against noise can be further enhanced.

In the first to third embodiments, the embedded electrodes 34, 37 and 41 are provided on the analog circuit section 22 side. Or the embedded effect may be provided in both the analog circuit section 22 and the digital circuit section 23. In addition, the circuit block of the integrated circuit is not limited to being divided into two parts, the analog circuit part 22 and the digital circuit part 23. For example, the analog circuit part 22 is further divided into a plurality of circuit blocks, and each circuit block is The buried electrode may be provided. Furthermore, the same shielding effect can be obtained by keeping the embedded electrode at a predetermined potential, not necessarily at the ground potential.

(2) Fourth to Sixth Embodiment Next, a fourth embodiment (corresponding to claim 6) of the present invention will be described with reference to FIGS. FIG. 6 schematically illustrates a configuration of a semiconductor device 51 according to the present embodiment, which is configured by forming an element such as a MOSFET 53 on an SOI substrate 52. The SOI substrate 52 has, for example, an insulating layer 55 made of a buried oxide film on a support substrate 54 made of a silicon substrate, and a single crystal semiconductor layer 56 made of single crystal silicon for forming an element on the insulating layer 55. Is configured. The single crystal semiconductor layer 56 is insulated and separated into regions for each element, and the gate electrode 5
8 and the source 59 and the drain 60 are formed to form the MOSFET 53.

At this time, in the insulating layer 55, a MOS
A first portion made of polycrystalline silicon to which impurities such as phosphorus and boron are added at a high concentration,
Embedded electrode 61 is provided. The first buried electrode 61 extends rightward in the figure until a part of the first buried electrode 61 departs from the MOSFET 53 formation region, and the upper surface of the extension is a contact surface 61a. This first embedded electrode 6
1 is a MOSFE when a required potential is applied.
It functions as a so-called back gate for controlling the operation threshold voltage of the gate of T53.

In addition, the first layer is provided in the insulating layer 55.
Of polycrystalline silicon to which impurities such as phosphorus and boron are added at a high concentration, for example, the first embedded electrode 61, the element formation region, and the entire region of the wiring (not shown). Is provided with a second embedded electrode 62 for electrically fixing. This second embedded electrode 6
2 is provided in such a manner that the right end side in the figure is lifted upward, and the upper surface thereof is a contact surface 62a. The contact surface 62a is a contact surface of the first embedded electrode 61. 61a. The second embedded electrode 62 is maintained at, for example, a ground potential.

Although not shown, an interlayer insulating film is formed on the single-crystal semiconductor layer 56, and the interlayer insulating film and the insulating film 55 are etched, so that the electrodes of each element are etched. And the contact surfaces 61a, 62a
A contact hole is opened toward the. Then, the wiring is formed so as to fill the contact hole with aluminum, tungsten or the like.

In the semiconductor device 51 having the above structure, S
Of course, the merit of the OI structure can be enjoyed, and the first embedded electrode 61 can be used as a back gate. Then, the first embedded electrode 6
Since the second buried electrode 62 for electrically fixing the whole is provided between the first buried electrode 61 and the support substrate 54, the first buried electrode 61 and thus the MOSFET 53 are affected by noise. Thus, the operation of the MOSFET 53 can be stabilized.

Here, as shown in FIG.
Has a constant conductivity, the support substrate 54 is set to the ground potential, so that the second embedded electrode 62 is not provided.
It is conceivable that the support substrate 54 performs the same function as the second embedded electrode 62. In this case, an interlayer insulating film 63 is formed on the single crystal semiconductor
After forming contact holes 64, 65, 66 for the FET 53 (only for the drain 60), the first embedded electrode 61, and the support substrate 54, the wiring 67 is formed.
Is formed.

However, the contact holes 64, 6
The depths of the contact holes 6 are different from each other.
For example, if all contact holes 64, 65, and 66 are to be formed in a single etching step, the contact hole 64 is opened and the single crystal semiconductor layer 56 is exposed. Until the opening 65 and the contact hole 66 are opened, the single crystal semiconductor layer 56 is exposed to the etching atmosphere.

For this reason, from the relationship between the etching selectivity and the thickness of each part, or when the amount of over-etching is set to a relatively large value, as shown in FIG. And there is a danger of short-circuiting to the first embedded electrode 61. Therefore, in order to obtain the structure shown in FIG. 7, it is necessary to perform a step of dividing the etching step into three steps by a mask step, resulting in a disadvantage that the manufacturing process is complicated.

On the other hand, in this embodiment, the second embedded electrode 62 for electrically fixing the whole is provided, and the contact surface 62a is configured to be lifted upward. Since the contact holes are located on the same surface as the contact surfaces 61a of the embedded electrodes 61, the total etching time is greatly reduced even when these contact holes are simultaneously formed in one etching step. Therefore, the time during which the first exposed single crystal semiconductor layer 56 is exposed to the etching atmosphere can be shortened, and the disadvantage that the single crystal semiconductor layer 56 is completely removed at the contact hole portion can be solved. This can improve the operability and can simplify the process related to the formation of the contact hole.

FIG. 9 shows a configuration of a semiconductor device 68 according to a fifth embodiment (corresponding to claim 7) of the present invention. This embodiment differs from the fourth embodiment in that the first embedded electrode 69 has a configuration in which the right end in the figure is lifted upward, and the contact surface 69a is the first embedded electrode 69 of the insulating layer 55. This is at a point located at a height between the embedded electrode 69 and the single crystal semiconductor layer 56. Also in this case, the contact surface 70a of the second embedded electrode 70 is flush with the contact surface 69a. According to this, the depth of the contact hole is further reduced, and the etching time can be further reduced.

FIG. 10 shows a sixth embodiment of the present invention.
This shows a configuration of a semiconductor device 71 according to the third embodiment, which is different from the fourth embodiment in the following point. That is, the MOSFET 53 is formed in the single-crystal semiconductor layer 56, the first contact portion 72 is formed on the right side in the drawing, and the second contact portion 73 is formed on the right side. These first and second contact portions 7
2 and 73 are formed by lowering the resistance by ion implantation simultaneously with the formation of the source 59 and the drain 60 of the MOSFET 53.

Then, the first embedded electrode 7 in the insulating layer 55
4 is a form in which the right end is lifted and the first
(Electrically connected) to the contact portion 72 of the
The embedded electrode 75 is in contact with (electrically connected to) the second contact portion 72. With this, the first and second
The surfaces of the contact portions 72 and 73 are contact surfaces, respectively, and are located on the same plane as the surfaces of the single crystal semiconductor layers 56 (the source 59 and the drain 60).

According to the sixth embodiment, the depths of the contact holes are all the same and sufficiently shallow, so that the etching process for forming the contact holes can be completed in a short time and all of them at the same time. Thus, the operation steps can be further simplified.

(3) Seventh and Eighth Embodiments Next, a seventh embodiment (corresponding to claims 6 and 9) of the present invention will be described with reference to FIGS. FIG.
Shows the configuration of a semiconductor device 81 manufactured by the manufacturing method according to the present embodiment. This semiconductor device 81
The semiconductor device has an SOI structure in which a single crystal semiconductor layer 84 for element formation made of single crystal silicon is provided over a support substrate 82 made of a silicon substrate with an insulating layer 83 interposed therebetween.

On the upper surface of the single crystal semiconductor layer 84, a gate electrode 86 is formed via a gate oxide film 85. At the same time, a source 87 and a drain 8 are formed on the single crystal semiconductor layer 84.
8 are formed, and thus the MOSFET 89 is formed. Further, an interlayer insulating film 90 made of, for example, a silicon oxide film is formed on the upper surface so as to cover the gate electrode 86 and the whole.

In the insulating layer 83, the MO
A first buried electrode 91 functioning as a back gate is provided below the SFET 89, and below the first buried electrode 91 and the entire region of the element formation region are electrically connected. Embedded electrode 9 for fixing to
2 are provided. The second embedded electrode 92 has a form in which the right end in the figure is lifted upward, and is a contact surface 92a located on the same plane as the contact surface 91a of the first embedded electrode 91. I have.

The surface layers (first insulating film 96 described later) of the interlayer insulating film 90 and the insulating layer 83 are etched so that the electrodes of the MOSFET 89 (only the drain 88 is shown) and the contact surface 91 are formed.
a, a contact hole 93 is opened toward 92a,
The wiring 94 is formed in such a manner that the contact hole 93 is buried with aluminum, tungsten or the like.

Now, a procedure for manufacturing the semiconductor device 81 having the above configuration will be described with reference to FIGS. First, as shown in FIG.
On the surface of a first semiconductor substrate 95 made of a silicon substrate of
By a method such as thermal oxidation or CVD, for example, a thickness of 100 nm
Of forming the first insulating film 96 is performed. Next, as shown in FIG. 11B, a first conductor 91 made of, for example, a polycrystalline silicon film doped with phosphorus at a high concentration and serving as the first embedded electrode is formed on the first insulating film 96. The step of forming is performed.

In the step of forming the first conductor 91, first, a polycrystalline silicon film having a thickness of, for example, 370 nm is formed on the entire surface of the first insulating film 96, and phosphorus is added thereto at a high concentration to form a conductor. After that, patterning is performed by etching into a desired shape. As a method of adding phosphorus, a so-called phosphorus deposition in which heat treatment is performed in a phosphorus atmosphere after the deposition of polycrystalline silicon, or a so-called doped poly in which phosphorus is added to a gas of a polycrystalline silicon deposit can be used. Incidentally, boron or the like can be adopted instead of phosphorus.

Subsequently, as shown in FIG. 11C, a step of forming a second insulating film 97 having a thickness of, for example, 100 nm on the surface of the first conductor 91 by, for example, thermal oxidation is performed. In this case, the thermal oxidation rate of the first conductor 91 is high, and the second insulating film 97 can be formed on the surface of the first conductor 91 in a short time.
Since the first insulating film 96 having a thickness of 100 nm is already formed on the surface of the first semiconductor substrate 95, the oxidation of the surface of the first semiconductor substrate 95 hardly progresses during such a thermal oxidation time.

Next, as shown in FIG. 12A, a second conductive film is formed on the entire surface of the second insulating film 97 and the first insulating film 96 in the same manner as in the step of forming the first conductor 91. A step of forming a second conductor 92 having a thickness of, for example, 370 nm, which is to be an embedded electrode is performed. Then, a flattening material 98 made of, for example, a silicon oxide film is
For example, a step of depositing with a thickness of, for example, 1 μm by the VD method and further polishing and planarizing the surface is performed.

As shown in FIG. 14, the first buried electrode 91 is provided in the layer made of the first insulating film 96, the second insulating film 97, and the planarizing material 98.
And insulating layer 83 in which second embedded electrode 92 is embedded
Is configured. Then, at this time,
And contact surface 19a of second embedded electrodes 91 and 92
And 92a are both located on the back surface of the first insulating film 96 and are located on the same surface.

Thereafter, as shown in FIG. 12B, a step of bonding the support substrate 82 (for example, having a thickness of 600 μm) on the flattening material 98 is performed. As is well known, the bonding step includes forming an oxide film (not shown) on the surface of the support substrate 82, and then forming the surface (bonded surface) of the support substrate 82 and the planarization process. Material 9
The surface of No. 8 is subjected to a hydrophilic treatment, and the two are brought into close contact with each other.

Next, as shown in FIG. 12C, a step of removing the first semiconductor substrate 95 and exposing the first insulating film 96 is performed. In this step, first, the first semiconductor substrate 95 is polished from the back surface side (the lower side in the figure), and when a thickness of, for example, several μm is left, the first semiconductor substrate 95 is switched to selective etching using, for example, a KOH solution to switch the first semiconductor substrate 95 Substrate 95
By removing the remaining part, the first insulating film 96 can be exposed in a short time with good controllability. As a result, as shown in FIG. 14, the insulating layer 83 is provided on the support substrate 82, which is inverted upside down.

On the other hand, a second semiconductor substrate 99 (shown in FIG. 13A) made of a single-crystal silicon substrate is prepared, and hydrogen ions are implanted into the surface of the second semiconductor substrate 99 with a predetermined energy, for example. A step of forming the defect layer 100 for separation at a predetermined depth (for example, 1 μm from the surface) of the surface of the substrate 99 is performed. This hydrogen absorbing and peeling technique is known, for example, in Japanese Patent Application Laid-Open No. 5-211128. As a result, a thin single crystal thin film layer 99 a serving as the single crystal semiconductor layer 84 is formed on the surface layer of the second semiconductor substrate 99 in a form partitioned by the defect layer 100.

Then, as shown in FIG. 13A, a step of bonding the second semiconductor substrate 99 to the first insulating film 96 on the surface of the insulating layer 83 provided on the supporting substrate 82 is included. This is performed in the same manner as in the bonding step of the support substrate 82. Subsequently, as shown in FIG. 13B, a step of peeling the second semiconductor substrate 99 at the defect layer 100 is performed by causing a crack in the defect layer 100 by heat treatment. Thus, the single crystal thin film layer 99
a is separated from the second semiconductor substrate 99 to form the first insulating film 96.
The state is as if it had been transferred onto. Thereafter, the insulating layer 8 is formed on the supporting substrate 82 by performing a high-temperature annealing process, a smoothing process on the separated surface of the single crystal thin film layer 99a, and the like.
Through the step 3, an SOI structure having a high-quality thin-film single crystal semiconductor layer 84 can be obtained.

Although not shown in detail, after this, an oxide film is formed on the single crystal semiconductor layer 84 to insulate and separate regions of each element, and then a MOSF is formed by a known process.
ET89 is formed, and further, an interlayer insulating film 90 having a thickness of, for example, 0.5 to 1 μm is formed. Then, an etching step for forming the contact hole 93 is performed. As described in the fourth embodiment, the contact surface 92a of the second embedded electrode 92 is lifted upward and the first
Are located on the same surface as the contact surface 91a of the buried electrode 91, so that the contact holes 93 can be simultaneously formed in one etching step while preventing problems such as a short circuit due to the wiring 94. This makes it possible to simplify the process for forming the contact hole 93.

As described above, according to the manufacturing method of this embodiment,
A first buried electrode 9 serving as a back gate is formed in the insulating layer 83.
1 and a second embedded electrode 9 for electrically fixing the entire region
2 and their contact surfaces 91a and 92
The semiconductor device 81 in which a is located on the same plane can be easily manufactured by a relatively simple process. In addition, since the single crystal semiconductor layer 84 is obtained by bonding, the single crystal semiconductor layer 84 having high quality, a small thickness, and a uniform thickness can be obtained.

FIG. 15 shows an eighth embodiment (corresponding to claims 7 and 10) of the present invention.
The points different from the embodiment are as follows. That is, in this embodiment, as shown in FIG. 11A, after forming the first insulating film 101 having a thickness of, for example, 100 nm on the surface of the first semiconductor substrate 95, as shown in FIG. M
An etching step is performed to reduce the thickness of the other portions of the OSFET 89 formation region (at least the region corresponding to the channel region) while leaving a required film thickness.

This etching step is performed by, for example, dry etching in a plasma gas atmosphere or wet etching using an HF aqueous solution after forming a predetermined mask pattern by a photolithography process. MOSFET 8 in film 101
The portion outside the formation region of No. 9 is etched in a concave shape to form a thin portion 101a having a thickness of, for example, about 10 nm. In this case, by leaving the thin portion 101a, it can be used as a stopper for selective etching in a later step of removing the first semiconductor substrate 95.

Then, as in the seventh embodiment, the first buried electrode (first conductor) 102 and the second insulating film 9 are formed.
7. A step of forming a second buried electrode (second conductor) 103 and a planarization material 98 is performed.
2, a step of removing the first semiconductor substrate 95, and a step of forming the single crystal semiconductor layer 84 by bonding and peeling of the second semiconductor substrate 99 are performed. Thus, an SOI structure having the single crystal semiconductor layer 84 over the supporting substrate 82 with the insulating layer 104 interposed therebetween is obtained as shown in FIG.

At this time, the first buried electrode 102 serving as a back gate and the second buried electrode 103 for electrically fixing the entire region are provided in the insulating layer 104. By providing the thin portion 101 a in the first insulating film 101, the end portion of the first embedded electrode 102 is lifted upward, so that the portion between the first embedded electrode 103 and the single crystal semiconductor layer 84 is formed. The contact surface 102a can be located at the height, and the contact surface 103a of the second embedded electrode 103 can also be located on the same plane. Therefore, as described in the fifth embodiment, the depth of the contact hole (not shown) can be further reduced, and the etching time required for forming the contact hole can be further reduced.

In the eighth embodiment, the first insulating film 10
In the first etching step, the required film thickness is left in the region where the MOSFET 89 is formed. However, other portions may be thinned while leaving the entire region constituting the analog circuit section. Also, the thickness of the part to be thinned is
What is necessary is just to set according to the etching selectivity in the step of removing the first semiconductor substrate 95.
It may be about nm.

(4) Ninth and Tenth Embodiments Next, a ninth embodiment (corresponding to claims 8 and 11) of the present invention will be described with reference to FIGS. FIG.
(B) shows the SOI substrate 111 of the semiconductor device manufactured by the manufacturing method of this embodiment before the element is formed, in an upside down state. The SOI substrate 111 has a structure in which a single crystal semiconductor layer 114 made of single crystal silicon is provided on a support substrate 112 made of, for example, a silicon substrate with an insulating layer 113 interposed therebetween.

In this case, the single crystal semiconductor layer 114
The element formation region 114a located on the left side in the figure and the two contact formation regions 114b and 114 located on the right side thereof
c and insulated from each other. Although not shown, a MOSFET is formed in the element formation region 114a,
The contact forming regions 114b and 114c are configured to have a low resistance to form a contact portion. In the insulating layer 113, there are provided a first buried electrode 115 serving as a back gate of the MOSFET and a second buried electrode 116 for electrically fixing the entire region. 1 embedded electrode 115 is in the contact formation region 1
14b is in contact with (electrically connected to) the second embedded electrode 1
Reference numeral 16 is in contact with (electrically connected to) the contact formation region 114c.

Now, the semiconductor device according to the present embodiment (SOI
The method for manufacturing the substrate 111) will be described below. First, as shown in FIG. 16A, a step of etching the surface of the semiconductor substrate 117 made of single-crystal silicon into a concave shape (for example, a depth of about 150 nm) excluding a predetermined region is performed. In this case, the predetermined area is the element formation area 114a and the two contact formation areas 114b,
114c. Therefore, the protrusions 117a, 117b, and 117c corresponding to the element formation region 114a and the contact formation regions 114b and 114c are formed on the surface of the semiconductor substrate 117.

Next, the surface of the semiconductor substrate 117 is thermally oxidized or deposited, for example, to a thickness of 100 nm.
A step of forming m first insulating films 118 is performed. Further, of the first insulating film 118, the protrusion 117b is formed.
Is performed to form an opening 118a by etching the upper surface of the substrate. This etching step is performed, for example, by forming a predetermined mask pattern by photolithography and then performing dry etching in a plasma gas atmosphere or wet etching using an HF aqueous solution or the like.

Next, as shown in FIG. 16B, on the first insulating film 118, for example, a polycrystalline silicon film to which phosphorus is added at a high concentration is formed, for example, to become the first buried electrode. The step of forming the first conductor 115 having a thickness of 370 nm is performed in the same manner as described in the seventh embodiment.
At this time, the first conductor 115 is formed in such a manner that a part thereof is in contact with the surface of the semiconductor substrate 117 (the convex portion 117b) through the opening 118a of the first insulating film 118. Subsequently, a step of forming a second insulating film 119 having a thickness of, for example, 100 nm on the surface of the first conductor 115 by, for example, thermal oxidation is performed.

Then, the step of forming the opening 118b by etching the upper surface of the projection 117c in the first insulating film 118 is performed in the same manner as described above. After this,
As shown in FIG. 16C, a second buried electrode is formed on the entire surface of the second insulating film 119 and the first insulating film 118 in the same manner as in the step of forming the first conductor 115. For example, a step of forming the second conductor 116 having a thickness of 370 nm is performed. As a result, a part of the second conductor 116 extends through the opening 118b to form the protrusion 11 of the semiconductor substrate 117.
7c is formed in contact with the surface.

Subsequently, as shown in FIG.
A step of depositing a flattening material 120 made of, for example, a silicon oxide film with a thickness of, for example, 1 μm on the conductor 116 by a CVD method and further polishing and flattening the surface is performed. Thereafter, the support substrate 112 (for example, having a thickness of 6
(00 μm) on the flattening material 120.

Then, as shown in FIG. 17B, the back surface of the semiconductor substrate 117 is exposed to the region (projection 117a) left in the etching step by using a known selective polishing technique.
117c) is exposed (until the lowermost portion of the first insulating film 118 is exposed). As a result, the protrusions 117a are left as the element formation regions 114a, and the protrusions 117b and 117c are left as the contact formation regions 114b and 114c, and the insulating layer is formed on the support substrate 112 as described above. The SOI substrate 111 having the single crystal semiconductor layer 114 (regions 114a to 114c) can be obtained via 113.

Thereafter, although not shown, an element (MOSFET) is formed in the element formation region 114a, and simultaneously with the formation of the source / drain (with the same mask), the ions are formed in the contact formation regions 114b and 114c. Implantation is performed to reduce the resistance of the regions 114b and 114c, so that two contact portions are formed. As a result, the surfaces of the contact portions are respectively set as contact surfaces, and the contact surfaces are MOSF
Thus, the ET is located on the same plane as the source / drain surfaces. Thereafter, an interlayer insulating film is formed, a contact hole is formed, and a wiring is formed.

Therefore, according to this embodiment, the contact surfaces (the element formation region 114a and the contact formation region 114a)
b, 114c) are located on the same plane, so that the configuration shown in the sixth embodiment (see FIG. 10) can be easily obtained, and the depths of the contact holes are all the same and sufficient. Therefore, the etching process for forming the contact holes can be completed in a short time and all the processes at the same time, so that the working process can be greatly simplified.

Finally, FIG. 18 shows a tenth embodiment (corresponding to claim 11) of the present invention. This embodiment differs from the ninth embodiment in the following points. That is,
In the nineteenth embodiment, the element formation region 114a and the contact formation region 114b are formed on the surface of the semiconductor substrate 117.
Although the projections 117a and 117b and 117c corresponding to the first and the fourth 114c are formed (see FIG. 16 (a)), in the present embodiment, in the step of etching the semiconductor substrate made of single crystal silicon, Etching is performed while leaving only the formation region 121.

Thereafter, as in the ninth embodiment, a step of forming a first insulating film 118 on the semiconductor substrate, and a portion of the first insulating film 118 corresponding to the contact surface 122a of the first embedded electrode 122 is performed. Forming an opening in a first step
Forming an embedded electrode 122, forming a second insulating film 119, forming an opening in a portion of the first insulating film 118 corresponding to the contact surface 123a of the second embedded electrode 123, Forming a buried electrode 123, depositing a planarization material 120 and planarizing the same,
The step of bonding 12 and the step of removing the back surface of the semiconductor substrate by selective polishing until the element formation region 121 is exposed are sequentially performed.

As a result, as shown in FIG.
An SOI structure in which an element formation region (single-crystal semiconductor layer) 121 is provided over a supporting substrate 112 with an insulating layer 124 interposed therebetween is obtained. At this time, the first buried electrode 122 and the A second buried electrode 123 is provided, and the first buried electrode 122 and the second buried electrode 1 are provided.
Thus, a configuration in which the 23 contact surfaces 122a and 123a are exposed on the same surface as the surface of the element formation region 121 is obtained.

Thereafter, as shown in FIG. 18B, a MOSFET 125 is formed in the element forming region 121, an interlayer insulating film 126 is formed, and then a contact hole 127 and a wiring 128 are formed. At this time, since the contact surfaces 122a and 123a are located on the same plane as the surface of the element forming region 121, the depths of the contact holes 127 are all the same and sufficiently shallow, as in the ninth embodiment. This greatly simplifies the process of forming the contact hole 127.

The present invention is not limited to the embodiments described above and shown in the drawings. For example, the buried electrode may be formed by employing a metal such as tungsten or copper by a CVD method or the like. In addition, a polycrystalline silicon film or the like can be used as a planarization material, and a ceramic substrate, a quartz substrate, or the like can be used as a support substrate. In addition, the present invention can be practiced with appropriate changes without departing from the gist, for example, the material and thickness of each part are merely examples.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention, and is a schematic longitudinal sectional view of a semiconductor device.

FIG. 2 is a schematic plan view of a semiconductor device.

FIG. 3 shows a second embodiment of the present invention, and is a schematic plan view of a semiconductor device.

FIG. 4 is a schematic longitudinal sectional view for comparing and explaining the operation.

FIG. 5 is a schematic longitudinal sectional view of a main part showing a third embodiment of the present invention.

FIG. 6 shows a fourth embodiment of the present invention, and is a schematic longitudinal sectional view of a semiconductor device.

FIG. 7 is a schematic longitudinal sectional view for comparison.

FIG. 8 is a schematic longitudinal sectional view when a short circuit occurs.

FIG. 9 is a schematic longitudinal sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a schematic longitudinal sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 11 shows a seventh embodiment of the present invention, and is a schematic longitudinal sectional view showing a manufacturing process of a semiconductor device (part 1).

FIG. 12 is a schematic longitudinal sectional view showing a manufacturing process of the semiconductor device (part 2).

FIG. 13 is a schematic vertical sectional view showing a manufacturing process of the semiconductor device (part 3).

FIG. 14 is a schematic longitudinal sectional view of a semiconductor device.

FIG. 15 shows the eighth embodiment of the present invention and is a schematic longitudinal sectional view showing a manufacturing process.

FIG. 16 shows the ninth embodiment of the present invention, and is a schematic longitudinal sectional view showing a manufacturing process of a semiconductor device (part 1).

FIG. 17 is a schematic longitudinal sectional view showing a manufacturing process of the semiconductor device (part 2).

FIG. 18 shows the tenth embodiment of the present invention, and is a schematic longitudinal sectional view showing a manufacturing process.

FIG. 19 is a schematic longitudinal sectional view showing a conventional example.

FIG. 20 is a schematic longitudinal sectional view showing a different conventional example.

FIG. 21 is a schematic longitudinal sectional view showing still another conventional example.

DESCRIPTION OF THE SYMBOLS In the drawings, 21, 36, and 40 are semiconductor devices, 22 is an analog circuit section, 23 is a digital circuit section, 25 is a support substrate, 2
6 is an insulating layer, 27 is a single crystal semiconductor layer, 28 is a MOSFE
T (transistor), 34, 37, 41 are embedded electrodes, 5
1, 68, 71 are semiconductor devices, 53 is a MOSFET (transistor), 54 is a support substrate, 55 is an insulating layer, 56 is a single crystal semiconductor layer, 61, 69, 74 are first embedded electrodes,
61a, 62a, 69a, 70a are contact surfaces, 6
2, 70, 75 are second buried electrodes, 72, 73 are contact portions, 81 is a semiconductor device, 82 is a support substrate, 83, 1
04 is an insulating layer, 84 is a single crystal semiconductor layer, 89 is MOSF
ET (transistor), 91 and 102 are first buried electrodes, 91 a, 92 a, 102 a and 103 a are contact surfaces, 92 and 103 are second buried electrodes, 95 is a first semiconductor substrate, 96 and 101 are first 1 is an insulating film, 97 is a second insulating film,
98 is a planarization material, 99 is a second semiconductor substrate, 100
Is a defect layer, 112 is a supporting substrate, 113 and 124 are insulating layers, 114 is a single crystal semiconductor layer, 115 and 122 are first embedded electrodes, 116 and 123 are second embedded electrodes, 117 is a semiconductor substrate, 118 is a first insulating film, 118a, 118b
Denotes an opening, 119 denotes a second insulating film, 120 denotes a planarization material, 121 denotes an element formation region, 122a and 123a denote contact surfaces, and 125 denotes a MOSFET (transistor).

Claims (11)

[Claims] An analog circuit section is formed by forming a number of elements such as transistors on a single crystal semiconductor layer provided on a support substrate via an insulating layer. Semiconductor device (21, 3) comprising an integrated circuit in which (22) and a digital circuit section (23) coexist.
6, 40), wherein buried electrodes (34, 37, 41) for electrically shielding a circuit block area of the integrated circuit are provided in the insulating layer (26). A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said circuit block is divided into an analog circuit section (22) and a digital circuit section (23). 3. The buried electrode (34, 41) has a position corresponding to the entire region constituting the analog circuit section (22),
3. The semiconductor device according to claim 1, wherein the semiconductor device is provided at a position corresponding to an entire region constituting the digital circuit section. 4. 4. The buried electrode (37) is provided in a form divided at a position corresponding to the channel region (33) of the transistor (28), and a space between the divided buried electrodes (37) is provided. The semiconductor device according to claim 1, wherein the semiconductor device is connected by a wiring. 5. The buried electrode (34, 37, 41)
5. The semiconductor device according to claim 1, wherein the semiconductor device is set to a ground potential. 6. A single crystal semiconductor layer (56, 84, 114) provided on a supporting substrate (54, 82, 112) via an insulating layer (55, 83, 104, 113, 124).
Elements such as transistors (53, 89, 125) are formed, and the insulating layers (55, 83, 104, 113,
124), the transistors (53, 89, 12)
5) First embedded electrodes (61, 69, 74, 9) corresponding to (5)
1, 102, 115, 122), wherein the insulating layers (55, 83, 104, 113, 124) are provided.
The first embedded electrodes (61, 69, 74, 91, 1)
02, 115, 122) and second embedded electrodes (62, 70, 7) for electrically fixing the entire element formation region.
5, 92, 103, 116, 123)
The first embedded electrodes (61, 69, 74, 91, 10)
2, 115, 122) contact surfaces (61a, 69)
a, 91a, 102a, 122a) and the second embedded electrodes (62, 70, 75, 92, 103, 116, 12).
3) Contact surface (62a, 70a, 92a, 103)
a, 123a) are located on the same plane. 7. The first and second embedded electrodes (69, 7).
0, 102, 103) contact surfaces (69a, 70a).
a, 102a, 103a) are the insulating layers (55, 10
7. The semiconductor device according to claim 6, wherein the semiconductor device is located at a height between the first buried electrode and the single crystal semiconductor layer. . 8. The first and second embedded electrodes (74, 7).
5, 115, 116, 122, and 123) are formed on the single crystal semiconductor layer (5).
7. The semiconductor device according to claim 6, wherein the semiconductor device is located on the same plane as the surface of (6, 114). 9. An insulating layer (83, 1) on a supporting substrate (82).
04) through the single crystal semiconductor layer (84)
An element (89) such as a transistor is formed, and the transistor (89) is formed on the insulating layer (83, 104).
And a second buried electrode (92, 103) for electrically fixing the first buried electrode (91, 102) and the entire element formation region. ). A method for manufacturing a semiconductor device (81) having in advance a first insulating film (96, 1) on a surface of a first semiconductor substrate (95).
01), and the first insulating film (96, 10).
1) A first conductor (91, 1) serving as the first embedded electrode is formed thereon.
02) and the first conductor (91, 102).
Forming a second insulation film (97) on the surface of the first insulation film (96, 101) and the second conductor (92) serving as the second buried electrode on the second insulation film (97). , 103); depositing a planarization material (98) on the second conductor (92, 103) to planarize the surface; and supporting the support on the planarization material (98). Substrate (8
Laminating 2) and the first semiconductor substrate (95)
Removing the first insulating film (96, 101) by removing the second semiconductor substrate (9) made of a single crystal semiconductor.
A step of forming a defect layer (100) for separation by performing ion implantation to a predetermined depth with respect to (9), and removing the surface of the second semiconductor substrate (99) on the ion implantation side with the first insulating film (96). , 101), and the second step
Separating the semiconductor substrate (99) at the defect layer (100). 10. A first insulating film (101) formed on said first semiconductor substrate (95), leaving a required film thickness in at least a region corresponding to a channel region of said transistor (89). 10. The method of manufacturing a semiconductor device according to claim 9, wherein an etching step of thinning other portions is performed. 11. An insulating layer (11) on a supporting substrate (112).
3, 124) via the single crystal semiconductor layer (11
4), an element (125) such as a transistor is formed, and a first embedded electrode (115, 1) corresponding to the transistor (125) is formed in the insulating layer (113, 124).
22) and a second electrode for electrically fixing the entire first buried electrodes (115, 122) and the element forming region (121).
A buried electrode (116, 123) in advance, wherein a surface portion of a semiconductor substrate (117) made of a single crystal semiconductor is provided at least in an element formation region (121). Etching in a concave shape except for a corresponding predetermined region, forming a first insulating film (118) on the surface of the semiconductor substrate (117), and forming the first insulating film (118) in the first insulating film (118). Forming an opening (118a) at a position corresponding to the contact portion of the embedded electrode (115, 122), and a first conductor serving as the first embedded electrode on the first insulating film (118). (115, 122); and providing the first conductor (1).
Forming a second insulating film (119) on the surface of the first embedded film (15, 122); and forming a second insulating film (119) on the first insulating film (118) at a position corresponding to the contact portion of the second embedded electrode (116, 123). Forming an opening (118b);
Providing a second conductor (116, 123) serving as the second embedded electrode on the insulating film (118) and the second insulating film (119), and planarizing the second conductor (116, 123); Depositing a processing material (120) and flattening the surface thereof; bonding the support substrate (112) on the flattening processing material (120);
7) removing the back surface side until the region left in the etching step is exposed.