JP2000058830A - Antireflection structure and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To limit the effect of nitrogen of the surface on a photo-resist by depositing an antireflection covering body of oxynitride silicon on a material layer, removing nitrogen from the surface region of the antireflection covering body and mounting the photo-resist. SOLUTION: The layer 104 of a polysilicon-gate material is deposited on a silicon wafer 102 with a shallow trench separator and twin-wells for a LOCOS or a CMOS device. A flattened pre-metal dielectric layer 130 is prepared on the polysilicon-gate material layer 104, nitrogen is removed from the surface region of the antireflection coating layer 150 of oxynitride silicon on the dielectric layer 130, a photo-resist is fitted onto the antireflection coating layer 150, from which nitrogen is removed, and a pattern is prepared from the antireflection coating layer 150 and metallic interconnecting bodies 142 are prepared.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to electronic semiconductor devices. More particularly, the present invention relates to antireflective structures and methods of making the same.

[0002]

Semiconductor integrated circuits with highly integrated devices include short gates for field effect transistors, small area emitters for bipolar transistors, and thin interconnects between the devices. Requires a minimum size structure.
Typically, the creation of such polysilicon structures or metal structures (or stacks of metal or metal silicide on polysilicon) involves photolithography through a wire with the required structure pattern. By exposing the resist to radiation, the positioning of such structures in a photoresist layer above a polysilicon or metal layer is performed. During this exposure, radiation reflected from the underlying material (eg, polysilicon, metal,...) Degrades the pattern created in the photoresist.
Therefore, an antireflective coating (ARC) layer is provided over the polysilicon or metal. Commercially available anti-reflective coatings include organic materials and T
iN. These materials strongly absorb radiation at that wavelength, such as polymers with dyes for absorption.

After exposing and developing a photoresist, a pattern is formed on a lower layer formed by adding an antireflection coating and a certain material (polysilicon, metal,...). An anisotropic etch is performed (or the antireflective coating is first wet-developed and then the underlying material can be anisotropically etched) using the photoresist as an etch mask. In this way, the minimum feature line width is equal to the minimum line width that can be produced in the photoresist by development.

One approach to overcoming line width limitations is to create a photoresist in a pattern, and then subject the photoresist created in the pattern to an isotropic etch to reduce its size, and Is to further reduce the original line width to imitate. However, this method has the problem that the isotropic etching of the patterned photoresist also etches the anti-reflective coating.

Ogawa et al., 2197 Proc. SPIE 722
(1994) disclose silicon oxynitride (Si _x O) as an anti-reflective coating (ARC) layer on oxide-coated tungsten silicide and on an aluminum layer for i-line.
And the use of the _Y N _Z), discloses and the use of exposure by deep ultraviolet as the thickness of the quarter wave plate so that the interference occurs destructive upon reflection (wavelength 248nm and 193 nm).

[0006] Chemically enhanced photoresists used with deep UV exposure are sensitive to nitrogen-containing surfaces such as silicon nitride, silicon oxynitride, tantalum nitride, and the like. The high electron density in such nitrogen effectively reduces the sensitivity of the resist at the surface, thus leaving a "footprint" after exposure and development. Therefore, there is a problem when using silicon oxynitride as the ARC.

[0007] Photoresists adhere better to hydrophobic surfaces than to hydrophilic surfaces. Therefore, Si (C
Instead of H ₃₎ OH surface group with a group _3, hexamethyldisilazane (HMDS, it is known to treat the surface of the wafer with agents such as hexamethyldisilazane).
See US Pat. No. 5,501,870, which discloses an automated HMDS application system.

[0008]

SUMMARY OF THE INVENTION In accordance with the present invention, an integrated circuit having a plasma surface treatment on a silicon oxynitride anti-reflective coating (ARC) layer to limit the effect of surface nitrogen on photoresist. A manufacturing method is obtained. Silicon oxynitride has a relatively low dielectric constant, and silicon oxynitride can be used as a hard mask that remains in place over gates and / or interconnects.

The anti-reflective coating according to the invention and its method of manufacture have the advantage that they are compatible with standard integrated circuit processing steps.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS The drawings are intended to aid in a clear understanding of the present invention.

Overview In a preferred embodiment, silicon oxynitride (Si _x O
_y N _z) performs processing in a plasma containing oxygen to antireflective coating member (ARC) layer. Such an ARC layer is used between the photoresist layer and the underlying polysilicon or metal to be patterned. The ARC limits the exposure radiation of the photoresist from being reflected from polysilicon or metal. This avoids false exposure of the photoresist. The plasma treatment of the preferred embodiment removes nitrogen from the surface, thereby limiting the loss of photoresist sensitivity due to nitrogen. FIG. 20 shows the removal of nitrogen. The composition and thickness of the silicon oxynitride ARC layer are determined by the optical constants of the photoresist and the underlying material, for example, polysilicon, titanium nitride, aluminum, and the like.

The refractive index and extinction coefficient (the real and imaginary parts of the square root of the dielectric constant) of silicon oxynitride vary with composition. (See FIG. 15.) Therefore, the composition was chosen to have an optical constant that adjusted the amplitude of the reflected wave according to the reflectivity of the underlying material; and
The thickness of the oxynitride layer is selected so that the reflected wave is canceled by the interference of the half-wave plate.

The patterned ARC layer of silicon oxynitride can also be used as a hard mask,
And the resulting integrated circuit can have the silicon oxynitride remaining on the gate and / or the interconnect or both, or the silicon oxynitride remaining on any of these Can not have. The silicon oxynitride of the preferred embodiment has a relatively low dielectric constant (e.g., 4.1-4.2, and thus is comparable to the dielectric constant of the oxide), and thus the capacitive coupling between adjacent interconnects or gates. Silicon oxynitride does not contribute to the fringing field.

First Preferred Embodiment FIGS. 1 to 13 show a field effect transistor (for example, a CM).
FIGS. 4A to 4C are cross-sectional views of various stages of a method of manufacturing a first preferred embodiment of an integrated circuit with an OS or BiCMOS. The lithography of this example has a minimum line width of 0.25 μm and a minimum metal interconnect width of 0.25 μm (gate length) along with a minimum polysilicon line width (gate length) of 0.18 μm. Circuit provided. This preferred embodiment has the following various steps.

(1) Shallow trench isolation and twin wells for LOCOS or CMOS devices (with optional addition of memory cell array wells and bipolar device buried layers)
Starting with a wafer 102 of silicon (or silicon on insulator) with. Threshold adjustment implant (this can be different for cell transistors and various peripheral transistors)
And create a gate dielectric. Thickness 300
A layer 104 of nm polysilicon gate material is deposited. See FIG.

(2) Deposit a (hydrogenated) silicon oxynitride matching layer 110 from flowing silane and nitrite by PECVD to a thickness of 29 nm on a polysilicon coated wafer. I do. See FIG. The composition and thickness of the silicon oxynitride are selected according to the reflectivity of the lower material. Especially in the case of polysilicon 104,
The ratio of silicon to oxygen to nitrogen is 38: 53: 9 (ie,
S _0.38 O _0.53 N _0.09 ).
This silicon-rich silicon oxynitride also contains about 10% bound hydrogen, but it is difficult to measure the exact hydrogen percentage. This composition gives measured optical constants of n = 2.11 and k = 0.55 (theoretically n = 2.15 and k = 0.60). Thus, a 29 nm thick layer provides a quarter wave plate at 248 nm. For a wavelength of 193 nm, the layer thickness will be even smaller and the optical constants will be slightly different. See the description below for the composition of the oxynitride.

(3) Place the wafer in a plasma reactor (which can be part of an apparatus with a plasma-enhanced deposition vessel from the previous step) and add N ₂ O
And Ar plasma is excited. Then, active oxygen from the plasma replaces nitrogen on the surface of oxynitride 110 and near the surface. Plasma treatment with a partial pressure of N ₂ O mTorr and a plasma power of 130 watts gives a top
m of nitrogen are removed. See FIG. 20, which shows the concentration (atomic percent) of oxygen and nitrogen near the surface of the plasma treated silicon oxynitride layer. Within the top 1 nm, oxygen increases from 53% to about 65% and nitrogen increases from 9% to 0%.
%.

Another method of depositing a thin (eg, 5 nm) silicon dioxide layer over silicon oxynitride to separate nitrogen from photoresist is to alter the average composition and thickness of the layer. I refuse. See the description of the plasma treatment below.

(4) Spin-on photoresist layer 112 that is sensitive to 248 nm radiation (deep ultraviolet) and has an average thickness of 900 nm. See FIG.

(5) Exposing the photoresist 112 to the gate and the interconnect at the same level as the gate with radiation having a wavelength of 248 nm through a mesh line. The minimum line width exposed can be about 250 nm. During the exposure of the photoresist 112, the silicon oxynitride 110 acts as an interference anti-reflection layer. Photoresist 112
Is developed. FIG. 4 showing different heights of photoresist created in a pattern possible with LOCOS separation
See

(6) The photoresist formed in the pattern is reduced (line width is reduced) by isotropic etching. This isotropic etch can be an oxygen / nitrogen plasma etch in a high density plasma reactor with a small bias applied to limit the ion bombardment to be isotropic. The final minimum linewidth is 180 nm (although down to 60 nm can be achieved with good linewidth control). Therefore, the minimum line width photoresist is 900nm x 250nm
From 850nm x 180nm. See FIGS. FIGS. 4-5 show (exaggerated) the reduction of the original photoresist line 114 created in the pattern to a photoresist line 116. Alternatively, if the line width is sufficient to remain exposed, the step of reducing the photoresist created in the pattern can be omitted.

(7) Exposed portions of silicon oxynitride 110 are removed by anisotropic plasma etching using CF ₄ or another fluorine source. This etch also acts as a breakthrough etch (to remove surface oxide) on the next stage polysilicon 104. This etching is
It can be performed just before in the same container as the etching. This etch also reduces the height of the photoresist to about 700 nm. See FIG.

(8) Add the remaining silicon oxynitride 110 and photoresist to the polysilicon 104
The gate 106 and the same level of interconnect 108 as the gate are made using as an etch mask for the anisotropic plasma etch of FIG. This etching can be performed by plasma obtained by adding oxygen to HBr. The etching by plasma obtained by adding oxygen to HBr is very selective with respect to oxides and oxynitrides. Thus, even if the polysilicon etch removes the photoresist, the anti-reflective layer of oxynitride remains because the etch is selective, and sufficient etch masking is obtained. FIG. 7 illustrates a gate 106 having oxynitride on top and an interconnect 108 at the same level as the gate. The gate material could also provide a polysilicon emitter for bipolar devices that require pre-base implantation. The height of the gate 106 is 300 nm and the length is 180 nm. (FIG. 7 is a longitudinal cross-sectional view of a gate. Typically, the gate has a width much greater than its length.)

(9) The gate, oxynitride, and any remaining resist are used as implantation masks,
Injecting a small amount of impurities into the drain is performed. It also does not require strict lithographic masks for CMOS or BiCMOS circuits. These circuits will also remove any remaining resist. See FIG.

(10) Create sidewall dielectric spacers 120 over the gate (and interconnect at the same level as the gate) by aligning and depositing a dielectric layer and then performing an anisotropic etch. The sidewall dielectric can be silicon nitride and the anisotropic etch can be an etch by a plasma of fluorine plus an inert gas. This sidewall spacer etch will also remove some (or all) of the oxynitride on top of the gate and the interconnect at the same level as the gate. Sources and drains are created by introducing the added impurities. See FIG. In yet another embodiment, self-aligned silicidation will be performed to create silicide on both the gate top and the source / drain. By removing any oxynitride remaining on the top of the gate and any oxide remaining on the source / drain surfaces, and depositing a blanket metal (Ti or Co or Ni) and then Reaction with the lower silicon
Then, the unreacted metal (or Ti in a nitrogen atmosphere)
This silicidation is performed by removing TiN). FIG. 10 shows the resulting silicide.

(11) (such as refluidized BPSG or a stack of matched and planarized layers)
A planarized premetal dielectric layer 130 is created. (This planarization is performed by chemical mechanical polishing (CMP,
chemical mechanical polishing) or resist etching back. 3.) A hole through the dielectric layer 120 is then photolithographically defined and etched for contact to the source / drain and gate / interconnect. See FIG. The anti-reflective layer for this lithography can also be oxynitride, but the reflection at deeper locations becomes important because the underlying oxide is transparent.

(12) An embedded memory using a memory cell with one transistor and one capacitor
For structures having a cell array, bit lines and cell capacitors can then be created. Such steps are not shown for clarity.
The accompanying additional dielectric layer deposited on the dielectric 130 can be considered just a part of the dielectric 130 in the figure.

(13) 50 nm Ti, 50 nm Ti
N, 300 nm W (with Cu and Si added) or
Uses a metal stack such as Al, 50 nm TiN (with hole filling).
Blanket deposit (including filling). Ti at the bottom and
TiN forms a barrier to diffusion and the top Ti
N forms an anti-reflective coating for lithography.
Prior to the deposition of W or Al, the Ti at the bottom is the source / drain
Can react with ins to form silicide, which
Can stabilize metal / silicon contact
You. Ti and TiN are formed by physical vapor deposition (PVD, physic).
al vapor deposition) or chemical vapor deposition (CVD, chem
ical vapor deposition) (for example, TiCl _Four+ NH_Three
(→ TiN + HCl). Al
Minium is deposited by PVD and then
Or by forced deposition into the holes by CVD.
Wear. W can be deposited by CVD. Or
In contrast, W is deposited on a CVD blanket and
And then do an etching back and put W only in the hole
Leave, then deposit aluminum blanket
This allows the holes to be filled with W.

(14) On blanket metal 140
A silicon oxynitride antireflection coating layer 150
I can. See FIG. Again, the optical constant according to the reflectivity of the metal
Select the composition of the oxynitride to give a number, and
Select the thickness of the oxynitride layer to be a one-half wavelength plate
You. For example, 30 nm T on 370 nm aluminum
In the case of iN, the reflectance is larger than that of polysilicon
And oxynitride is almost Si_0.469O_0.446
N_0.085Must. This Si_0.469O _0.446
N_0.085Has n = 1.9 and k = 0.15. This value
Depends on the thickness of TiN and aluminum
(For example, a field of 24 nm TiN over 500 nm Al
If Si_0.44O_0.47N_0.085Is used).
If the silicon concentration is high, the small
Electricity occurs. This dielectric constant value is the dielectric constant of silicon dioxide.
Rate and therefore oxynitride
By expanding the field, adjacent interconnects can be
It does not detrimentally increase the capacitive coupling between them.

In contrast to the lower uncapped aluminum and deep ultraviolet (248 nm) exposure, n = 2.
Take 16 and k = 0.83. This means that 248nm / 4 * 2.
16 = means a thickness of 29 nm. Note that this extinction coefficient is much larger than the extinction coefficient of oxynitride for TiN and polysilicon. This is due to the high reflectance of aluminum.

(15) In order to remove nitrogen from the top 2 to 3 nm of the silicon oxynitride layer 150, a treatment is performed with a plasma containing oxygen (for example, N ₂ O). See step (3) above.

(16) Photoresist is spin-on and patterned to define first level metal interconnects. See FIG. 12, which shows a resist 152 formed in a pattern with a minimum line width of 250 nm. Again, a simple fluorine-based plasma etch is performed to remove the exposed oxynitride without removing much of the patterned resist. Since the width of the interconnect is greater than the width of the gate, a reduction in resist line width is not required.

(17) Anisotropic plasma etching is performed on the metal using the patterned resist and oxynitride as etching masks, thereby forming interconnects 142. A chlorine-based plasma with some fluorine is used for copper-added aluminum and TiN, and a fluorine-based plasma for tungsten. FIG.
See

(18) TEO containing oxygen or ozone
Due to the plasma-enhanced decomposition of the S
On top of 2, a matched oxide liner 150 having a thickness of 50 nm is deposited. The liner 150 passivates the metal surface,
It prevents metal atoms from diffusing into the dielectric at the intermediate metal level. The dielectric can be a low dielectric constant material such as porous silica or fluorinated parylene. Next, an intermediate metal level dielectric is deposited over the liner coated interconnect. The intermediate metal level dielectric may be comprised of two or more porous silicas, such as porous silica between a first level interconnect and porous silica and fluorinated silicon dioxide over the interconnect. It can be a laminate of materials.

(19) A hole is created in the intermediate metal level dielectric, similar to the hole creation of step (11).
Next, a second level interconnect is created on this intermediate metal level dielectric by repeating steps (13)-(18) above. By repeating similar steps, third level interconnects, fourth level interconnects, fifth level interconnects,... Can be created.

Composition of Silicon Oxynitride The refractive index and extinction coefficient of silicon oxynitride change with the composition. As shown in FIG. 15, as the concentration of nitrogen increases, n and k increase. Thus, silicon oxynitride as an anti-reflective layer requires two parameters (layer thickness and composition) to match the reflectivity of the underlying material such that the net reflectivity from the anti-reflective layer is zero. )give. In particular, consider a simple case where the number of reflections is one. That is, intensity 1 radiation transmitted through the photoresist is incident on the anti-reflective layer, and r% (typically about 5% to 10%) is reflected (with a phase difference of π). Back to the photoresist. Then, (1-r)% transmits through the antireflection layer, and at the time of this transmission, it is attenuated by a factor e ^−kt . Here, k is the extinction coefficient, and t is the thickness of the antireflection layer. At the interface with the lower material, R% reflects (with a phase difference of π),
The remainder is then transmitted and / or absorbed by the underlying material. The reflected portion R also undergoes attenuation by e ^−kt as it passes through the anti-reflective layer on returning, and re-enters the photoresist. Therefore, the portion reflected from the lower material is R (1-r) e- ^2kt ,
And this should be offset by the first reflected portion r. For this cancellation to take place, the amplitudes must be equal (r = R (1-r) e- ^2kt ) and the phases must differ by .pi .. This means that the thickness t
Must be a quarter of the wavelength.
The wavelength in the antireflection layer is obtained by dividing the wavelength λ of the radiation in vacuum by the refractive index of the antireflection layer. Therefore,
t = λ / 4n and the composition of the oxynitride is given by the ratio k / n
Is selected so as to satisfy the following equation.

[0037]

## EQU1 ## r = R (1-r) e ^-k λ ^{/ 4n}

[0038]

K / n = 4 / λ [log (R) + log ((1
-R) / r)]

Of course, the reflectance r is determined by n and k and the optical constant of the photoresist, but the reflectance r is relatively constant over a certain range of n and k. Similarly, once the lower material is given, R (R also varies with n and k) is approximately known, and a composition can be chosen that gives the required k / n.

FIG. 16 shows the interface between the resist and the oxynitride when the thickness of the oxynitride layer is 29 nm.
5 is a graph of the net reflection intensity reflected back into the resist as a function of the oxynitride optical constants, using a more precise model of reflection at the polysilicon interface. The inside of the central contour indicates that the area where the net reflectivity into the resist is 1% or less. FIG. 16 also shows a curve of the relationship between n and k of silicon oxynitride as shown in FIG. 15 superimposed on the calculated net reflectance. This curve passes through the center of the region where the net reflectivity is less than 1%. This indicates that targeting the composition at the central location will provide robust oxynitride parameters.

In the case of a multi-layer metal stack (or silicified polysilicon, etc.), the model of reflection also includes reflection from the underlying metal interface. The preferred embodiment silicon oxynitride ARC described below produces a small net reflection. (A) 20 nm TiN on 360 nm aluminum
In this case, 25 nm thick Si _0.469 O _0.446 N _0.085 is used. This material has n = 1.90 ± 0.02 and k = 0.14 ± 0.02
Having. (B) 25 nm TiN on 500 nm aluminum
In this case, Si _0.44 O _0.47 N _0.085 is used.

These silicon oxynitrides contain about 10% nitrogen.
A similar (i.e., equal to within 10%) amount of silicon, as opposed to having a lesser composition but about twice the amount of silicon as silicon dioxide And oxygen. However, the dielectric constant of these silicon oxynitrides is about 4.1 to 4.2, and the value of this dielectric constant is almost the same as that of oxide. Therefore, this oxynitride can be used as a hard mask,
Then, after etching, it can remain on top of the metal interconnect. This is because lower dielectric constants do not increase the capacitive coupling between adjacent interconnects, as do high dielectric constant materials such as silicon nitride. See FIG. FIG. 14 shows a silicon oxynitride ARC 150 and a 5 nm thick oxide liner 160 over the interconnect 142.

Plasma Treatment of Oxynitride Surface treatment of silicon oxynitride ARC with oxygen-containing plasma is shown in the table below, which shows the experimental results with N ₂ O plus Ar plasma.
The effect on optical properties is very small.

[0044]

Table 1 Treatment Thickness (nm) nk As deposited 31.5 1.98 0.67 20 seconds, 130 watts 30.8 1.93 0.65 to 0.66 40 seconds, 130 watts 30.7 1.92 0.65 20 seconds, 200 watts 30.8 1.92 0.65 to 0.66 Oxide cap 35.8 1.82 0.62

The last row (5 nm oxide cap)
Instead of the nitrogen removal plasma treatment, silicon oxynitride A
This is compared to another embodiment where a thin layer of silicon dioxide is deposited over the RC. Such an oxide capping scheme introduces another interface for reflection and complicates the anti-reflective properties.

Various nitrogen removal plasmas can be used.
Wear. The basic reaction is that one of the oxygens places nitrogen on the surface
It is a change reaction. Therefore, oxygen plasma (eg,
O _TwoTo the oxygen) or oxygen to the nitrite oxide
And the like can be used. N_TwoO plasma?
Both oxygen and nitrogen atoms are on the surface of the oxynitride.
Collisions, but oxygen preferentially displaces nitrogen.
The partial pressure of the gas containing oxygen is less than 1 minute.
Be in a range such as 100 millitorr to 10 torr
And will be able to. Plasma bias, nitrogen removal
Help determine the depth of the area.

Another embodiment of the oxygen plasma treatment is to terminate the oxynitride deposition to obtain a nitrogen-depleted surface by converting N ₂ O to silane to O ₂ at the end of the oxynitride.
It is to switch to the one that has been added. However, this alternative embodiment has problems with controlling the deposition of oxide films of 5 nm or less and controlling the uniformity of the film.

The ray reduction 17 of width, to the line width of the various initial resist, stated oxygen resist etch (which removes the resist 80 nm) was used oxynitride antireflection layer in the case of FIG. 9 is a diagram illustrating the robustness of resist line width reduction created in a pattern. FIG. 17 shows the standard deviation seen in the line width reduced by the three-sigma curve of FIG. Thus, the reduction from 220 nm to 60 nm is about 2 nm to 3 nm.
Has a standard deviation of This robust large linewidth reduction using a silicon oxynitride antireflective layer allows the linewidth of the original resist to be patterned in a range where lithography is well controlled.

Preferred Embodiment of the Disposable Gate FIGS. 18a to 18d show a method of a disposable gate for manufacturing an integrated circuit using a silicon oxynitride antireflection layer. In particular, steps (1) to (10) are performed to have a polysilicon dummy gate with sidewall spacers and source / drain made in the substrate. To create a dummy gate length of only 60nm,
The reduction of the resist created in the pattern is used. This means that the original dummy gate length of 220 nm is followed by an 80 nm resist etch (see Figure 17).
(See FIG. 17). The resulting structure is similar to the structure of FIG.

500 nm dielectric such as TEOS oxide
And exposes the top of the polysilicon dummy gate by planarization in a CMP-like manner.
FIG. 18a shows a dummy gate 505 and a dielectric 530.
It is shown. The dummy gate 505 has a height of about 2
00 nm, length can be 60 nm.

Using HB + O ₂ plasma, dummy dummy
The gate 505 is removed by etching. Optionally, the gate oxide is removed, and a new gate oxide is thermally grown on the bottom of the trench left by the removal of the dummy gate 505. Next, the trench is filled and the dielectric 530 is covered by blanket depositing a gate material such as TiN or a stack of different metals. See FIG. 18b. FIG. 18b shows a metal gate material 507 having a thickness of 200 nm.

Silicon oxynitride having a composition (optical constant) compatible with the gate material is deposited to a thickness of 29 nm and then surface treated with oxygen plasma, and then
Spin on photoresist that is sensitive to 48 nm radiation. Photoresist is patterned to define a 250 nm long gate top, and photoresist created for this pattern (line width not reduced)
Is used to etch the gate material 507, thereby forming a T-type gate 506. See FIG. 18c.

The steps (11) through (11) can be accomplished by depositing dielectrics, creating holes, creating first level metal interconnects, etc.
Continue (19). See FIG. 18d.

Damascene Preferred Embodiment Since the linewidth reduction of the photoresist is used only at the gate level, the metal interconnect structure of the preferred embodiment can be replaced with a damascene interconnect structure. In particular, the steps (1) to (13) are repeated by changing the step (13) of initially filling the holes, and then depositing a second dielectric level and photo-locating the groove in the dielectric. Define by lithography and then etch the dielectric to define the trench, and then CMP or etch back the blanket metal leaving only the metal in the trench and thereby creating the interconnect . FIG. 19 shows one metal level with gate 606, pre-metal level dielectric 630, filled hole 6
44 is an illustration of a damascene structure for the first metal level dielectric 650. FIG.

Modification Example An anti-reflective coating of silicon oxynitride (A) with a nitrogen removal surface treatment or a high concentration of silicon for low dielectric constant.
Various modifications can be made to the preferred embodiment while retaining the characteristics of the (RC) layer.

For example, silicon oxynitride can have a different composition, but still have a k / n ratio that can be tuned to one or more underlying materials.

With respect to the above description, the following items are further disclosed. (1) (a) depositing an anti-reflective coating of silicon oxynitride on a layer of material to be patterned;
(B) removing nitrogen from the surface region of the anti-reflective coating of silicon oxynitride; and (c) attaching a photoresist to the silicon oxynitride anti-reflective coating from which nitrogen has been removed. Manufacturing method for integrated circuits. (2) Performing oxygen plasma treatment on the silicon oxynitride anti-reflective coating removes surface nitrogen and enhances photoresist adhesion. Silicon oxynitride has a high silicon concentration and a low dielectric constant, and therefore does not require removal after being used as a hard mask.

The following pending patents disclose the contents related to the present application. Serial No. 08 / 678,847, 1996
Filed December 7, 2012 (TI-20565) and serial number
No. 60 / 049,006, filed on September 6, 1997 (TI-25277).
These applications are assigned to the same assignee as the assignee of the present application.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of the first stage of a method of manufacturing a preferred embodiment integrated circuit.

FIG. 2 is a cross-sectional view of the next stage of FIG. 1;

FIG. 3 is a cross-sectional view of the next stage of FIG. 2;

FIG. 4 is a cross-sectional view of the next stage of FIG. 3;

FIG. 5 is a cross-sectional view of the next stage of FIG. 4;

FIG. 6 is a cross-sectional view of the next stage of FIG. 5;

FIG. 7 is a cross-sectional view of the next stage of FIG. 6;

FIG. 8 is a cross-sectional view of the next stage of FIG. 7;

FIG. 9 is a cross-sectional view of the next stage of FIG. 8;

FIG. 10 is a cross-sectional view of the next stage of FIG. 9;

FIG. 11 is a cross-sectional view of the next stage of FIG. 10;

FIG. 12 is a cross-sectional view of the next stage of FIG. 11;

FIG. 13 is a cross-sectional view of the next stage of FIG. 12;

FIG. 14 is a cross-sectional view of the next stage of FIG. 13;

FIG. 15 is a diagram showing a change in an optical constant depending on a composition.

FIG. 16 shows a net reflection.

FIG. 17 is a diagram showing a reduction in line width.

FIG. 18 is a cross-sectional view of another preferred embodiment, wherein a is a diagram of the first stage, b is a diagram of the next stage after a, c is a diagram of the next stage of b, and d is a diagram of the next stage. Next stage diagram.

FIG. 19 is a diagram of a preferred embodiment of a damascene.

FIG. 20 is a diagram showing distributions of oxygen and nitrogen.

[Explanation of symbols]

 150 Anti-reflective coating

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/3205 H01L 21/88 B 21/8238 27/08 321D 27/092 (72) Inventor Guoxian Singh United States of America Texas, Dallas, Audelia Road 11700, number 417

Claims (1)

[Claims] A) depositing an anti-reflective coating of silicon oxynitride on a layer of material to be patterned; and b) removing nitrogen from the surface region of the anti-reflective coating of silicon oxynitride. And (c) attaching a photoresist to the silicon oxynitride antireflective coating from which nitrogen has been removed.