JP2000056971A - High-speed arithmetic processor and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute a program in data dependency relation fast by extracting information on data dependency relation and performing static prediction when a source program is compiled, and dynamically predicting and selectively executing an instruction which is not solved so far and has high prediction probability at the time of execution. SOLUTION: A compiler 2 takes a morpheme analysis and a syntax analysis of a C source code 1 to generate a binary code. A simulator 4 registers in a profile image table 5 a pair of the line of an instruction in data dependency relation of an object to be predicted and a dependent instruction among instructions in data dependency relation. In the profile image table 5, the object instruction to be predicted among the instructions in the data dependency relation is registered. A compiler 6 generates a binary code 7 in execution form and registers an instruction code and a dependent instruction in the data dependence relation in the binary code in execution form corresponding to line numbers (address). The analysis and prediction of the source program and the fast execution of the compiled instruction in executable form are enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a high-speed arithmetic processing device and a recording medium for analyzing a source program to make predictions and executing the executable-format instructions obtained by compiling the source program at a high speed.

[0002]

2. Description of the Related Art Conventionally, in order to improve the execution performance of a processor, when there is a branch instruction, a branch destination is predicted and executed in advance, and if the prediction result is correct, execution is continued from the one after the preceding execution. If the prediction result is wrong, the preceding execution is canceled and another branch destination is executed.

[0003]

As described above, conventionally, prediction of a branch destination, that is, branch prediction of a control flow, has been performed. However, data necessary for execution in one task is executed in another task. There is a problem that data cannot be predicted when there is a so-called data dependency that the data cannot be executed unless it is determined and confirmed, and high-speed execution cannot be performed.

[0004] The present invention solves these problems,
Performs static prediction by extracting information on data dependencies at the time of compiling the source program and dynamically predicting and executing instructions that have data dependencies at the time of execution and are not resolved by the time of execution and have a high prediction probability, The purpose is to realize high-speed execution of programs that have a data dependency.

[0005]

Means for solving the problem will be described with reference to FIG. In FIG. 1, a compiler 2 generates a binary by performing morphological analysis, syntax analysis, and the like on a C source code.

The simulator 4 selects an instruction to be predicted from instructions having a data dependency and registers it in the profile image table 5. The profile image table 5 is for registering an instruction to be predicted among instructions having a data dependency (see FIG. 4 described later).

The executable binary 7 is an executable binary (see FIG. 5 described later). Next, the operation will be described. The compiler 2 analyzes the C source program, sets the data-dependent instruction in the profile image table 5 in association with the line number based on the result of the analysis by the simulator 4, and executes the instruction of the set data-dependent instruction. The prediction flag of the instruction whose data is to be predicted is set to ON.

At this time, the instruction for setting the prediction flag to ON is an instruction excluding the instruction whose data is determined in the own task. The instruction for setting the prediction flag to ON is an instruction that excludes an instruction whose data is determined in another task but has been determined by the time the instruction is executed.

In addition, when an executable instruction is executed, a data value is predicted with reference to a table in which instructions having a data dependency are set, and pre-execution is performed. Preemptive execution of instructions with a low correct answer rate is suppressed.

At this time, as a total of the results of the dynamic prediction, the correct flag is incremented by +1 when the prediction result is correct, and the incorrect flag is incremented by +1 when the prediction result is incorrect, and the correct answer rate is totaled.

[0011] Further, as an instruction having a data dependency,
It is a memory access instruction. Therefore, at the time of compiling the source program, information on data dependence is extracted and static prediction is performed, and at the time of execution, an instruction which has data dependence and is not resolved by execution and has a high prediction probability is dynamically predicted and selected for execution. By doing so, it becomes possible to execute a data-dependent program at high speed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments and operations of the present invention will be sequentially described in detail with reference to FIGS.

FIG. 1 shows a system configuration diagram of the present invention.
In FIG. 1, a C source code is an example of a source code, and here is a C language source code.

The compiler 2 generates a binary 3 by performing morphological analysis, syntax analysis and the like on the C source code 1. The binary 3 is an executable code generated by the compiler 2.

The simulator 4 selects an instruction to be predicted from instructions having a data dependency and registers the instruction in the profile image table 5. The profile image table 5 is for registering an instruction to be predicted among instructions having a data dependency, and as shown in FIG. 4 described later, a row number of an instruction having a data dependency and a pair of a dependent instruction. Is registered.

The compiler 6 generates an executable binary 7. The execution form binary 7 is an execution form binary in which an instruction code and a dependent instruction having a data dependency are registered in association with a line number (address) as shown in FIG. The details will be sequentially described below.

FIG. 2 is an explanatory view (part 1) of the present invention. In FIG. 2, PE (A) and PE (B) are processor elements that operate tasks A and B. Here, task A operates on PE (A), and task B operates on PE (B). The data dependency relationships (1), (2), and (3) are indicated by dashed-dotted arrows, and only the data dependency relationship (1) is an object to be predicted and executed in advance.

The PC (line number) is a program counter which holds (generates) the line number (address) to be executed at present. Next, the operation of FIG. 2 will be described.

(1) Task B operating on PE (B)
Performs the operation of z = y + 4 with the row number PC = 001. At this time, y during the calculation has a data dependency that it is necessary to wait until task A operating on the PE (A) is calculated and determined by the calculation of y = c + 2 at the row number PC = 101 and determined.

(2) Task B operating on PE (B)
Performs the operation of z = z + 2 with the row number PC = 002. At this time, there is a data dependency that the same task B has already been calculated and determined with the row number PC = 001 and does not need to wait.

(3) The task B operating on the PE (B) performs an operation of x = x + 5 with the row number PC = 003. At this time, x during the calculation has a data dependency such that the task A operating on the PE (A) is determined by the calculation of x = a + 1 with the row number PC = 100 and x = a + 1, and there is no need to wait.

Therefore, of the data dependencies (1), (2), and (3), only the data dependency that needs to be waited is (1), which is used to predict the value of the data of the present invention. This is an instruction to be executed in advance, and sets a prediction flag of a corresponding address (line number) of an execution format binary in FIG. 5 described later to 1 (prediction). For those that do not need to be predicted, the prediction flag is set to 0 (non-prediction). This means that a static prediction has been performed among the instructions that have a data dependency at the time of compilation. The above is summarized as follows.

(A) Instructions defined in the invoking task are not to be predicted (in the case of (2) in FIG. 2, they are not to be predicted). (B) Instructions that are defined in other tasks and whose data are determined before the execution of the instruction are not to be predicted (in the case of (3) in FIG. 2, are not to be predicted).

(C) An instruction which is defined in another task and whose data is not determined even when the instruction is executed is to be predicted (in the case of (1) in FIG. 2, it is to be predicted).

(D) As will be described later with reference to FIG. 8, the data of the instruction (c) is predicted, the simulation is actually executed, and only the instruction having a high accuracy rate of the prediction result is set as a prediction target, and Instructions with a low rate may be excluded from prediction targets.

FIG. 3 is an explanatory view (part 2) of the present invention. This shows an example of a source image program that runs on task B in FIG. Here, for example, the line number 001 executed on the task B in FIG. 2 is 001 add
% Rz,% ry, 4. 001 is a line number, a
dd is an addition instruction, and% rz,% ry, 4 add 4 to the contents (y) of the register ry and store the result in the register r.
z. Similarly, line numbers 121 and 20
0 describes ST (store instruction) and ld (load instruction).

FIG. 4 shows an example of a profile image table according to the present invention. This is a data-dependent instruction extracted from the source program and registered.
2 are registered in the row numbers 001, 002, and 003 of FIG. For example, the program counter dependent instruction 1 dependent instruction 2 dependent instruction 3 001 101 --- is the instruction of the line number 001 executed by the task B in FIG. Represent. The second and third data dependencies are none here. The instruction of line number 200 is the first instruction having a data dependency (dependent instruction 1) 150 (register r
2) second (dependent instruction 2) 130 (register r3),
Third (dependent instruction 3) 121 (register r8).

As described above, by extracting and registering the line numbers of other instructions having a data dependency at the time of compiling at the time of compiling, the data value can be changed only for the instructions having the data dependency. It is possible to predict and execute in advance.

FIG. 5 shows an example of an executable binary of the present invention. This is an executable binary, in which the following items shown in the figure are registered. Address Instruction code Dependent instruction 1, Dependent instruction 2, Dependent instruction 3 Prediction flag 001 add% rz,% ry, 4 101--1 (prediction) 002 add% rz,% rz, z---0 (non-prediction) 003 add% rx,% rx, 5 100 --0 (non-prediction) As described above, the address (line number), instruction code, dependent instructions 1 to 3 and prediction flag f that have a data dependency are registered at the time of compilation. Thus, by predicting the value of the data for an instruction whose prediction flag is only 1 (prediction) at the time of execution and executing the instruction in advance, the data dependency is efficiently reduced at the time of execution based on the result of the selective static prediction. It is possible to execute a certain instruction in advance and realize high-speed execution of the CPU.

FIG. 6 shows another system configuration diagram of the present invention. This is performed at the time of execution, as shown in FIG.
The address (line number) set in the (program counter) is compared with the tag to output a hit when they match, and to output a mishit when they do not match, and to read out the value and difference when a hit occurs. This is a hardware image in which a prediction value is calculated by performing a calculation (here, for example, addition) by a calculator.

With the above configuration, the prediction flag is set to 1 in FIG.
It is possible to read out the address of the instruction set as (predicted), the value of the data of the variable at that time, and the difference between the previous and previous times at a high speed, predict the value of the variable having a data dependency, and execute the preceding execution. Become. Hereinafter, the operation at the time of execution will be sequentially described in detail.

FIG. 7 is an explanatory diagram of the present invention (No. 3, execution). This shows a state in which the line number 001 is set in the PC (program counter), and the task B operating on the PE (B) in FIG. 2 tries to execute z = y + 4 with the line number 001.

The initial value is the row number 0 which has a data dependency.
It indicates that the initial value of the variable y of the instruction 01 is 0. 1
The third time indicates that the execution result of the variable y of the instruction of the line number 001 having the data dependency relationship is 8.

The second time, the line number 0 having a data dependency
13 shows an example of prediction of a variable y of the 01 instruction. (A) shows the case where the value y = 16 predicted at the second time (8 + 8 = 16 obtained by adding the difference to the value at the first time) coincides with the value 16 of the actually executed y and is correct. In this case, updating is performed as shown below.

The PC value difference 001 16 8 (b) indicates that the second predicted value y = 16 (8 + 8 = 16 obtained by adding the difference to the first time value) does not match the actually executed y value 8. Indicates an incorrect answer. In this case, updating is performed as shown below.

PC value difference 001 8 0 As described above, the first value is predicted based on the initial value, and when it matches the actual execution result, the value at that time and the difference from the previous time are registered. Is repeated, a table as shown in FIG. 8 to be described later can be created. Then, since the execution result predicted at the time of the correct answer is correct, the subsequent processing can be executed. On the other hand, at the time of the incorrect answer, the result of the prediction is canceled and re-executed with the determined variable value. As a result, the value and the difference that become correct at the time of execution are registered as shown in the table of FIG. 8, the ratio of the number of correct answers is predicted for a predetermined threshold value (for example, 60% or more), and the prediction of other instructions is performed. Is suppressed, the probability of the prediction rate is improved, the cancellation rate is reduced, and the overall execution speed can be greatly improved.

FIG. 8 is an explanatory diagram (No. 4, during execution) of the present invention. This is a list in which the values of variables at the time of the correct answer and the difference from the previous time are registered for the instruction (the line number of the instruction) to be predicted by the procedure of FIG. The correct answer rate is a predetermined threshold (for example, 60
% Or more) and the prediction flag of other instructions is set to 0.
(Non-prediction) is set, and it is possible to dynamically collect statistics and dynamically increase the accuracy rate of prediction of data having a data dependency to perform high-speed execution. Here, PC = 001 (line number 001) is executed n times, the correct answer is 13974 times, the incorrect answer is 64 times, and the correct answer rate is 60% or more. Instruction). on the other hand,
PC = 002 (line number 002) is executed n times, the number of correct answers is 21 times, the number of incorrect answers is 17365 times, and the correct answer rate is 6
Since it is 0% or less, the data prediction of the instruction having the data dependence (the instruction of the line number 002) is suppressed, and the processing speed is dynamically reduced at the time of execution to prevent the reduction in the processing speed due to the unnecessary load due to the cancellation. Becomes possible.

FIG. 9 is a block diagram showing one embodiment of the present invention.
FIG. 9A shows each of PE # 1 to PE # of the execution object.
The state of allocation to No. 4 is shown. Here, as shown in the figure, the execution objects are allocated to the four PEs # 1 to # 4, and at this time, the addresses (line numbers) of the instructions having the data dependency described above in association with each address (line number) are assigned. No.) are registered in the dependent instructions 1, 2, and 3 (collected and registered at the time of compilation). These four PE # 1
The execution objects respectively assigned to to # 4 are
It is sequentially executed by PEs # 1 to # 4 in (b).

FIG. 9B shows four PEs # 1 to # 4.
Shows the processing when each execution object is executed. Here, in each of the PEs # 1 to # 4, if the data dependence is YES and the dependency solved is NO, the values of the variables are predicted, and the execution objects are respectively executed based on the predicted values.

As described above, the execution object is
If the data is allocated to # 1 to # 4 and the data dependencies are YES in each of PEs # 1 to # 4, and if the dependency has been resolved is NO, the value of the variable is predicted, and the execution object is determined based on the predicted value. By executing, it is possible to precedely execute instructions having a data dependency with a high correct answer rate and to increase the processing speed.

FIG. 10 is a flowchart illustrating another operation of the present invention. This is a flowchart when dynamically predicting the value of a variable of an instruction having a data dependency described above.

In FIG. 10, S1 determines whether there is any dependency. This is because, for example, one of the dependent instructions 1, 2, and 3 is set in the execution object allocated to each PE in FIG. 9A, and it is determined whether the instruction to be executed has a data dependency. I do. In the case of YES, it is determined that there is a data dependency, and the process proceeds to S2. In the case of NO, it is determined that there is no data dependency, so the prediction flag is set to 0 (non-prediction) in S5.

In step S2, it is determined whether or not the data dependency exists but has been resolved. In the case of YES, since the data dependency has been resolved, the prediction flag is set to 0 (non-prediction) in S6. In the case of NO, the process proceeds to S3 because the data dependency has not been resolved.

In step S3, it is determined whether or not the correct answer rate of the result of predicting the value of the variable is high. This is because if the value of the instruction variable is predicted and the result is collected as shown in FIG. 8 and the data is predicted when the correct answer rate is high (for example, 60% or more), the speed can be increased. Since it is found, the value of the data of the variable of the instruction is predicted in S4. On the other hand, in the case of NO, the correct answer rate is low, processing accompanying the cancellation occurs, and if the prediction is performed, the processing speed is reduced. Therefore, the prediction flag is set to 0 (non-prediction) in S7.

As described above, there is a dynamic data dependency at the time of execution, and when the data dependency is not resolved and the accuracy rate at the time of data prediction is high, the value of the data of the instruction variable is high. Prediction is performed, data prediction is suppressed for the other instructions, and the execution speed of the instruction is dynamically analyzed to efficiently increase the speed.

FIG. 11 shows an example of the predicted correct answer rate of the present invention.
This is the benchmark program SC (SPECint
92, which is data obtained when a simulation of System Performance Evaluation Cooperative) is performed. The horizontal axis represents a program for performing various processes, and the vertical axis represents a predicted correct answer rate. The horizontal line portion of the bar graph in the figure represents the LOAD instruction portion, the horizontal line portion represents the STORE instruction portion, and the dotted portions represent OTHERS (LAAD, STORE).
Instruction other than the memory access instruction).
The symbols in the figure represent the following.

Comp: compress (compression program) eqn: eqnottt (C program) esp: epresse gcc: Compiler li: Solving 9 queens problem with lisp interpreter sc: Spreadsheet ave: Average FIG. 12 shows selective values of the present invention. Indicates the target instruction and the non-target instruction example (%) of the prediction. This is a classification of the benchmark program SC already described in FIG. 11, and is classified into the following items shown in the figure.

No dependency (when there is no data dependency): Solved (when there is data dependency but it has been solved by the time of execution): Prediction target (when there is data dependency and it has not been solved) : Instruction for which the value of the data of the instruction of the present invention is to be predicted ・ load: Instruction for loading data into memory ・ store: Instruction for storing data from memory to register ・ others: Instruction other than load and store memory access instructions Here, (1) described on the left side corresponds to (1) in FIG. 2 and is a ratio (%) of an object whose data dependency is predicted.

(2) is the ratio (%) of instructions having no data dependency, corresponding to (2) in FIG. (3)
Corresponding to (3) in FIG. 2, this is the ratio (%) of instructions for which there is a data dependency or for which the value of the data is resolved by the time of actual execution of the instruction.

Therefore, in the benchmark program SC, the prediction targets are comp, eqn, esp, gcc,
The ratio of li, sc, and Ave is between 9.2 and 11.6%. For these, the values of instruction variables are selectively predicted, and the reduction in processing due to the cancellation when predicting unnecessarily is eliminated. In addition, it becomes possible to predict the value of a variable of an instruction that has a data dependency of only one that is likely to be speeded up when predicted and execute it in advance. Further, since the memory access of the load instruction and the store instruction has a merit that the execution speed is slow and the preceding execution is high, the memory access instruction (the load instruction and the store instruction) is selected as a prediction target, and the variable of the instruction having the data dependency is selected. The value may be predicted and executed in advance.

FIG. 13 shows an example of the execution time of the present invention. This represents the time when each of the benchmark programs SC described above is simulated and executed, the horizontal axis represents a program for performing various processes, and the vertical axis represents the execution time (K cycles). The left side of the bar graph in the figure indicates no prediction, the center indicates prediction, and the right side indicates perfect prediction (when all predictions are correct). For example, in the case of sc, it has been found that, when the prediction of the present invention is performed, the speed can be increased by 20.9% of the time (the number of cycles) as compared with the case without prediction. More specifically, it has been found that 9.2% sc (spreadsheet) instructions included in the benchmark program SC can be predicted, and the speed can be increased by about 20.9% of the number of cycles. At this time, if all the predictions were correct, it could be simulated that the speed could be increased by about 34.5% of the number of cycles. For other programs in the benchmark program, the speed can be increased to the number of cycles with prediction in the center of FIG. 13 for each ratio to the whole shown in FIG.

[0052]

As described above, according to the present invention,
A configuration in which information on data dependence is extracted at the time of compiling a source program to perform static prediction, and at the time of execution, an instruction which has a data dependence and is not resolved by execution and has a high prediction probability is dynamically predicted and selected for execution. Therefore, a device that executes a program having a data dependency at a high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of the present invention.

FIG. 2 is an explanatory view (No. 1) of the present invention.

FIG. 3 is an explanatory view (No. 2) of the present invention.

FIG. 4 is an example of a profile image table according to the present invention.

FIG. 5 is an example of an executable binary of the present invention.

FIG. 6 is another system configuration diagram of the present invention.

FIG. 7 is an explanatory diagram of the present invention (No. 3, execution).

FIG. 8 is an explanatory diagram (No. 4, execution) of the present invention.

FIG. 9 is a configuration diagram of one embodiment of the present invention.

FIG. 10 is a flowchart illustrating another operation of the present invention.

FIG. 11 is an example of a predicted correct answer rate according to the present invention.

FIG. 12 is an example of a target instruction and a non-target instruction for selective value prediction according to the present invention.

FIG. 13 is an example of execution time of the present invention.

[Explanation of symbols]

 1: Source code 2, 6: Compiler 3: Binary 4: Simulator 5: Profile image table 7: Executable binary

Claims (8)

[Claims] 1. A high-speed processing apparatus for analyzing and predicting a source program, comprising: means for analyzing the source program; and a table for storing an instruction having a data dependency in association with a line number based on the result of the analysis. And a means for setting a prediction flag of an instruction of a data prediction target among the instructions having the data dependence set to ON. 2. The high-speed arithmetic processing device according to claim 1, wherein the instruction for setting the prediction flag to ON is an instruction excluding an instruction whose data is determined in its own task. 3. An instruction for setting the prediction flag to ON, wherein the instruction excludes an instruction whose data is determined in another task but which is determined by the time of execution of the instruction. Alternatively, the high-speed processing device according to claim 2. 4. A high-speed processing apparatus for executing an executable-format instruction obtained by compiling a source program at a high speed, comprising the steps of: executing an executable-format instruction by referring to a table in which data-dependent instructions are set; A high-speed processing apparatus comprising: means for predicting a value and executing the result in advance; and means for summing up the results of the dynamic prediction and suppressing the advance execution of an instruction having a low accuracy rate of the prediction. 5. The total of the results of the dynamic prediction, wherein the correct answer flag is incremented by +1 when the predicted result is correct, and the incorrect flag is incremented by +1 when the predicted result is incorrect, and the correct answer rate is totaled. Item 5. A high-speed processing device according to item 4. 6. The high-speed processing device according to claim 1, wherein the instruction having the data dependency is a memory access instruction. 7. A means for analyzing a source program, means for setting an instruction having a data dependency in a table in association with a line number based on the result of the analysis, and an instruction having a data dependency set in the table A computer-readable recording medium on which a program for functioning as a means for setting a prediction flag of an instruction of a data prediction target to ON is recorded. 8. A means for predicting the value of data with reference to a table in which instructions having a data dependence are set when executing an instruction in an executable format, and executing a preceding execution. A computer-readable recording medium in which a program for functioning as a means for suppressing an advance execution of an instruction having a low accuracy rate of a predicted prediction is recorded.