JP2000050271A - Image compressor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image compressor that can compress digital image data at high speed. SOLUTION: This image compressor is provided with a counter 24 that sets a zero flag, depending on whether or not data to be received are 0 and counts the number of zero run length to be received, a means 24 that cross-references the zero flag with the data when the data are 0, cross-references the zero flag with the run length when the data are not 0 and writes the result to a buffer, and a means 25 that reads the zero flag sequentially from the buffer and applies Huffman coding to a set of data, corresponding to the zero flag and the run length by setting 0 to the run length when the zero flag is not set and to a set of data stored next and the run length stored corresponding to the zero flag, when the zero flag read from the buffer is set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image compression apparatus, and more particularly to a digital image compression apparatus.

[0002]

2. Description of the Related Art One of the standard compression methods for digital still images is JPEG (joint photographic expert group).
) There is a method.

FIG. 9 is a block diagram showing the configuration of a conventional JPEG image compression apparatus. Hereinafter, the discrete cosine transform is referred to as DCT.
That.

[0004] The DCT and quantization section 31 performs DCT processing and quantization processing. In the DCT processing, image data is subjected to DCT processing in block units to obtain DCT coefficients. One block is composed of 8 × 8 = 64 image data. DCT
The coefficient represents a spatial frequency component of the image data. The quantization process quantizes the DCT coefficients and mainly reduces the amount of information of high frequency components. The DCT and quantization unit 31 outputs the quantized DCT coefficient CF1.

[0005] In the buffer 32, the DCT coefficient CF1 is written in block units. DCT coefficient C for one block
F1 is composed of 64 DCT coefficients. One DCT coefficient is, for example, 11 bits. The buffer 32 is 64
A DCT coefficient of × 11 bits is stored. Next, write timing to the buffer 32 will be described.

FIG. 10 is a timing chart showing a write operation to the buffer 32. The clock CLK is
This is an operation clock of the image compression device. DCT coefficient CF1
Is, for example, "D0, D1, 0, 0, 0, 0, D2, D
3 "in the order of one clock cycle from the DCT and quantization unit 31. Here, DCT coefficients D0, D1, D2,
D3 is a coefficient other than 0. Write address WA
Is a write address to the buffer 32. DCT
The coefficient CF1 is written to the address WA of the buffer 32 in one clock cycle.

[0007] In FIG.
It is determined whether or not the DCT coefficient CF1 read from Step 2 is 0. When the DCT coefficient CF1 is 0, the run length counter 33 counts the run length (run length) of 0 and outputs the run length RL to the Huffman encoding unit 35. The run length RL is a number of 0s that are continuously arranged.
For example, if the DCT coefficient CF1 is “0, 0, 0, 0”, the run length RL is 4. By obtaining the run length RL, run length encoding is performed.

The run length counter 33 has a DC
When the T coefficient CF1 is not 0, the run length RL is output as 0.

When the judging section 36 judges that the DCT coefficient CF1 is not 0, it outputs the DCT coefficient CF2 to the Huffman encoding section 35.

The Huffman encoding 35 includes an enable signal E
According to N, a set of the run length RL and the DCT coefficient CF2 is Huffman-encoded, and the compressed data CD is output. The Huffman encoder 35 converts the run-length RL and DC
A set of T coefficients CF2 is input, a Huffman table is looked up, and compressed data CD is output. In Huffman coding, compression is performed by allocating compressed data CD having a short code length to frequently used data.

The Huffman encoding unit 35 requires two clocks for one encoding process for internal processing reasons. That is, the compressed data CD is output in two clock cycles.
Next, the above processing timing will be described.

FIG. 11 is a timing chart showing the read operation from the buffer 32.

The read address RA is an address for reading from the buffer 32. DCT coefficient CF1
Is a coefficient read from the corresponding read address RA. Since the processing cycle of the Huffman encoding unit 35 (FIG. 9) is two clocks, the DCT coefficient CF1 is read from the address RA in two clock cycles in accordance with that.

The run length RL is a run length of 0 in the DCT coefficient CF1, and is generated two clocks (one cycle) later than the DCT coefficient CF1. DCT coefficient C
When F1 is D0 and D1, D0 and D1 are not 0, so that both run length RL are 0. Next, DC
When "0, 0, 0, 0" is input as the T coefficient CF1, the number of 0s is sequentially counted as "1, 2, 3, 4", and the count value becomes the run length RL. DCT coefficient C
When F1 is D2 and D3, since D2 and D3 are not 0, the run length RL is 0.

The DCT coefficient CF2 is calculated by the Huffman coding unit 3
5 (FIG. 9). DCT coefficient CF1
Are D0, D1, D2, and D3, the DCT coefficient CF
Since 1 is not 0, the DCT coefficient CF1 is
It becomes the T coefficient CF2. When the DCT coefficient CF1 is 0,
DCT coefficient CF2 maintains the previous value.

Only when the enable signal EN is at the high level, the Huffman encoding unit 35 executes the run length RL and the DCT.
The Huffman coding process is performed on the set with the coefficient CF2. The run length RL is the DCT coefficient CF2 that is set with it.
Represents the number of 0s before. For example, 0 before DCT coefficient D0
Is 0, the number of 0s before the DCT coefficient D1 is 0, and the number of 0s before the DCT coefficient D2 is 4.

The Huffman encoder 35 requires two clocks to process one set of data. Time T
1 is the time required for Huffman coding the eight DCT coefficients CF1, which is 16 clocks.

[0018]

The Huffman encoder 35
Is the time T1 to process the eight DCT coefficients CF1
(16 clocks). However, the Huffman encoding unit 35 actually performs processing only during the time when the enable signal EN is at the high level. The time T2 during which the enable signal EN is at the low level is wasted time because the Huffman encoding unit 35 does not perform the processing.

In FIG. 9, while the DCT and quantization unit 31 performs processing in one clock cycle, the Huffman encoding unit 35 performs processing in two clock cycles, so that a useless time T2 occurs.

It is difficult for the Huffman encoding unit 35 to process in one clock cycle. Huffman encoding unit 35
Compressed data C at high speed while processing at clock cycle
It is desired to generate D.

An object of the present invention is to provide an image compression device capable of compressing image data at high speed.

[0022]

According to one aspect of the present invention, DCT means for performing discrete cosine transform of image data;
A quantizing means for quantizing the data transformed by the DCT means, an input terminal for sequentially inputting the quantized data quantized by the quantizing means, and storing the quantized data inputted to the input terminal; A buffer capable of determining whether or not the quantized data input to the input terminal is 0, and setting a zero flag when the quantized data is 0, and a 0 flag input to the input terminal. And a run-length counter for counting the run length of the
When the zero flag and the quantized data are associated with each other and written into the buffer, and when the quantized data input to the input terminal is not 0, the zero flag and the run length are associated with each other and the buffer is stored in the buffer. There is provided a JPEG image compression apparatus having a writing unit for writing.

In the buffer, a set of a zero flag and quantized data or a set of a zero flag and a run length is written. Various processes can be performed on the information in the buffer by referring to the zero flag in the buffer.

According to another aspect of the present invention, zero flags are sequentially read from the buffer, and when the read zero flag is not set, the run length is set to 0.
And outputs a set of the quantized data corresponding to the zero flag and the run length. When the zero flag read from the buffer is set, the run length stored corresponding to the zero flag and the next stored run length are stored. JPEG image compression apparatus comprising: output means for outputting set quantized data as a set; and Huffman coding means for Huffman coding a set of run length and quantized data output from the output means. Is provided.

In the buffer, a set of a zero flag and quantized data or a set of a zero flag and a run length is written. By supplying a set of the run length and the quantized data to the Huffman encoding unit according to the zero flag stored in the buffer, the Huffman encoding unit can perform the encoding process efficiently and at high speed.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a J according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a PEG image compression device.

The controller 8 generates a clock CLK, exchanges timing signals with all other processing blocks, and adjusts timing between the processing blocks.

The DCT and quantization unit 21 performs a discrete cosine transform (DCT) process and a quantization process. The DCT process performs DCT processing on image data in block units,
Find the coefficient. One block is composed of 8 × 8 = 64 image data. The DCT coefficient represents a spatial frequency component of the image data. The quantization process quantizes the DCT coefficients and mainly reduces the amount of information of high frequency components. The DCT and quantization unit 31 outputs the quantized DCT coefficient CF1.

The run length counter 23 has a zero flag ZF and a run length RL according to the DCT coefficient CF1.
Outputs 1. The zero flag ZF is 1 if the DCT coefficient CF1 is 0, and is 0 if the DCT coefficient CF1 is not 0. In other words, the run length counter 23
If the CT coefficient CF1 is 0, the zero flag ZF is set (Z
F = 1), and if the DCT coefficient CF1 is not 0, the zero flag ZF is lowered (ZF = 0).

The run length RL1 is equal to the DCT coefficient CF1.
It is the number of 0s that are continuously arranged in the table. For example, DCT
If “0, 0, 0, 0” is sequentially input as the coefficient CF1, the run length RL1 is 4. Run length RL
By obtaining 1, run-length encoding is performed.

The buffer controller 24 writes the write data WD to the address WA of the buffer 22 according to the zero flag ZF, the run length RL1, and the DCT coefficient CF1.
Write to. The buffer 22 is, for example, an SRAM,
Stores 12-bit data WD. The buffer 22
It is necessary to have a capacity to store 12-bit data WD for one block (64 data). Next, the contents of the data WD will be described.

FIG. 2A shows the write data WD when the DCT coefficient CF1 is not 0. Write data W
D is a total of 12-bit data of the zero flag ZF of the upper 1 bit and the DCT coefficient CF1 of the lower 11 bits.
Since the DCT coefficient CF1 is not 0, the zero flag ZF is set to 0
become.

FIG. 2B shows the write data WD when the DCT coefficient CF1 is 0. Write data W
D is a total of 12-bit data of the zero flag ZF of the upper 1 bit and the run length RL1 of the lower 11 bits. Since the DCT coefficient CF1 is 0, the zero flag ZF
Becomes 1.

FIG. 3 is a timing chart showing writing to the buffer 22. The clock CLK is an operation clock of the image compression device, and is generated by the controller 8. The DCT coefficient CF1 is, for example, “D0, D1,
0, 0, 0, 0, D2, D3 ”in this order from the DCT and quantization unit 21 in one clock cycle. Where DC
The T coefficients D0, D1, D2, and D3 are coefficients other than 0.

In the figure, the zero flag ZF indicates 0 at a low level and 1 at a high level. DCT coefficient CF1 is 0
Otherwise, the zero flag ZF becomes 0, and when the DCT coefficient CF1 is 0, the zero flag ZF becomes 1.

The run length RL1 is equal to the DCT coefficient CF1.
Is the number of consecutive zeros in When the DCT coefficient CF1 is D0 and D1, the run length RL1 is both 0 because D0 and D1 are not 0. Next, the DCT coefficient CF
When "0,0,0,0" is input as 1, the number of 0s is sequentially counted as "1,2,3,4", and the count is set as a run length RL1. Next, when the DCT coefficient CF1 is D2 and D3, since D2 and D3 are not 0, the run length RL1 is 0.

The write data WD has a DCT coefficient CF
1, for the zero flag ZF and the run length RL1,
The data is written to the address WA of the buffer 22 with one clock delay.

The write data WD has a DCT coefficient CF1
Is not 0, it has the configuration of FIG. 2A, and when the DCT coefficient CF1 is 0, it has the configuration of FIG. In the figure, write data WD is represented by a set of left data and right data. The left data is the zero flag ZF, and the right data is the DCT coefficient CF1 or the run length RL1.

The write address WA is incremented in one clock cycle in principle, but the zero flag ZF
Is not incremented when it is 0 both last time and this time. As a result, when the data WD having the configuration shown in FIG. 2B is continuous, they all have the same address WA.
(For example, WA = “2”).

For example, the buffer 22 stores the following data WD at the following address WA.

WA = 0 WD = “0, D0” WA = 1 WD = “0, D1” WA = 2 WD = “1, 4” WA = 3 WD = “0, D2” WA = 4 WD = “0” , D3 "

Next, in FIG. 1, the buffer controller 24 outputs the data RD from the address RA of the buffer 22.
And supplies a set of the run length RL2 and the DCT coefficient CF2 to the Huffman encoding unit 25. The details will be described later with reference to the timing chart of FIG.

The Huffman encoder 25 has a run-length R
Huffman coding of a set of L2 and DCT coefficient CF2,
Generate compressed data CD. The Huffman encoding unit 25
A set of a run length RL2 and a DCT coefficient CF2 is input, a Huffman table is looked up, and compressed data CD is output. In Huffman coding, compression is performed by allocating compressed data CD having a short code length to frequently used data.

FIG. 4 is a timing chart showing the read operation from the buffer 22. The clock CLK is
This is an operation clock of the image compression device. The read address RA is an address read from the buffer 22. The read data RD is data read from the address WA.

In the data RD, the left data is the zero flag ZF and the right data is the DCT coefficient CF1 or the run length RL1. For example, when the zero flag in the data RD read from the address RA is 0 as in the case of the address RA = 0, the address RA is output after two clocks.
Is incremented, and the next (for example, address RA = 1)
) Of the data RD. On the other hand, for example, the address RA
= 2, the data RD read from the address RA
When the inside zero flag is 1, the address RA is incremented after one clock to read the next data RD (for example, address RA = 3), and the address RA is further incremented after one clock and the next (for example, address RA = 3). 4) Read data RD.

That is, when the zero flag ZF is 1, the zero flag ZF
Is read out, and the next data RD whose zero flag ZF is 0 is read out in the subsequent one clock. Thereby, the data RD in which the zero flag ZF is 0 can be read in two clock cycles.

Run length RL2 and DCT coefficient CF2
Is supplied to the Huffman encoding unit 25 (FIG. 1) with a delay of two clocks compared to the data RD. When the address RA = 0, the data RD has the zero flag ZF = 0 and the DCT coefficient CF
1 = include D0. Since the zero flag ZF in the data RD is 0, the run length RL2 becomes 0, and the DCT coefficient CF2 becomes CF1 (= D0). Address RA = 1,
4, the run length RL2 becomes 0, and the DCT
The coefficient CF2 becomes D1 and D3.

Data RD at address RA = 2 includes zero flag ZF = 1 and run length RL1 = 4. The data RD of the address RA = 3 is obtained by the zero flag ZF = 0 and DC
Includes T coefficient CF1 = D2. These two data RD form a set. In this case, the run length RL2 is RL1
(= 4), and the DCT coefficient CF2 is CF1 (= D2).
become.

The Huffman encoder 25 has a run-length R
Huffman coding is performed on a set of L2 and DCT coefficient CF2. The DCT coefficient CF2 is a sequence of non-zero DCT coefficients, and the corresponding run-length RL2 is
This is the number of zeros arranged before the T coefficient CF2. For example, DCT
The number of 0s before the coefficient D0 is 0, the number of 0s before the DCT coefficient D1 is also 0, and the number of 0s before the DCT coefficient D2 is 4
It is.

The Huffman encoding unit 25 requires two clocks to process one set of data for internal processing reasons. Time T1 corresponds to the eight DCTs shown in FIG.
This is a time required for outputting the coefficient CF1 after Huffman encoding, and is 8 clocks. The compressed data CD (FIG. 1) corresponding to the eight DCT coefficients is also output at eight clocks.

As shown in FIG. 11, in the conventional image compression apparatus, the time T1 for outputting eight DCT coefficients CF1 after Huffman coding is 16 clocks.

The image compression apparatus according to the present embodiment can output the compressed data CD at a higher speed than that of the prior art, so that the image compression time can be substantially reduced. In addition, the conventional Huffman encoding unit 25 can be used, and no special hardware is newly added for speeding up the compression. An apparatus can be provided.

FIG. 5 shows the DCT and quantization unit 2 shown in FIG.
1 is a block diagram showing a configuration of FIG. The DCT and quantization unit 21 has an image memory 1, a DCT unit 2, a DCT coefficient memory 3, and a quantization unit 4. The controller 8 exchanges a timing signal with the processing block described above,
Adjust the timing between processing blocks.

The image memory 1 is, for example, a DRAM or a flash memory, and stores one frame of image data. The image memory 1 stores image data in a normal raster format. The image data is composed of a plurality of pixel data.

The raster format is an arrangement of the following pixel data for one frame image. First, the images are arranged sequentially starting from the pixel at the upper left corner of the image toward the right horizontal direction. After reaching the rightmost pixel, subsequently, starting from the leftmost pixel of the next line, the pixels are sequentially arranged in the right horizontal direction. Hereinafter, the process is similarly performed up to the bottom line. The pixel at the lower right corner is the last data.

Since the image compression apparatus basically performs processing for each block of 8 × 8 pixels, the image memory 1 converts the image data from a raster format to a block format, and the DCT unit 2 Supply data I. A monochrome image has one type of image data. A color image is divided into luminance data and color data, and each is subjected to raster / block conversion as separate image data.

The block format is an arrangement of the following pixel data for one frame image. As shown in FIG. 6, an image of one frame is divided into a plurality of blocks. One block is 8 × 8 pixels. The order of blocks in one frame is the same as in the above raster format.
Starting from the block in the upper left corner, line up horizontally to the right. The last block is the block in the lower right corner. The arrangement of the pixel data in the block is also the same as the raster format,
Starting from the pixel data at the upper left corner in the block, they are arranged in the right horizontal direction. The last pixel data is the pixel data at the lower right corner in the block.

The DCT unit 2 performs a DCT process on the image data I in block units. In the DCT processing, the image data I is interposed between a transposed cosine coefficient matrix ^Dt and a cosine coefficient matrix D, and a matrix operation is performed to obtain a DCT coefficient F.

F = D ^t ID Here, the DCT coefficient F is an 8 × 8 matrix and indicates a spatial frequency component.

The DCT coefficient memory 3 is, for example, a DRAM or an SRAM, and has a DCT coefficient F generated by the DCT unit 2.
Is stored.

Next, the configuration of the quantization unit 4 will be described. The memory 11 stores a reference quantization table Q.

FIG. 7 shows an example of the reference quantization table Q. The image compression apparatus compresses data in units of 8 × 8 blocks.
It is composed of a × 8 matrix.

The reference quantization table Q is a quantization table for compressing data at a standard compression degree. The quantization process divides the 8 × 8 DCT coefficient F by the corresponding coefficient in the quantization table Q. The DCT coefficients have lower spatial frequency components in the upper left direction of the matrix and higher spatial frequency components in the lower right direction. The reference quantization table Q indicates that the lower the frequency component as a whole, the finer the quantization, and the higher the frequency component, the coarser the quantization. Generally, data compression is performed by removing information on high-frequency components of image data in consideration of human visual characteristics and high-frequency components having a lot of noise.

In FIG. 5, the multiplier 12 multiplies the reference quantization table Q by a scale factor SF. That is,
All elements of the matrix of the reference quantization table Q are multiplied by the scale factor SF. The multiplier 12 calculates the quantization table S
F × Q is output to the divider 15.

The divider 15 converts the DCT coefficient Fuv stored in the DCT coefficient memory 3 into a quantization table SF ×
It divides by Quv and outputs the following quantized data CF1uv. Elements in the matrix are specified by u rows and v columns. Rounding round means rounding to the nearest integer.

CF1uv = round [Fuv / (SF
× Quv)] As shown in FIG. 8, the quantized data CF1uv is output in the order of zigzag scan from low-frequency components to high-frequency components. In the quantized data CF1uv, many 0s tend to be collected in the lower right part (high-frequency component) of the matrix.

As described with reference to FIG. 1, the image compression apparatus thereafter performs run-length coding and Huffman coding on the quantized data CF1. The run-length coding can perform high compression on data in which 0s continuously follow.

As shown in FIG. 9, in the conventional image compression apparatus, the DCT coefficient CF1 is stored in the buffer 32 as it is. On the other hand, as shown in FIG. 1, in the image compression apparatus according to the present embodiment, the data WD including the zero flag ZF is stored in the buffer 22. The data WD includes the DCT coefficient CF1 or the run length R in addition to the zero flag ZF.
L1.

The zero flag ZF indicates whether or not the DCT coefficient CF1 is 0. According to the zero flag ZF,
By supplying the set of the run length RL2 and the DCT coefficient CF2 to the Huffman encoding unit 25, the Huffman encoding unit 25 can output the compressed data CD at high speed. The image compression device according to the present embodiment can perform image compression at a high speed and reduce the compression time.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0071]

As described above, according to the present invention,
In the buffer, a set of the zero flag and the quantized data or a set of the zero flag and the run length is written, so by referring to the zero flag in the buffer,
Various processes can be performed on the information in the buffer.

When Huffman coding is performed, a set of run length and quantized data is supplied to the Huffman coding means in accordance with the zero flag stored in the buffer. Can perform encoding processing efficiently and at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image compression device according to an embodiment of the present invention.

FIGS. 2A and 2B are diagrams showing contents of data stored in a buffer; FIGS.

FIG. 3 is a timing chart showing a write operation to a buffer shown in FIG. 1;

FIG. 4 is a timing chart showing an operation of reading data from a buffer shown in FIG. 1;

FIG. 5 is a block diagram illustrating a configuration of a discrete cosine transform (DCT) and a quantization unit.

FIG. 6 is a schematic diagram illustrating a process of blocking image data.

FIG. 7 is a diagram illustrating a matrix of a quantization table.

FIG. 8 is a diagram showing a scanning order of zigzag scanning.

FIG. 9 is a diagram showing a configuration of an image compression device according to a conventional technique.

FIG. 10 is a timing chart showing a write operation to the buffer shown in FIG. 9;

FIG. 11 is a timing chart showing an operation of reading data from the buffer shown in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image memory 2 Discrete cosine transform (DCT) part 3 DCT coefficient memory 4 Quantization part 8 Controller 11 Quantization table memory 12 Multiplier 15 Divider 21 Discrete cosine transform (DCT) and quantization part 22 Buffer 23 Run length counter 24 Buffer controller 25 Huffman coding unit 31 DCT and quantization unit 32 Buffer 33 Run-length counter 35 Huffman coding 36 Judgment unit ZF Zero flag CF1, CF2 DCT coefficient RL1, RL2 Run-length WA, RA address WD, RD data CD Compressed data CLK clock

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 MA23 MC11 ME02 ME05 PP04 RC11 TA57 TB08 TC45 UA02 UA34 UA38 5C078 BA23 BA57 CA31 DA01 DA05 5J064 AA03 BA08 BA09 BA16 BB05 BC01 BC02 BC16 BD01

Claims (3)

[Claims] 1. DCT for performing discrete cosine transform of image data
Means, quantizing means for quantizing the data transformed by the DCT means, an input terminal for sequentially inputting the quantized data quantized by the quantizing means, and quantized data inputted to the input terminal A buffer which can determine whether or not the quantized data input to the input terminal is 0, and sets a zero flag when the quantized data is 0; A run-length counter that counts the run length of 0 to be performed; and when the quantized data input to the input terminal is 0, the zero flag and the quantized data are associated with each other and written to the buffer, and the input terminal When the quantized data input to the buffer is not 0, the writing is performed by associating the zero flag with the run length in the buffer. Image compression apparatus of the JPEG scheme and means. 2. The method according to claim 1, further comprising the step of sequentially reading a zero flag from the buffer, setting the run length to 0 when the read zero flag is not set, outputting a set of quantized data corresponding to the zero flag and the run length,
When the zero flag read from the buffer is set, output means for outputting a set of the run length stored corresponding to the zero flag and the quantized data stored next, and output by the output means 2. A JPEG image compression apparatus according to claim 1, further comprising Huffman coding means for performing Huffman coding on a set of the run length and the quantized data to be performed. 3. The JP according to claim 2, wherein a processing cycle of said Huffman encoding means is longer than a processing cycle of said quantization means.
EG type image compression device.