JP2000049762A - Reference phase detection method and device, and recording medium there - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately detect an F-bit to be the reference phase of reception data. SOLUTION: This method is provided with a gate signal preparation part 17 for specifying the change phase of an F-bit by opening a gate by violation detection signals detected from a positive side reception signals and closing the gate by pulse detection signals detected from negative side reception signals, an F-bit change point detection part 18 for detecting the F-bit change points of the positive side reception signals and an AND circuit 20 for selecting and outputting the F-bit change point inside the section of opening the gate among the F-bit change points as the reference phase. By the method, gate signals to be at a first level by the detection of a violation on one side of reception signals and be at a second level by the detection of pulses on the other side of the reception signals are used. Then, among the F-bit change points detected in a frame, the F-bit change point detected when the gate signals are at the first level is selected as the F-bit as the reference phase. Thus, the F-bit to be the reference phase is detected accurately for each frame.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a reference phase of a reception signal in a reception timing generation circuit for realizing a connection defined in ITU-T I.430. The present invention relates to a reference phase detecting device and a recording medium on which a program for detecting a reference phase is recorded.

[0002]

2. Description of the Related Art ITU-T I.430 is a standard of ITU.
-Defines ISDN basic user / network interface layer specifications based on the T Recommendation. According to this recommendation, three types of connections, short-distance passive bus connection, long-distance passive bus connection, and one-to-one connection, are used as connections of interfaces supported by a digital service unit (DSU), that is, a network termination unit (NT). The configuration is specified.

In each connection, a delay range between a transmission frame and a reception frame in NT is defined as follows, including a 2-bit offset delay. That is, the delay range of the short-distance passive bus connection is 10 μs to 14 μs, and the delay range of the long-distance passive bus connection is 10 μs to 42 μs.
The delay range of the one-to-one connection is defined as 10 μs to 42 μs.

[0004] A reception timing generation circuit is used to synchronize received signals whose phases are shifted by a delay between frames. The reception timing generation circuit detects and uses the reference phase of the reception signal.

Conventionally, as a method of detecting the reference phase,
When the received signal is from the violation of the + side signal, the rule that there is a violation of the − side signal within 13 bits from the violation (1)
3 bit rule).

[0006]

However, when the 13-bit rule is used as in the prior art, an erroneous reference phase is detected due to noise or the like, and signals subsequent to the next frame violate the 13-bit rule. In this case, the same operation as the abnormal frame reception occurs. As a result, the operation starts while maintaining the previous frame phase. That is, a phenomenon occurs in which the user cannot escape from the wrong phase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide a technique for accurately detecting an F bit serving as a reference phase of received data.

[0008]

(Reference phase detecting method) According to the reference phase detecting method of the present invention, the TTC standard JT-
In order to realize the connection specified in I430, in detecting the F bit as the reference phase of the received signal, by sampling the received signal on one of the + side and the − side received signal by a clock signal. Detecting the pulse of the received signal on one side, setting the level of the gate signal to the first level when a violation is detected from the received signal on the other side, and setting the level of the gate signal when a pulse is detected. Is set to the second level, an F-bit (frame bit) change point is detected from the received signal on the other side,
Among the bit change points, an F bit change point when the level of the gate signal is the first level is selected as a reference phase.

As described above, in the present invention, the F bit change point is detected as a reference phase from among the F bit change points included in one or more frames using the gate signal.
The level of this gate signal becomes the first level when a violation is detected. This state is called a state in which the gate is open. Then, at the F bit serving as the reference phase, a violation always occurs for each frame. Therefore, the F-bit change point serving as the reference phase is detected when the gate is open.

The level of the gate signal becomes the second level when the pulse signal of the received signal on the side opposite to the side where the violation is detected is detected. This state is called a state in which the gate is closed. For example, when a violation is detected as a positive pulse, the gate is closed by detecting a negative pulse. Therefore, it is possible to exclude the F-bit change point other than the reference phase from the section of the first level of the gate signal. As a result, it is possible to accurately detect the F bit serving as the reference phase for each frame.

(Reference Phase Detector) According to the reference phase detector of the present invention, an F bit as a reference phase of a received signal is detected in order to realize the connection specified in ITU-T I.430. A reference phase detection device, wherein a pulse detection unit that detects a pulse of the reception signal on one side by sampling a reception signal on one side of the reception signals on the + side and the − side with a sampling clock signal; A gate signal generation unit that sets the level of the gate signal to a first level when a violation is detected from the reception signal on the other side and sets the level of the gate signal to a second level when a pulse is detected. An F-bit change point detecting unit for detecting an F-bit change point from the reception signal on the other side; Certain of F bit change points as the configuration in which a selection output unit that selects as a reference phase.

As described above, according to the reference phase apparatus of the present invention, similarly to the above-described reference phase detection method, it is possible to accurately detect the F bit serving as the reference phase for each frame.

(Recording Medium) According to the recording medium of the present invention, in order to realize the connection specified in ITU-T I.430, when detecting the F bit as the reference phase of the received signal, By sampling the received signal on one side of the received signals on the-and-sides with a clock signal, a process of detecting a pulse of the received signal on one side and a violation from the received signal on the other side were detected. In this case, the level of the gate signal is set to the first level,
When a pulse is detected, the process of setting the level of the gate signal to the second level, the process of detecting the F bit change point from the received signal on the other side of the received signal, A program for causing a computer to execute a process of selecting the F-bit change point when the level of the gate signal is the first level as a reference phase is recorded.

By reading the program recorded on the recording medium of the present invention into a computer and executing the program, it is possible to accurately detect the F bit serving as the reference phase for each frame.

In practicing the present invention, it is preferable to detect the B1, B2, D and FA channel pulses in the received signal on one side.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited only to the illustrated example.

First, with reference to FIG. 1, an example of a timing generating circuit having the reference phase detecting device of the present invention as a component will be described. FIG. 1 is a block diagram showing a configuration of the timing generation circuit.

As shown in FIG. 1, this timing circuit includes a pulse presence / absence detection section 1, a violation detection section 2,
It comprises an FL change point detecting unit 3 as a reference phase detecting device, a comparing unit 4, a frequency dividing circuit 5, and a mode selecting unit 6.

To the pulse presence / absence detection unit 1, a + side reception signal (data) and a − side reception signal (data) of the reception signal from the S / T point (reference point) are input. Then, the pulse presence / absence detection section 1 detects the pulses of the + side and − side reception signals, respectively. Further, the pulse presence / absence detecting section 1 outputs pulse detection results of the + side and − side reception signals.

The pulse detection result is input to the violation detection unit 2. Then, this violation detection 2 is performed by using a violation (AMI (alternate
markinversion). Further, the violation detection section 2 outputs a violation detection signal 11.

Further, the FL change point detecting section 3 includes a + side received data 14, a − side received data 12, a violation detection signal 11, and an LFL bit (DC balanced bit.
A 192 clock signal for sampling received data excluding frame bits and DC balanced bits) is input.
Then, the FL change point detecting unit 3 detects and outputs the F bit serving as the reference phase for each frame. In addition, FL
The detailed operation of the change point detecting section 3 will be described later.

Further, the comparison section 4 stores information on the reference phase,
A 4 kHz clock signal of the transmission signal is input. Then, the comparison unit 4 compares the reference phase and the transmission phase,
Output the comparison result.

The frequency dividing circuit 5 receives reference phase information. The frequency divider 5 sets the reference phase to 15.
The 36 MHz clock is reset at the reference phase. Then, this 15.36 MHz is divided by 80 to 192 kHz.
A clock signal of z is generated and output.

The mode selector 6 receives the comparison result from the comparator 4, the clock signal from the frequency divider, and the 192 kHz clock signal for transmission. And
The mode selector 6 selects one of the following mode and the fixed mode according to the comparison result. When the tracking mode is selected, a clock signal is output from the frequency dividing circuit. On the other hand, when the fixed mode is selected, a clock signal for transmission is output.

Next, an example of the configuration of the FL change point detecting section 3 as the reference phase detecting device of the present embodiment will be described with reference to FIG. FIG. 2 is a block diagram illustrating the configuration of the FL change point detection unit 3.

As shown in FIG. 3, the FL change point detector 3 includes a pulse detector 15, an F-bit specific gate signal generator 17, an F-bit change point detector 18, and an AND circuit 20 as a selection output unit. It is configured.

The pulse detector 15 receives the negative side received signal and the sampling clock signal. Then, the pulse detection unit 15 samples the minus side received signal with a sampling clock signal,
Detects the pulse of the side reception signal. Further, the pulse detection section 15 outputs a pulse detection signal.

The F-bit specific gate signal generator 17
Is supplied with a violation detection signal detected from the + side received signal and the pulse detection signal. Then, when a violation is detected, the gate signal creation unit 17 sets the level of the gate signal to a high level.
That is, the gate is opened. Then, when a pulse is detected, the level of the gate signal is set to a low level. That is, the gate is closed. In this way, a gate signal for selecting the changing phase of the F bit is created. And
The gate signal generator 17 outputs this gate signal.

Further, the F bit change point detecting section 18 has +
Side reception signal is input. Then, the F-bit change point detecting section 18 detects the F-bit change point (fall) of the + side received signal and outputs an F-bit change point detection signal.

A gate signal and an F-bit change point detection signal are input to the AND circuit 20. And A
The ND circuit 20 selects and outputs an F-bit change point detected when the gate signal is at a high level, that is, when the gate is open, among the F-bit change points. The selected F bit change point is the F bit 1 serving as the reference phase.
9 As described above, by using the gate signal, the F bit serving as the reference phase can be accurately detected for each frame.

Next, an example of the reference phase detecting method will be described with reference to the time chart of the received signal shown in FIG. Note that the processing of the reference phase detection method in this embodiment is executed by a computer controlled by a program. This program is provided, for example, by a recording medium. As the recording medium, for example, a magnetic disk, a semiconductor memory, or any other computer-readable medium can be used.

First, the operation in the case of a normal received signal will be described with reference to the time chart of FIG. In the case of a normal received signal, a violation is always detected at the position of the F bit. The portion of this violation is indicated by a mark “V” on the time chart of FIG.

The detection signal 11 of this violation is
It is input to the F-bit specific gate signal generator 17 shown in FIG. When the violation detection signal 11 is input,
The gate signal creation unit 17 opens (opens) a gate that specifies the F bit. The opening and closing of the gate is shown by a gate signal 21 in FIG. When the level of the gate signal 21 is high, the state is open, and when the level is low, the state is closed.

Further, in the pulse detection section 15 shown in FIG. 2, the negative side received signal 11 is sampled by a 192 kHz clock signal for sampling the received data excluding the LFL, so that the negative side received signals B1, B2, D and The presence or absence of the FA channel pulse is detected. As a result of detection,
When a pulse of a bit after B1-1 is detected, F
Close (close) the gate specifying the bit.

In parallel with this, the F-bit change point detecting section 18 shown in FIG. 2 detects a falling change of the + side received signal. Then, in the AND circuit 20,
From all the F bit change points of the + side received signal, only the F bit change point in the section where the gate is open is selected. The selected F bit change point becomes a reference phase of the reception timing generation circuit.

Next, an example in the case of an abnormal frame will be described with reference to the time chart of FIG. Here, the abnormal frame means that the multi-frame has collapsed,
This is a frame in which the data of the received signal is all “1”, that is, no pulse.

In this abnormal frame, a violation occurs at the F bit. For this reason, the gate is opened in the gate signal creation unit 17 that has received the abnormal frame. In this abnormal frame, the received signal data after B1-1 are all "1", so that the gate remains open until the next frame. Then, even if no violation occurs at the position of the F bit in the next frame, the F bit can be correctly detected.

At this time, there may be a case where even one bit has a bit of "0" in the negative signal after B1-1 in the frame, that is, a case where there is a pulse. In this case, a pulse always occurs in the + side received signal according to the AMI coding rule, and a violation occurs in the F bit of the next frame. Therefore, the operation is the same as that of a normal frame.

Here, FIG. 3C shows a time chart in a case where all the received signal data after B1-1 are "1" as a most extreme example (worst case) in a normal frame. Show. Also in this case, the F bit can be correctly detected.

FIG. 3D shows a time chart when a bit break occurs in the L bit. Bit breakage of the L bit with respect to the F bit means that different types of terminals are S / S
It may occur when connecting to point T. Even in such a case, since the present invention does not use the L bit for detecting the reference phase, the F bit can be correctly detected.

When a violation is detected only with L bits, a violation is detected with the L bit broken. As a result, the gate opened by the F bit is immediately closed. This is shown by the gate signal 23 in FIG. Then, in the next frame, the violation at the F bit cannot be detected. Therefore, the gate cannot be opened in the next frame. As a result, the F bit cannot be detected correctly.

In the above-described embodiment, an example in which the present invention is configured under specific conditions has been described. However, the present invention can be variously modified. For example, in the above-described embodiment, an example has been described in which the received signal on one side is a − side received signal and the received signal on the other side is a + side received signal. And may be interchanged. That is, in the above-described embodiment, the condition for closing the gate is changed to the following condition for the B1-1 channel and thereafter.
Although the example in which the pulse of the side reception signal is detected has been described, in the present invention, for example, the gate may be closed when the pulse of the + side reception signal is detected.

Further, the present invention is based on the AMI coding rule.
The present invention can be applied to various transmission apparatuses having an instantaneous tracking type frame synchronization or timing generation circuit based on bipolar violation.

[0044]

As described above in detail, according to the present invention, the level of the received signal becomes the first level by detecting the violation on one side, and the pulse is detected on the other side of the received signal by the detection of the pulse. A second level gate signal is used. Then, of the F bit transition points detected during the frame, the F bit detected when the gate signal is at the first level.
The bit change point is selected as the F bit as the reference phase. Therefore, according to the present invention, the reference phase F
Bits can be detected accurately for each frame.

Therefore, the previous phase is not held when an abnormal frame is detected. Therefore, even when abnormal frames are continuously input, the reference phase can be detected with a correct phase.

Further, when a malfunction occurs in a certain frame due to noise or the like, it is possible to self-recover as an error only in that frame. As a result, the influence of the malfunction can be prevented from affecting other frames.

Further, even in the case where the L bit is cracked with respect to the F bit, occurrence of a malfunction can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a reception timing generation circuit.

FIG. 2 is a block diagram illustrating a configuration example of an FL change point detection unit.

FIG. 3 is a time chart of a reception signal.

[Explanation of symbols]

 Reference Signs List 1 pulse presence / absence detection unit 2 violation detection unit 3 FL change point detection unit 4 comparison unit 5 frequency divider 6 mode selection unit 11 + violation detection signal 12 -side reception signal 13 192 kHz clock signal for sampling 14 + side reception signal 15 Pulse presence / absence detection unit 16 Pulse presence / absence detection result 17 F-bit specific gate signal creation unit 18 F-bit change point detection unit 19 F-bit serving as reference phase 20 AND circuit 21, 22, 23 Gate signal

Continuation of the front page (72) Inventor Katsuji Kanno 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within NEC Telecom System Co., Ltd. 5K047 AA04 BB17 CC01 DD01 HH02 HH36 KK02 KK05 MM53 MM55 MM63

Claims (6)

[Claims] 1. To realize a connection defined in ITU-T I.430, F.R.
In detecting a bit, a pulse of the received signal on one side is detected by sampling a received signal on one side of the received signals on the + side and the-side with a clock signal, and receiving a signal on the other side. , When the violation is detected, the level of the gate signal is set to the first level, and when the pulse is detected, the level of the gate signal is set to the second level.
A F-bit change point is detected from the reception signal on the other side, and among the F-bit change points, an F-bit change point when the level of the gate signal is the first level is selected as a reference phase. A method for detecting a reference phase, comprising: 2. The reference phase detecting method according to claim 1, wherein, in detecting the pulse, detecting pulses of B1, B2, D and FA channels in the received signal on the one side. Characteristic reference phase detection method. 3. In order to realize the connection specified in ITU-T I.430, F.R.
A reference phase detection device for detecting a bit, wherein a pulse of the received signal on one side is detected by sampling a received signal on one side of a received signal on a + side and a − side with a sampling clock signal. A pulse detection unit that performs the detection, and sets the level of the gate signal to the first level when a violation is detected from the reception signal on the other side, and sets the level of the gate signal to the second level when the pulse is detected.
A gate signal generating unit for setting a level; an F bit change point detecting unit for detecting an F bit change point from the reception signal on the other side; A selection output unit for selecting the F-bit change point at the time of (1) as a reference phase. 4. The reference phase detection device according to claim 3, wherein the pulse detection device detects pulses of B1, B2, D, and FA channels in the negative side reception signal. Reference phase detector. 5. In order to realize the connection specified in ITU-T I.430, F.R.
In detecting a bit, a process of detecting a pulse of a received signal on one side by sampling a received signal on one of the received signals on the + side and a − side with a clock signal, When the violation is detected from the signal, the level of the gate signal is set to the first level, and when the pulse is detected, the level of the gate signal is set to the second level.
A process of setting the level, a process of detecting an F-bit change point from the received signal on the other side of the received signal, and a process of detecting the level of the gate signal at the first level among the F-bit change points. A recording medium on which a program for causing a computer to execute a process of selecting a bit change point as a reference phase is recorded. 6. The recording medium according to claim 6, wherein, when detecting the pulse, the computer performs a process of detecting a B1, B2, D, and FA channel pulse of the received signal on the one side. A recording medium on which a program to be executed is recorded.