JP2000049309A - Semiconductor storage and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce consumption power by connecting a latch circuit in series with a PMOS transistor and an NMOS transistor and providing a second MOS transistor for turning on/off in linking with the on/off of a first MOS transistor. SOLUTION: A PMOS transistor 24X is connected between a PMOS transistor 211 and the wiring of a power supply potential VDD by a NOR gate 25. The gate of the PMOS transistor 24X is commonly connected to the gate of an NMOS transistor 24, and a word line reset signal WRST is supplied. A PMOS transistor 23X is connected between a PMOS transistor 221 and the wiring of the power supply potential VDD by a NOR gate 26. The gate of the PMOS transistor 23X is commonly supplied to the gate of an NMOS transistor 23 and the word line reset signal WRST is supplied, thus blocking a feedthrough current without increasing the occupancy area of a latch circuit 20A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device of the type in which the output of a word decode circuit is held by a latch circuit, and a test method therefor.

[0002]

2. Description of the Related Art Semiconductor memory devices are required to have low power consumption, especially for portable electronic devices. The synchronous DRAM has a plurality of banks, and switches at every system clock cycle to operate the plurality of banks in parallel, thereby enabling high-speed access. In order to enable the parallel operation, a latch circuit is connected to an output terminal of a word decode circuit to which a signal obtained by pre-decoding a row address is supplied, corresponding to each word line.

FIG. 8 shows a circuit for one row of a conventional word decoder. The word decode circuit 10 is a NAND gate in which NMOS transistors 11 and 12 are connected in series, and outputs the predecoded signals S1 and S2 respectively.
It is supplied to the gates of the MOS transistors 11 and 12. When the signals S1 and S2 are set high to select the word line WL, the signal S3 goes low. The signal S3 is held in the latch circuit 20, and a high-level signal S4 obtained by inverting the signal S3 is output from the latch circuit 20.

The latch circuit 20 comprises inverters 21 and 22
Are connected in a ring, a setting NMOS transistor 23 is connected between the output terminal of the inverter 22 and the ground line, and a reset NMOS transistor 24 is connected between the output terminal of the inverter 21 and the ground line. ing. The driving capability of the signal S4 is amplified by the driver 30, and the word line WL rises.

Since activation is performed in memory block units to reduce power consumption, at the end of access, a word line reset signal WRST is supplied commonly to all the latch circuits 20 in the activated memory block and the NMOS transistor 24 is turned on, the signal S4 transitions to low level, and the word line WL falls. Before shipment of the semiconductor memory device, the signal line of the multiple selection signal WMSEL is commonly connected to all the latch circuits 20 in the chip in order to raise all the word lines WL and perform a high-temperature acceleration test. When the multiple selection signal WMSEL is set to the high level, the NMOS transistor 23 is turned on, the output of the inverter 22 is changed to the low level, the output of the inverter 21 is changed to the high level, and the signal S4 rises.

FIG. 9 shows a configuration of the latch circuit 20 in FIG. In the inverter 21, a PMOS transistor 211 and an NMOS transistor 212 are connected in series between power supply lines of the potentials VDD and VSS, and both gates are connected in common. Similarly, in the inverter 22, a PMOS transistor 221 and an NMOS transistor 222 are connected in series, and both gates are connected in common.

When the signal S3 is at a low level, the PMOS transistor 211 is on and the NMOS transistor 212 is off. In this state, the word line reset signal W
When RST transitions to the high level, the NMOS transistor 24 is turned on, and the PMO
Through current flows through the S transistor 211 and the NMOS transistor 24 to the wiring of the power supply potential VSS. When the signal S4 transitions to a low level, the PMOS transistor 2
21 and the NMOS transistor 222 are turned on and off, respectively, so that the signal S3 goes high and the PMO
S transistor 211 is off, NMOS transistor 2
12 is turned on, and this through current is blocked. However, since a through current flows until this state is reached, wasteful power is consumed.

Similarly, when the signal S4 is at a low level, the PMOS transistor 221 is turned on, and the NMOS transistor 222 is turned on.
Is turned off, and the multiple selection signal WMSEL transitions to a high level in the high-temperature acceleration test described above, the power supply potential VD
A through current flows from D through the PMOS transistor 221 and the NMOS transistor 23, and the through current continues to flow until the signal S4 transitions to a high level and the PMOS transistor 221 turns off. In this case, since a through current flows simultaneously for all the latch circuits 20 in the chip, it cannot be ignored. Next, the multiple selection signal WMSEL is returned to a low level. From this state, the word line reset signal WR is applied to the latch circuits 20 of all the memory blocks.
When ST is made to transition to the high level, the PMOS transistors 211 and NMO
A through current flows through the S transistor 24 and cannot be ignored. For this reason, the high temperature acceleration test performed by setting the ambient temperature becomes inaccurate.

On the other hand, since the latch circuit 20 is provided for each word line, its occupied area is limited. FIG. 10 shows a layout pattern of a diffusion region and a polysilicon wiring layer of two adjacent latch circuits 20. FIG. 10 does not show the pattern of the metal wiring layer to avoid complication. FIG. 11 is a circuit diagram in which transistors are arranged corresponding to the layout pattern of FIG. 10 to facilitate understanding of the pattern of FIG.

In order to reduce the occupied area of the latch circuit 20 and to reduce the width, the PMOS transistor group 20P and the NMO
The transistors are arranged separately from the S transistor group 20N, and further, the PMOS transistor group 20P and the NMOS transistor group 20N are arranged in a band along the word line direction. In FIG. 10, 221P and 211P are P-type diffusion regions of PMOS transistors 221 and 211, respectively, and 212N, 222N, 24N and 23P.
N is an NMOS transistor 212, 222, 2
4 and 23 are N-type diffusion regions. The hatched area is a polysilicon wiring, the small rectangle is an interlayer contact, and the dotted wiring near the boundary between the transistor groups 20P and 20N is for the transistor group 20P side to apply the power supply potential VDD to the N well. The transistor group 20N side is for applying the power supply potential VSS to the P well.

[0011]

When the latch circuit is provided with a through current blocking measure, the circuit becomes complicated, and when the circuit width in the direction perpendicular to the word line is increased, the word line pitch increases and the density of the memory cells increases. Decreases, thereby reducing the storage capacity or further increasing the word line direction.
This causes an increase in chip area.

SUMMARY OF THE INVENTION In view of the foregoing problems, it is an object of the present invention to prevent a through current of a latch circuit connected to a word decoder and reduce power consumption without increasing an occupied area. It is to provide a semiconductor memory device. Another object of the present invention is to provide a method of testing a semiconductor memory device that can perform a high-temperature acceleration test more accurately by blocking this through current.

[0013]

According to the present invention, an output of a word decode circuit is supplied to a data input terminal of a latch circuit, and the latch circuit includes a PMOS transistor connected in series between power supply lines. In a semiconductor memory device having a logic gate circuit including an NMOS transistor and a reset or set first MOS transistor connected in parallel to one of the PMOS transistor and the NMOS transistor, the latch circuit includes
A second MOS transistor is connected in series to the other of the MOS transistor and the NMOS transistor, and is turned off / on in conjunction with on / off of the first MOS transistor.

According to this semiconductor memory device, the first MOS
When the transistor is turned on, the second MOS transistor is turned off, so that a through current flowing through the one MOS transistor and the first MOS transistor is blocked by the second MOS transistor, thereby reducing power consumption. The element added to the logic gate circuit is a second element.
Since only MOS transistors are used, an increase in the area occupied by the latch circuit on the chip can be avoided or reduced.

In the semiconductor memory device according to the second aspect, the first aspect
Wherein the first MOS transistor is the NMOS
An NMOS transistor connected in parallel to the transistor, the second MOS transistor is a PMOS transistor connected in series with the PMOS transistor, a gate is connected between the first MOS transistor and the second MOS transistor, and a set signal is connected to the gate. Alternatively, a reset signal is supplied.

According to a third aspect of the present invention, there is provided the semiconductor memory device.
, The logic gate circuit is a two-input NOR gate circuit, and the latch circuit has first and second two-input NOR gate circuits, and an output terminal of the first two-input NOR gate circuit is the second two-input NOR gate circuit. The output terminal of the second two-input NOR gate circuit is connected to one input terminal of the input NOR gate circuit, and the output terminal of the second NOR gate circuit is connected to one input terminal of the first two-input NOR gate circuit. A set signal and a reset signal are supplied to one and the other of the other input terminals of the NOR gate circuit, respectively.

According to the semiconductor memory device of the fourth aspect, in the third aspect,
And a multi-select line for commonly supplying the set signal to the latch circuits connected to all the word decode circuits on the chip. According to this semiconductor memory device, all the latch circuits are set at the same time.
Since the shoot-through current is blocked for all the latch circuits,
High-temperature acceleration tests performed with the ambient temperature set are more accurate than before.

According to a fifth aspect of the present invention, there is provided a semiconductor memory device.
And a reset signal line for commonly supplying the reset signal to the latch circuits connected to the word decode circuits of the memory blocks sandwiched between adjacent sense amplifier rows. According to a sixth aspect of the present invention, in the semiconductor memory device according to any one of the third to fifth aspects, the latch circuit includes a PMOS transistor array of two rows and two columns and a two-row PMOS transistor array.
An NMOS transistor array in row 2 and column 2 are arranged along the word line direction.

According to this semiconductor memory device, an increase in the occupied area can be avoided. According to a seventh aspect of the present invention, in the semiconductor memory device according to the first aspect, the first MOS transistor is a P-type MOS transistor.
A PMOS transistor connected in parallel with the MOS transistor, and the second MOS transistor is connected to the NMO
An NMOS transistor connected in series with the S transistor, the gate of the first MOS transistor and the gate of the second MOS transistor are connected, and a set signal or a reset signal is supplied to the gate.

According to the semiconductor memory device of the present invention, there is provided a semiconductor memory device.
, The logic gate circuit is a two-input NAND gate circuit, and the latch circuit has first and second two-input NAND gate circuits, and the output terminal of the first two-input NAND gate circuit is the second two-input NAND gate circuit. An output terminal of the second two-input NAND gate circuit is connected to one input terminal of the input NAND gate circuit, and an output terminal of the second NAND gate circuit is connected to one input terminal of the first two-input NAND gate circuit. A set signal and a reset signal are supplied to one and the other of the other input terminals of the NAND gate circuit, respectively.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the ninth aspect,
And a multi-select line for commonly supplying the set signal to the latch circuits connected to all the word decode circuits on the chip. According to a tenth aspect of the present invention, in the ninth aspect, the reset for commonly supplying the reset signal to the latch circuit connected to the word decode circuit of the memory block sandwiched between the adjacent sense amplifier rows. It has a signal line.

[0022] In the semiconductor memory device according to the eleventh aspect, the latch circuit according to any one of the eighth to tenth aspects,
Row 2 column PMOS transistor array and 2 row 2 column NM
The OS transistor array is arranged along the word line direction. According to a twelfth aspect of the present invention, a semiconductor memory device according to the third or eighth aspect is prepared, and a high-temperature acceleration test is performed with the set signal line being activated.

According to this method, the through current of all the latch circuits set at the same time is prevented, so that the high-temperature acceleration test of the semiconductor memory device can be performed more accurately.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 schematically shows a synchronous DRAM according to a first embodiment of the present invention. The hatched portions are the sense amplifier rows.

In this synchronous DRAM, bank 0
Column decoder 40 and sense buffer circuit 41 are arranged so as to sandwich. Bank 0 includes sense amplifier arrays 42 to 44, memory block 0 between sense amplifier arrays 42 and 43, and memory block 1 between sense amplifier arrays 43 and 44. A word decoder is provided for each memory block. For example, the word decoder 45 corresponds to the memory block 0. Memory block 1 is memory block 0 except for the address range
The same applies to the banks 1 to 3 except for the address range.

An external address ADDR is supplied to address buffer registers 47 and 48 via a buffer gate 46 for a signal level interface. An external chip select signal * CS (* indicates active when it is at a low level, the same applies hereinafter), a row address strobe signal * RAS, a column address strobe signal * CAS, a write enable signal * WE, The clock enable signal CKE and the clock CLK are supplied to the control circuit 50 via the buffer gate 49.
The control circuit 50 controls the control signals * CS, * RAS, * CA
Various control signals are generated according to a command determined by a value of a set of S, * WE, CKE and a part of an address.

The control circuit 50 supplies the latch signal to the address buffer register 47 in response to the activation command ACT issuance, thereby causing the address buffer register 47 to hold the bank address, the block address in the bank, and the row address in the block. The output of the address buffer register 47 is pre-decoded by the pre-decoder 51 and further decoded by the word decoder including the word decoder 45, and the word line WL in the selected bank and block is activated.

When the word line WL rises, the stored contents of the row along the word line WL are read onto the bit line BL and amplified by the sense amplifier columns 42 and 43.
More specifically, for example, the storage content of the memory cell MC is read onto the bit line BL and amplified by the sense amplifier 52 in the sense amplifier array 43. The control circuit 50 supplies the latch signal to the address buffer register 48 in response to the issuance of the read command READ, thereby causing the address buffer register 48 to hold the column address.
The output of the address buffer register 48 is decoded by the column decoder 40, and the column gate is turned on by the selected column selection line CL. Thereby, for example, data on the bit line BL is read to the local data bus LDB along the sense amplifier row, and further amplified by the sense buffer circuit 41 through the global data bus GDB in a direction perpendicular to the local data bus LDB. . The output of the sense buffer circuit 41 is a signal level interface I / O.
The data is taken out as DATA via the O buffer gate circuit 53.

The multiple selection signal WMSEL is commonly supplied from the control circuit 18 to eight blocks of word decoders (WD), and the word line reset signals WRST1 to WRST7 are supplied. The multiple selection signal WMSEL is activated only during the high-temperature acceleration test, and is inactive during normal use. FIG. 2 shows a circuit for one row of the word decoder 45.

In the latch circuit 20A, the output terminal of the NOR gate 25 is connected to one input terminal of the NOR gate 26, the output terminal of the NOR gate 26 is connected to one input terminal of the NOR gate 25, and the other inputs of the NOR gates 25 and 26 are connected. The ends are supplied with a word line reset signal WRST0 and a multiple selection signal WMSEL, respectively. Other configurations are the same as those in FIG.

FIG. 3 shows a configuration example of the latch circuit 20A in FIG. In the NOR gate 25, the PMOS transistor 24X is connected between the PMOS transistor 211 and the wiring of the power supply potential VDD. The gate of the PMOS transistor 24X is commonly connected to the gate of the NMOS transistor 24, and both gates are connected to the word line reset signal WR.
ST is supplied. Similarly, in the NOR gate 26, the PM
The PMOS transistor 23X is connected between the OS transistor 221 and the wiring of the power supply potential VDD. PM
The gate of the OS transistor 23X is commonly connected to the gate of the NMOS transistor 23, and the word line reset signal WRST is supplied to both gates.

The other structure is the same as that of FIG. Next, the operation of the first embodiment configured as described above will be described.
In FIG. 2, the multiple selection signal WMSEL and the word line reset signal WRST0 are at a low level when inactive, and at this time, the NOR gates 25 and 26 both function as inverters.

Word line W of block 0 of bank 0 in FIG.
To select L, the predecoded signal S of FIG.
When 1 and S2 are brought high, signal S3 goes low and signal S4 goes high. At this time, in FIG. 3, the PMOS transistors 24X, 211 and 23X and the NMOS transistor 222 are turned on, and the NMOS transistors 212 and 24, the PMOS transistors 221 and N
MOS transistor 23 is off. Signal S4
The driver 30 has its driving capability amplified and the word line WL rises. Since the state of the latch circuit 20A is held, the address of another bank can be held in the buffer register 47 in synchronization with the rising edge of the next clock CLK, and parallel access can be made in a plurality of banks.

Since only block 0 is activated to reduce power consumption, at the end of access, word line reset signal WRST0 commonly supplied to all the latch circuits in block 0 goes high, and The NMOS transistor 24 turns on, the signal S4 transitions to a low level, and the word line WL falls. Since the PMOS transistor 24X is turned off simultaneously with the turning on of the NMOS transistor 24, a through current is prevented from flowing from the power supply potential VDD wiring to the power supply potential VSS wiring through the PMOS transistor 211 and the NMOS transistor 24. As a result, power consumption during normal use is reduced. The NMOS transistor 222 turns off and the PMOS transistor 221 turns on, and the signal S3 goes high. As a result, the PMOS transistor 211 turns off and the NMOS transistor 212 turns on. Next, the word line reset signal WRST0 is returned to a low level.

Prior to shipment of the semiconductor memory device, the signal line of the multiple selection signal WMSEL is commonly connected to all the latch circuits in the chip in order to raise all the word lines and perform a high-temperature acceleration test. Multiple selection signal WM
When SEL goes high, the NMOS transistor 23
Is turned on, and the signal S3 transitions to a low level. At the same time, the PMOS transistor 23X is turned off.
From the wiring of the power supply potential VDD to the PMOS transistor 211
And the power supply potential VSS through the NMOS transistor 23
Is prevented from flowing through the wiring. PMOS transistor 211 is on, NMOS transistor 212
Goes off, the signal S4 goes high, the word line WL rises on the one hand, the PMOS transistor 221 turns off and the NMOS transistor 222 turns on on the other hand. Next, the multiple selection signal WMSEL is returned to a low level.

From this state, the word line reset signal WR
ST0 to WRST7 transition to the high level, and all the word lines WL fall. At this time, through current is blocked by the operation at the time of resetting. Such an operation is performed simultaneously for all the word decoders. However, since the through current is blocked, the high-temperature acceleration test performed with the ambient temperature set becomes more accurate than before.

FIG. 4 shows two adjacent latch circuits 20A.
2 shows a layout pattern of a diffusion region and a polysilicon wiring layer. FIG. 4 does not show the pattern of the metal wiring layer to avoid complication. FIG. 5 is a circuit diagram in which transistors are arranged corresponding to the layout pattern of FIG. 4 to facilitate understanding of the pattern of FIG.

In order to reduce the area occupied by the latch circuit 20A, transistors are arranged separately in a PMOS transistor group 20AP and an NMOS transistor group 20AN. Further, the PMOS transistor group 20AP and the NMOS transistor group 20AN are arranged along the word line direction. And are arranged in a belt shape. PMOS transistor group 20AP
In both the NMOS transistor group 20AN and the NMOS transistor group 20AN, the transistors are arranged in two rows and two columns.

In FIG. 4, 221P, 23XP, 211P and 24XP are PMOS transistors 221 and 2P, respectively.
3X, 211 and 24X P-type diffusion regions, 212
N, 222N, 23N and 24N are N-type diffusion regions of the NMOS transistors 212, 222, 23 and 24, respectively. The hatched area is a polysilicon wiring,
The small rectangles are the interlayer contacts, and the transistor group 2
Wiring with dots near the boundary between 0AP and 20AN
The transistor group 20AP side is connected to the N well by the power supply potential VDD.
And a transistor group 20AN.
The side is for applying the power supply potential VSS to the P well.

When FIG. 4 is compared with FIG. 10, it can be seen that the occupied areas are the same. According to the semiconductor memory device of the first embodiment, the through current of the latch circuit 20A can be prevented without increasing the occupied area. [Second Embodiment] FIG. 6 shows a circuit for one row of a word decoder according to a second embodiment of the present invention.

In the latch circuit 20B, NAND gates 27 and 28 are used instead of the NOR gates 25 and 26 in FIG. Word line reset signal WRST
* WR which is a complementary signal of 0 and the multiple selection signal WMSEL.
ST0 and * WMSEL are supplied to one input terminals of NAND gates 27 and 28, respectively, contrary to the case of FIG. The multiple selection signal * WMSEL and the word line reset signal * WRST0 are at a high level when inactive, and at this time, the NAND gates 27 and 28 both function as inverters.

The other structure is the same as that of FIG. FIG.
7 shows a configuration example of a latch circuit 20B in FIG. In the NAND gate 27, the PM gate is connected in parallel with the PMOS transistor 211.
The OS transistor 24A is connected, the NMOS transistor 24AX is connected between the NMOS transistor 212 and the wiring of the power supply potential VSS, the gate of the PMOS transistor 24A is commonly connected to the gate of the NMOS transistor 24AX, and both gates have a multiple selection signal. * WMS
EL is supplied. Similarly, at the NAND gate 28, the PM
The PMOS transistor 23A is connected in parallel with the OS transistor 221, and the NMOS transistor 23A is connected between the NMOS transistor 222 and the wiring of the power supply potential VSS.
X is connected, the gate of the PMOS transistor 23A is commonly connected to the gate of the NMOS transistor 23AX, and * WRST is supplied to both gates.

The other structure is the same as that of FIG. Next, the operation of the second embodiment configured as described above will be described.
At the end of the access, the word line reset signal * WRST0
Is set to the low level, the PMOS transistor 23A is turned on, and the signal S3 transitions to the high level. At the same time, the NMOS transistor 23AX is turned off, so that the power supply potential VSS is supplied from the power supply potential VDD wiring through the PMOS transistor 23A and the NMOS transistor 222.
Is prevented from flowing through the wiring. As a result, power consumption during normal use is reduced. The signal S4 transitions to a low level, and the word line WL falls. Next, the word line reset signal * WRST0 is returned to a high level.

When the multiple selection signal * WMSEL is set to a low level in order to perform a high-temperature acceleration test, the PMOS transistor 24A is turned on, and the signal S4 changes to a high level.
The word line WL rises. Since the NMOS transistor 24AX is turned off simultaneously with the turning on of the PMOS transistor 24A, a through current is prevented from flowing from the power supply potential VDD wiring through the NAND gate 27 and the NMOS transistor 212 to the power supply potential VSS wiring. The signal S3 goes low, and then the multi-select signal * WMSE
L is returned to a high level.

From this state, the word line reset signal * W
RST0 transitions to a low level, and the word line WL falls. At this time, through current is blocked by the operation at the time of resetting. Such an operation is performed simultaneously for all the word decoders. However, since the through current is blocked, the high-temperature acceleration test performed with the ambient temperature set becomes more accurate than before.

The present invention also includes various modifications. For example, in FIG. 3, the output signal line of the NOR gate 25 to the NOR gate 26 and the multiple selection signal WMSEL
The connection destinations with the signal lines may be interchanged. This applies to the latch circuit 20B shown in FIG.

[Brief description of the drawings]

FIG. 1 shows a synchronous DR according to a first embodiment of the present invention.
It is a schematic block diagram of AM.

FIG. 2 is a diagram showing a circuit for one row of the word decoder in FIG. 1;

FIG. 3 is a diagram illustrating a configuration example of a latch circuit in FIG. 2;

4 is a diagram showing a layout pattern of a diffusion region including two latch circuits of FIG. 2 and a polysilicon wiring layer.

FIG. 5 is a circuit diagram in which transistors are arranged corresponding to a layout pattern of one latch circuit in FIG. 4;

FIG. 6 is a diagram showing a circuit for one row of a word decoder according to a second embodiment of the present invention.

7 is a diagram illustrating a configuration example of a latch circuit in FIG. 6;

FIG. 8 is a diagram showing a circuit for one row of a conventional word decoder.

FIG. 9 is a diagram showing a configuration of a latch circuit in FIG. 8;

10 is a diagram showing a layout pattern of a diffusion region including two latch circuits of FIG. 9 and a polysilicon wiring layer.

11 is a circuit diagram in which transistors are arranged corresponding to a layout pattern for one latch circuit in FIG. 10;

[Explanation of symbols]

10 Word decode circuit 11, 12, 212, 222, 23, 24, 23AX,
24AX NMOS transistor 20, 20A, 20B Latch circuit 20P, 20AP PMOS transistor group 20N, 20AN NMOS transistor group 21, 22 Inverter 211, 221, 23A, 23X, 24A, 24X P
MOS transistors 25, 26 NOR gate 27, 28 NAND gate 30 Driver 45 Word decoder WL Word line WMSEL, * WMSEL Multiple selection signal WRST, WRST0-WRSY6, * WRST0 Word line reset signal

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masato Takita 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Masatomo Hasegawa 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 F-term in Fujitsu Limited (reference) 5B024 AA01 AA15 BA13 CA07 EA01 5F083 GA05 LA01 LA05 LA11 ZA20 5L106 AA01 DD35 EE02 FF01 GG00

Claims (12)

[Claims] An output of a word decode circuit is supplied to a data input terminal of a latch circuit. The latch circuit includes a PMOS transistor and an NMOS transistor connected in series between power supply wirings, and a PMOS transistor and an NMOS transistor connected in series. In a semiconductor memory device having a logic gate circuit including a reset or set first MOS transistor connected in parallel to one side, the latch circuit includes the PMOS transistor and the NMOS
A second transistor which is connected in series with the other of the transistors and which is turned off / on in conjunction with on / off of the first MOS transistor;
A semiconductor memory device having a MOS transistor. 2. The method according to claim 1, wherein the first MOS transistor is connected to the NM.
An NMOS transistor connected in parallel to the OS transistor, wherein the second MOS transistor is the PMOS transistor
2. A PMOS transistor connected in series with a transistor, wherein a gate between the first MOS transistor and the second MOS transistor is connected, and a set signal or a reset signal is supplied to the gate.
13. The semiconductor memory device according to claim 1. 3. The logic gate circuit is a two-input NOR gate circuit, and the latch circuit has first and second two-input NOR gate circuits, and the output terminal of the first two-input NOR gate circuit is connected to the second input NOR gate circuit. The second two-input NOR gate circuit is connected to one input terminal of the second two-input NOR gate circuit, and the output terminal of the second two-input NOR gate circuit is connected to one input terminal of the first two-input NOR gate circuit. 3. The semiconductor memory device according to claim 2, wherein a set signal and a reset signal are supplied to one and the other of the other input terminals of said two-input NOR gate circuit, respectively. 4. The semiconductor memory according to claim 3, further comprising a multiple selection line for commonly supplying said set signal to said latch circuits connected to all said word decode circuits on a chip. apparatus. 5. A reset signal line for commonly supplying said reset signal to said latch circuit connected to a word decode circuit of a memory block sandwiched between adjacent sense amplifier rows. Item 5. The semiconductor memory device according to item 4. 6. The latch circuit according to claim 1, wherein said two-row, two-column PMOS
6. The semiconductor memory device according to claim 3, wherein the transistor array and the NMOS transistor array in two rows and two columns are arranged along a word line direction. 7. The first MOS transistor is connected to the PM transistor.
The second MOS transistor is a PMOS transistor connected in parallel to the OS transistor, and the second MOS transistor is the NMOS transistor.
2. An NMOS transistor connected in series with the transistor, wherein the gate of the first MOS transistor and the gate of the second MOS transistor are connected, and a set signal or a reset signal is supplied to the gate.
13. The semiconductor memory device according to claim 1. 8. The logic gate circuit is a two-input NAND gate circuit, and the latch circuit has first and second two-input NAND gate circuits, and the output terminal of the first two-input NAND gate circuit is connected to the second input NAND gate circuit. The two-input NAND gate circuit is connected to one input terminal of the second two-input NAND gate circuit, and the output terminal of the second two-input NAND gate circuit is connected to one input terminal of the first two-input NAND gate circuit. 8. The semiconductor memory device according to claim 7, wherein a set signal and a reset signal are supplied to one and the other of the other input terminals of said two-input NAND gate circuit. 9. The semiconductor memory according to claim 8, further comprising a multiple selection line for commonly supplying said set signal to said latch circuits connected to all said word decode circuits on a chip. apparatus. 10. A reset signal line for commonly supplying said reset signal to said latch circuit connected to said word decode circuit of a memory block sandwiched between adjacent sense amplifier rows. The semiconductor memory device according to claim 9. 11. The two-row, two-column PMO
11. The semiconductor memory device according to claim 8, wherein the S transistor array and the NMOS transistor array in two rows and two columns are arranged along the word line direction. 12. A method for testing a semiconductor memory device, comprising preparing the semiconductor memory device according to claim 3 or 8, and performing a high-temperature acceleration test with the set signal line being active.