JP2000049063A - Manufacture of soi wafer and the soi wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an SOI(silicon-on-insulator) with which the yield in a device process can be improved. SOLUTION: In this method of manufacturing an SOI wafer, a silicon single- crystal bar is grown at a growing rate of 0.6 mm/min or higher by the Czochralski method, so that it has highly dense COP with a concentration of contained oxygen of 16 ppma or lower, and it is processed as a bond wafer to a silcon wafer and the silcon wafer is heated in a reductive atmosphere and an SOI wafer is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a SOI wafer by producing a bond wafer for forming an SOI layer from a silicon single crystal by the Czochralski method, and an SOI wafer produced by this method.

[0002]

2. Description of the Related Art Conventionally, a wafer (hereinafter referred to as a CZ wafer) obtained from a silicon single crystal by the Czochralski method is used for a bond wafer for forming an SOI layer,
When manufacturing an OI (Silicon On Insulator) wafer, a COP (Crystal Originated P) existing in the CZ wafer is used.
article) is a problem.

[0003] COP is one of the crystal defects introduced during crystal growth, and is known to be a cavity-type defect having an octahedral structure. When the silicon wafer after mirror polishing is washed with a mixed solution of ammonia and hydrogen peroxide, COP forms pits on the surface of the wafer. When the wafer is measured with a particle counter, the pits are detected as particles together with the original particles. You. Such pits are called COPs to distinguish them from the original particles.

When an SOI wafer is manufactured using a CZ wafer in which this COP exists as a bond wafer, for example, a time-dependent dielectric characteristic (Time Dependent Diel) of an oxide film, which is an important electrical characteristic of a device, is obtained.
Electric Breakdown (TDDB) or normal oxide film breakdown voltage (Time Zero Director)
ic Breakdown (TZDB).

Further, the COP on the surface of the CZ wafer sometimes becomes a hole penetrating the thin SOI layer. For example,
In the etching process and the heat treatment process in the device process, the buried oxide film is etched by the etchant or the atmospheric gas penetrating from the hole, or a step is generated in the wiring process, which causes disconnection and causes a decrease in the yield in the device process. Met.

Therefore, as a method of manufacturing a semiconductor substrate,
A method of manufacturing an SOI wafer using an FZ wafer instead of a CZ wafer as a bond wafer has been considered. This FZ wafer has the advantage that there is no COP. However, at present, a technique for producing a wafer having a large diameter of 8 inches or more has not been established, and there is a disadvantage that it is not possible to cope with a recent increase in diameter of a semiconductor substrate.

Further, there is a method in which an epitaxial wafer in which a single crystal thin film layer is grown on a CZ wafer is used as a bond wafer of an SOI wafer. This epitaxial wafer also has the advantage that there is no COP in the epitaxial layer. However, at present, there is a disadvantage that the cost of manufacturing an epitaxial wafer is higher than the cost of manufacturing a normal bond wafer.

Therefore, as a method for manufacturing an SOI wafer using a CZ wafer, high-temperature annealing is performed to reduce CO2.
A method has been proposed in which a CZ wafer having a reduced P density is used as a bond wafer (see JP-A-10-84101). However, the typical condition of 1200
Even if hydrogen annealing is performed at 60 ° C. for 60 minutes, the COP on the wafer surface does not completely disappear but remains slightly, and the COP also remains relatively near the surface.

Further, another method of reducing COP other than hydrogen annealing has been considered as a method of reducing crystal defects by slowing the growth rate of silicon single crystal by the Czochralski method. According to this method, the number of COPs can be reduced, and furthermore, if the silicon wafer obtained by this method is subjected to hydrogen annealing, the COP in the silicon wafer used for SOI wafer production can be more effectively reduced. I thought it could be done. But,
In this method, the number of COPs can be reduced, but the size of the COPs increases. Therefore, even if the wafer obtained from the silicon single crystal rod is subjected to hydrogen annealing, it is impossible to completely eliminate the COPs. could not.

As described above, it is difficult to sufficiently eliminate COP even if hydrogen annealing is performed on the CZ wafer, and the size of the COP increases even if the pulling speed of the silicon single crystal by the Czochralski method is reduced. Therefore, the current situation is that it is hard to disappear even if hydrogen annealing is performed. For this reason, it has been difficult at present to improve the yield of device processes for SOI wafers using this CZ wafer.

[0011]

Accordingly, the present invention has been made in view of such problems, and an object of the present invention is to minimize crystal defects existing on the wafer surface and surface layer such as COP. It is an object of the present invention to provide a method for manufacturing an SOI wafer capable of improving the yield of a device process by using a CZ wafer produced by a technique for suppressing the temperature of the SOI wafer as a bond wafer.

[0012]

In order to achieve the above object, according to the first aspect of the present invention, a bond wafer for forming an SOI layer from a silicon single crystal by a Czochralski method is manufactured, and the bond wafer is formed. In a method for manufacturing an SOI wafer in which a wafer and a base wafer serving as a support substrate are bonded via an oxide film, and thereafter the bond wafer is thinned, a growth rate of a silicon single crystal by a Czochralski method is used as the bond wafer. 0.6 mm
/ Min or more and the content oxygen concentration is 16 pp
Growing a silicon single crystal rod having a COP of less than or equal to ma at a high density, slicing the silicon single crystal rod into a silicon wafer, and applying a heat treatment in a reducing atmosphere to the silicon wafer. SO characterized by
This is a method for manufacturing an I wafer.

As described above, in the method for manufacturing an SOI wafer using a CZ wafer as a bond wafer, the growth rate of a silicon single crystal by the Czochralski method is raised to 0.6 mm / min or more as the bond wafer, and the oxygen content is increased. By growing a silicon single crystal rod having a COP of 16 ppma or less at a high density, slicing the silicon single crystal rod and processing it into a silicon wafer, and applying a heat treatment in a reducing atmosphere to the silicon wafer, The SOI layer of the SOI wafer has a greatly reduced COP, and the buried oxide film is not etched by the etching or heat treatment in the SOI wafer manufacturing process or the device process, and the disconnection does not occur in the wiring process. Etc. can significantly improve the yield

[0014] Further, the invention described in claim 2 of the present invention relates to a method of converting SO from a silicon single crystal by the Czochralski method.
A bond wafer for forming an I layer is formed, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film.
In the method for producing an I-wafer, as the bond wafer, a silicon single crystal in which a COP having an oxygen concentration of 16 ppma or less exists at a high density by raising the growth rate of a silicon single crystal by the Czochralski method to 0.6 mm / min or more. A rod is grown, the silicon single crystal rod is sliced and processed into a silicon wafer, and the silicon wafer is subjected to a heat treatment at a temperature of 1200 ° C. or more for 1 second or more in a reducing atmosphere using a rapid heating / cooling apparatus. Is a method for manufacturing an SOI wafer, characterized by using a product obtained by adding the above.

As described above, in the method of manufacturing an SOI wafer using a CZ wafer as a bond wafer, a silicon wafer obtained by slicing a silicon single crystal rod having the same quality as the invention described in claim 1 is used as the bond wafer. By using a rapid heating / cooling device and applying a heat treatment at a temperature of 1200 ° C. or more for 1 second or more in a reducing atmosphere, the SOI wafer SO
The COP of the I layer is greatly reduced, and the buried oxide film is not etched by the etching or heat treatment in the SOI wafer manufacturing process or the device process, and the disconnection does not occur in the wiring process. It can be significantly improved.

Here, the rapid heating / rapid cooling means a method in which a wafer is immediately put into a heat treatment furnace set in the above temperature range and immediately taken out after a lapse of the heat treatment time,
This is a method in which a wafer is placed at a set position in a heat treatment furnace and then heat-treated immediately with a lamp heater or the like. This immediate loading and unloading means that the wafer is heated and lowered for a certain period of time, and the wafer is placed in a heat treatment furnace.
That is, the so-called loading and unloading operations of slowly loading and unloading are not performed. However, it takes a certain amount of time to carry the wafer to a predetermined position in the furnace, and it takes several seconds to several minutes depending on the ability of the moving device for loading the wafer. A rapid heating / cooling device (Rap
id Thermal Annealer, hereafter RTA
Device).

The invention according to claim 3 of the present invention is directed to a method of converting SO from silicon single crystal by the Czochralski method.
A bond wafer for forming an I layer is formed, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film.
In the method for producing an I-wafer, a silicon single crystal in which a COP having an oxygen concentration of 16 ppma or less exists at a high density by raising the growth rate of a silicon single crystal by the Czochralski method to 0.6 mm / min or more as the bond wafer. A rod is grown, the silicon single crystal rod is sliced and processed into a silicon wafer, and the silicon wafer is subjected to a heat treatment at a temperature of 1200 ° C. or more for 30 minutes or more in a reducing atmosphere using a batch type heat treatment furnace. This is a method for manufacturing an SOI wafer, characterized in that the method described above is used.

As described above, in the method for producing an SOI wafer using a CZ wafer as a bond wafer, a silicon wafer obtained by slicing a silicon single crystal rod having the same quality as the invention described in claim 1 is used as the bond wafer. When a batch type heat treatment furnace is used which is subjected to heat treatment at a temperature of 1200 ° C. or more for 30 minutes or more in a reducing atmosphere, the SOI layer of the SOI wafer has a greatly reduced COP, and the SOI The buried oxide film is not etched by the etching or heat treatment in the wafer manufacturing process or the device process, and the disconnection does not occur in the wiring process, so that the yield in the device process and the like can be significantly improved.

Here, the batch type heat treatment furnace is usually one in which a plurality of wafers are placed on a plurality of shelves provided in a vertical heat treatment furnace, or a plurality of wafers are charged in a boat provided in a horizontal heat treatment furnace. There is a thing, after introducing hydrogen gas and raising the temperature relatively slowly, heat-treated at a predetermined temperature for a predetermined time,
It is a furnace that performs heat treatment in a so-called batch type that cools down relatively slowly, so that a large amount of heat treatment can be performed at once,
Excellent controllability of temperature and stable operation.

In this case, as described in claim 4, it is preferable that the bond wafer subjected to the reducing heat treatment is polished before bonding to the base wafer. It is preferable to polish with a polishing allowance of 5 to 15 nm. This is because the surface of the wafer subjected to the reducing heat treatment has a surface roughness called haze, and if the surface is polished to about 5 to 15 nm and then bonded, the haze caused by the heat treatment can be removed. ,
This is because the occurrence rate of voids (unbonded portions) can be reduced and the bonding strength can be improved.

In this case, as described in claim 6, the thinning of the bond wafer can be performed by a grinding / polishing method and a vapor phase etching method. Here, in the grinding / polishing method and the vapor phase etching method, a bond wafer and a base wafer are bonded via an oxide film, and then the bond wafer is ground until a desired SOI layer thickness is obtained. This is a method of improving the surface roughness of the SOI layer surface and making the film thickness uniform by performing a polishing method or further performing a vapor phase etching, so that the thickness of the bond wafer can be easily reduced.

In this vapor phase etching, for example, P
ACE (Plasma Assisted Chemi
The distribution of the thickness of the silicon layer to be etched is measured in advance by a method such as the cal etching method, and a map of the thickness distribution is created. The thick portion is locally vapor-phase-etched by numerical control according to the map. The method of producing a thin film which is extremely thin and has a very uniform film thickness can be mentioned.

In this case, as described in claim 7, the thinning of the bond wafer can be performed by an ion implantation separation method. Here, the ion implantation separation method means that an oxide film is formed on at least one of two wafers, a bond wafer and a base wafer, and hydrogen ions or rare gas ions are implanted from the upper surface of the bond wafer.
After forming a microbubble layer (encapsulation layer) inside the wafer, the surface into which the ions are implanted is brought into close contact with the base wafer via an oxide film, and then heat treatment is applied to make the microbubble layer a cleavage surface. In this method, the bond wafer is separated into a thin film to reduce the thickness of the bond wafer (see Japanese Patent Application Laid-Open No. 5-211128). With such a method, the cleavage plane is a good mirror surface, and an SOI wafer having high uniformity of the thickness of the SOI layer can be obtained relatively easily.

As described in claim 8 of the present invention, if the reducing atmosphere is a 100% hydrogen atmosphere or a mixed atmosphere of hydrogen and argon, the heat treatment effect is sufficiently improved and the COP is significantly reduced. Then, the cavity can be filled with silicon to make a substantially defect-free wafer.

Further, the invention according to claim 9 of the present invention is an SOI wafer manufactured by the manufacturing method according to any one of claims 1 to 8. As described above, the SOI wafer manufactured by the manufacturing method according to any one of claims 1 to 8 has an extremely small COP of the SOI layer, and can be actually a defect-free SOI wafer.
Therefore, an extremely high-quality SOI wafer with significantly improved device reliability and improved yield can be obtained.

Hereinafter, the present invention will be described in more detail. The inventors of the present invention have conducted various experiments and investigations on manufacturing conditions for reducing the COP present on the surface or inside of a CZ wafer used for a bond wafer for forming an SOI layer of an SOI wafer. This involves pulling a single crystal at a high speed to produce a single crystal rod having a low oxygen concentration and a high density of micro-sized COPs at high density, and subjecting the obtained wafer to a heat treatment such as hydrogen annealing to obtain a COP. The inventors have found that the density is significantly reduced, and that a defect-free SOI wafer can be obtained from this silicon wafer.

The basic concept of the present invention is based on the following findings. The inventor of the present invention has found that a COP in a silicon single crystal pulled under the ordinary conditions of the Czochralski method has a regular octahedral cavity surrounded by a thin oxide film having a thickness of 2 to 4 nm. The total size is 100 with three connected structures
In addition to twin-triplet type COPs on the order of ~ 300 nm, the size of one independent octahedral cavity is on the order of 60-130 nm, and the oxide film is even thinner or present than the twin-triplet type. We have discovered for the first time that there is no single type COP.

The difference between the single type and twin to triplet type COP formation conditions is that when the Czochralski method is used to pull up and quench at high speed, many single type and small size COPs are generated.
Single type C with very thin or no inner oxide film
An OP is generated. Conversely, when the film is pulled up at a low speed and slowly cooled, it grows into a twin-triplet type COP and its number decreases, but the oxide film on the inner wall of the COP tends to become thick.

Therefore, as a result of analyzing the above phenomenon in more detail, it has been found that, in the past, single crystal growth was carried out at a low speed in order to reduce defects such as COP, and the remaining large twin to triplet type COP was turned into a wafer. It turned out that it was going to disappear by hydrogen annealing. This is 1
Since the individual COPs are too large and have a thick oxide film on the surface thereof, it is difficult to eliminate them by hydrogen annealing. On the other hand, in the present invention, on the contrary, a single crystal having a low oxygen content is grown at a high speed, and a large number of small COPs having no oxide film on the surface or a thin single COP even with the oxide film are generated. After making a single-crystal rod that has been subjected to a heat treatment such as hydrogen annealing, the COP
Is thought to be easily and completely extinct.

In the present invention, the pulling speed is set to 0.6 mm / min or more, more preferably 0.8 mm / min or more, and the number of COPs is large. It is assumed that there are many single types having a size as small as ~ 130 nm, so that they do not grow to a twin or triplet type as much as possible. Therefore, in the present invention, it is more preferable that the crystal is grown at a speed as high as possible according to the diameter of the pulled crystal, for example, 1.0 mm / min or more. If it is less than 0.6 mm / min, the cooling is slow and the twin-triplet type COP grows and the number thereof decreases, but the oxide film on the inner wall of the COP also becomes undesirably thick. The size of one single COP is about 60 to 130 nm, and the oxide film on the inner wall is not often grown at a low oxygen concentration.

As the quality of the silicon single crystal rod, the oxygen concentration is 16 ppma (JEIDA) or less, preferably 1 ppm.
0 ppma or less. If the concentration exceeds 16 ppma, the oxide film on the inner wall of the generated COP becomes thicker, and the COP disappears in the subsequent heat treatment incompletely or the heat treatment time becomes longer, thereby affecting the quality and productivity of the SOI wafer. .

In order to control the concentration of oxygen contained in the silicon single crystal rod, the flow rate of the inert gas, the number of rotations of the crucible, the rotation speed of the grown single crystal, the temperature of the silicon melt, and the like in the single crystal pulling furnace are appropriately controlled. It can be easily achieved by a conventionally known method.

Subsequently, by subjecting the silicon wafer obtained by slicing the silicon single crystal rod to a heat treatment in a reducing atmosphere, the COP can be significantly reduced.
It is also possible to make the COP density substantially zero. By using this heat-treated wafer as a bond wafer for forming an SOI layer, a substantially defect-free S
An SOI wafer having an OI layer can be manufactured.

A silicon wafer obtained by slicing the silicon single crystal rod is rapidly heated and cooled by a rapid cooling device (R).
TA device) or a batch type heat treatment furnace, heat treatment is performed in a reducing atmosphere of 100% hydrogen concentration or a mixture of hydrogen and argon at a temperature of 1200 ° C. or more, and a batch type heat treatment furnace for 1 second or more with an RTA device. Then for more than 30 minutes,
Staying can significantly reduce COP. In particular, according to the heat treatment conditions, it is possible to make the COP density substantially zero. Then, by using the heat-treated wafer as a bond wafer for forming an SOI layer, an SOI having a substantially defect-free SOI layer is obtained.
An I wafer can be manufactured.

The inventor conducted a study on the case where the defect-free CZ silicon wafer obtained as described above was applied as a bond wafer of an SOI wafer, and found that the bond wafer subjected to this heat treatment was oxidized with a base wafer. It has been found that it is preferable to polish the surface of the bond wafer with a polishing allowance of about 5 to 15 nm before bonding through the film.

The surface of the bond wafer that has been subjected to heat treatment such as hydrogen annealing is roughened by high density, very small shallow pits (dents) at the bottom, generally called haze. This haze causes voids when subsequently bonded to the base wafer. The voids may cause poor bonding between the bond wafer and the base wafer. Therefore, if the surface of the bond wafer is polished with a small polishing allowance of about 5 to 15 nm after the heat treatment, the haze can be completely removed and the bonding strength can be enhanced. Since the effect of reducing the COP by the heat treatment is more remarkable as it is closer to the surface of the bond wafer, it is preferable that the polishing allowance be smaller as far as the haze can be removed.

Then, the thickness of the bond wafer is reduced and S
An OI layer is formed, and the thickness of the bond wafer is reduced.
It can be performed by a usual polishing / grinding method and a vapor phase etching method, or can be performed by an ion implantation separation method.

Here, in the case where the bond wafer is made thinner by the ion implantation separation method, it is preferable that after the polishing for removing the haze generated by the heat treatment described above, ions are implanted into the polished surface. This is because, if polishing is performed after the implantation, the variation in the allowance for the polishing deteriorates the distribution of the implantation depth, and as a result, the uniformity of the thickness of the SOI layer may be deteriorated. If ions are implanted after the polishing for removing the haze, it is possible to prevent the film thickness uniformity of the SOI layer from deteriorating.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described, but the present invention is not limited to these embodiments.
The heating method used in the heat treatment process of the present invention, which can rapidly heat and rapidly cool a silicon wafer, includes a lamp heating method using heat radiation, a laser heating method using a laser beam, an X-ray heating method using X-rays, and resistance heating. An apparatus such as a heater according to the method can be used. As commercially available products, for example, SHS-28 manufactured by AST
Devices such as 00 are not particularly complex and expensive.

Here, an example of a rapid heating / cooling apparatus (RTA apparatus) for a silicon single crystal wafer used in the present invention will be described. FIG. 3 is a schematic diagram of an RTA apparatus. The heat treatment apparatus 20 shown in FIG. 3 has a bell jar 11 made of, for example, silicon carbide or quartz, and heats a wafer in the bell jar 11. Heating is performed by heaters 12 and 12 ′ arranged so as to surround the bell jar 11. The heater is divided in the vertical direction, so that the power supplied independently can be controlled. Of course, the heating method is not limited to this, and may be so-called radiant heating, high-frequency heating, or the like. A housing 13 for shielding heat is arranged outside the heaters 12 and 12 '.

A water cooling chamber 14 and a base plate 15 are arranged below the furnace, and seal the inside of the bell jar 11 from the outside air. The wafer 18 is held on a stage 17.
9 is attached to the upper end of a support shaft 16 that can move up and down. The water cooling chamber 14 is provided with a wafer insertion port (not shown) that can be opened and closed by a gate valve so that the wafer can be taken in and out of the furnace from a lateral direction. Further, the base plate 15 is provided with a gas inlet and an outlet, so that the gas atmosphere in the furnace can be adjusted.

The heat treatment for rapidly heating / cooling the wafer by the heat treatment apparatus 20 as described above is performed as follows. First, the inside of the bell jar 11 is heated to a desired temperature of, for example, 1200 ° C. or more by the heaters 12 and 12 ′, and is maintained at that temperature. If the supply power is controlled independently for each of the divided heaters, a temperature distribution can be provided in the bell jar 11 along the height direction. Therefore, the processing temperature of the wafer depends on the position of the stage 17,
That is, it can be determined by the insertion amount of the support shaft 16 into the furnace.

When the inside of the bell jar 11 is maintained at the desired temperature, the wafer is inserted from the insertion port of the water cooling chamber 14 by a wafer handling device (not shown) disposed adjacent to the heat treatment device 20 and is made to stand by at the lowermost position. A wafer is placed on the stage 17 through, for example, a SiC boat. At this time, since the water cooling chamber 14 and the base plate 15 are water cooled, the temperature of the wafer does not rise at this position.

When the mounting of the wafer on the stage 17 is completed, the motor 19 immediately rotates the support shaft 1.
The stage 17 is moved to 12 by inserting 6 into the furnace.
The temperature is raised to a desired temperature position of 00 ° C. or higher, and high-temperature heat treatment is applied to the wafer on the stage. In this case, the movement from the lower end position of the stage in the water cooling chamber 14 to the desired temperature position takes, for example, only about 20 seconds, so that the wafer is rapidly heated.

Then, the stage 17 is moved to a desired temperature position.
By stopping for a predetermined time (1 second or more), high-temperature heat treatment for the stop time can be applied to the wafer.
When the predetermined time has elapsed and the high-temperature heat treatment has been completed, the support shaft 16 is immediately pulled out of the furnace by the motor 19 to lower the stage 17 to the lower end position in the water cooling chamber 14. This lowering operation can be performed, for example, in about 20 seconds. The wafer on the stage 17 is rapidly cooled because the water cooling chamber 14 and the base plate 15 are water cooled. Finally, by taking out the wafer with the wafer handling device,
Complete the heat treatment. If there is a wafer to be further heat-treated, the temperature of the heat treatment apparatus 20 has not been lowered.
Wafers can be added one after another to perform continuous heat treatment.

The reducing atmosphere of the heat treatment is hydrogen gas 100
%, But may be a gaseous mixture with argon for adjusting the reducing power of hydrogen, suppressing the occurrence of slip dislocation, and other safety reasons. The temperature condition of the heat treatment was 1200 ° C. or higher, and the processing time was 1 second or longer. If the temperature is lower than 1200 ° C., it is difficult to completely eliminate the COP, and if it is shorter than 1 second, the heat treatment effect cannot be obtained.

As described above, the small size CO of the present invention is used.
A wafer obtained by heat-treating a P-containing wafer using an RTA apparatus, in particular, the COP on the surface almost disappears, and can be a defect-free silicon wafer. Therefore, this heat-treated wafer is used as a bond wafer in S
If an OI wafer is manufactured, it is possible to obtain an SI having a defect-free SOI layer.
An OI wafer can be manufactured, and the yield of device manufacturing can be improved. In the case of an RTA device, the temperature rise rate is extremely fast, and the time required to reach the temperature at which the COP disappears is extremely short. it is conceivable that.

As another heat treatment apparatus, a batch type heat treatment furnace can be used. Here, a batch-type heat treatment furnace is generally a method in which a plurality of wafers are placed in a vertical or horizontal heat treatment furnace, hydrogen gas is introduced, and the temperature is raised relatively slowly, followed by heat treatment at a predetermined temperature for a predetermined time. This is a so-called batch type heat treatment furnace that performs heat treatment and lowers the temperature relatively slowly. This batch type heat treatment furnace can perform a large amount of heat treatment at a time, has excellent temperature controllability, and can operate stably.

The heat treatment conditions such as hydrogen annealing in a batch type heat treatment furnace are basically the same as in the case of the above RTA apparatus, and the treatment is performed at 1200 ° C. or more in a 100% hydrogen gas atmosphere or a mixed atmosphere with argon. The heat treatment time is desirably 30 minutes or more. If the time is less than 30 minutes, the heat treatment effect is not sufficiently obtained, and the COP does not disappear much.

As described above, even with the batch type heat treatment furnace, the COP of the wafer obtained by heat-treating the wafer having the small COP of the present invention has almost disappeared, and a defect-free silicon single crystal wafer is manufactured. be able to. Therefore, if an SOI wafer is manufactured by using this heat-treated wafer as a bond wafer, an SOI wafer having a defect-free SOI layer can be manufactured, and the yield of device manufacturing can be improved.

According to another measurement method, the COP of the surface layer of the wafer to a depth of about 0.5 μm from the wafer surface is determined.
The total number of R
An advantageous result is obtained, which is about half that of the case where processing is performed by a TA device, and can be used properly with an RTA device according to the purpose.

It is preferable that the silicon wafer thus obtained is polished to remove the haze generated by the above-mentioned heat treatment for reducing, to obtain a bond wafer for forming an SOI layer of the SOI wafer. Hereinafter, the bond wafer and the base wafer are bonded via an oxide film,
Thereafter, a method of manufacturing a SOI wafer by thinning the bond wafer will be described with reference to the drawings.
The present invention is not limited to these.

First, the thinning of the bond wafer is performed by grinding and bonding.
The case of performing the polishing method and the vapor phase etching method will be described. Here, FIG. 1 shows the SOI when the thinning of the bond wafer is performed by a grinding / polishing method and a vapor phase etching method.
1 shows an example of a wafer manufacturing process.

In FIG. 1, first, the SOI is
A bond wafer 2 and a base wafer 3, which are raw material wafers for manufacturing a substrate, are prepared (FIG. 1A).
Here, in the present invention, at least the bond wafer 2 forming the SOI layer is raised with the growth rate of the silicon single crystal by the above-mentioned Czochralski method being 0.6 mm / min or more, and the COP having an oxygen concentration of 16 ppma or less is high. A silicon single crystal rod having a high density is grown, and a defect-free silicon wafer is produced by a method in which a wafer obtained from the single crystal rod is subjected to a reducing heat treatment using an RTA apparatus or a batch type heat treatment furnace. Of course, two wafers may be used as the defect-free silicon wafer.

Then, at least one of the prepared silicon wafers is subjected to an oxidizing heat treatment to form an oxide film 4 on the surface of the wafer (FIG. 1B). In this case, the oxide film need not always be formed on both wafers, but may be formed only on the bond wafer 2 or on the base wafer 3.
It may be formed only.

Next, the bond wafer 2 having the oxide film formed thereon and the base wafer 3 are adhered to each other in a clean atmosphere (FIG. 1C). This is subjected to a heat treatment in an oxidizing atmosphere, so that the bond wafer 2 and the base wafer 3 are firmly bonded, and the SOI substrate 1 is obtained. At this time, bond wafer 2
And the base wafer 3 are firmly bonded (FIG. 1
(D)). As a heat treatment condition of the heat treatment for firmly bonding the two wafers, for example, the heat treatment may be performed at a temperature of 200 ° C. to 1200 ° C. in an atmosphere containing oxygen or water vapor.

Next, as shown in FIG. 1E, if the surface of the bond wafer 2 is thinned to a desired thickness by grinding / polishing and vapor phase etching according to a usual method, a substantially defect-free SOI The SOI substrate 1 having the layer 5 can be manufactured. In this case, when etching is performed by the PACE method, the flatness of the SOI layer becomes extremely good.

On the other hand, a case where the bond wafer is thinned by an ion implantation separation method will be described. here,
FIG. 2 shows an example of a manufacturing process of an SOI wafer in a case where a bond wafer is thinned by an ion implantation separation method.

In FIG. 2, first, the SOI is
A bond wafer 2 and a base wafer 3, which are raw material wafers for manufacturing a substrate, are prepared (FIG. 2A).
Here, in the present invention, at least the bond wafer 2 forming the SOI layer is raised with the growth rate of the silicon single crystal by the above-mentioned Czochralski method being 0.6 mm / min or more, and the COP having an oxygen concentration of 16 ppma or less is high. A silicon single crystal rod having a high density is grown, and a defect-free silicon wafer is produced by a method in which a wafer obtained from the single crystal rod is subjected to a reducing heat treatment using an RTA apparatus or a batch type heat treatment furnace. Of course, two wafers may be used as the defect-free silicon wafer.

Then, an oxidizing heat treatment is performed on the prepared silicon wafer to form an oxide film 4 on the surface of the wafer (FIG. 2B). In this case, the oxide film need not always be formed on both wafers, and may be formed only on the bond wafer 2 or only on the base wafer 3.

Next, hydrogen ions or rare gas ions are implanted into the surface of the bond wafer 2 that is bonded to the base wafer 3 to form a microbubble layer (enclosure layer) 6 parallel to the surface of the bond wafer ( (FIG. 2 (c)). Here, since the haze generated by the heat treatment for obtaining the defect-free silicon wafer has been removed by polishing at the prepared stage, unlike the case of polishing after ion implantation, the SOI layer film is formed. There is no adverse effect on thickness uniformity.

Then, the base wafer 3 is overlapped and adhered to the implantation surface of the bond wafer 2 into which hydrogen ions or rare gas ions have been implanted via an oxide film (FIG. 2).
(D)). By bringing the surfaces of the two wafers into contact with each other in a clean atmosphere at room temperature, the wafers are bonded to each other without using an adhesive or the like.

Next, the wafer is separated into the peeled wafer 7 and the SOI wafer 1 by peeling with the sealing layer 6 as a boundary (FIG. 2E). For example, if heat treatment is performed at a temperature of about 500 ° C. or more in an inert gas atmosphere, the wafer can be separated into the separation wafer 7 and the SOI wafer 1 by rearrangement of crystals and aggregation of bubbles.

Since the bonding force between the adhered wafers is weak for use in the device process as it is,
As a bonding heat treatment, a high-temperature heat treatment is performed on the SOI wafer 1 to make the bonding strength sufficient (FIG. 2 (f)). This heat treatment is performed, for example, in an inert gas atmosphere at 1050 ° C. to 120 ° C.
The heat treatment may be performed at 0 ° C. for 30 minutes to 2 hours. Thus, an SOI wafer having a substantially defect-free SOI layer can be obtained (FIG. 2G).

As described above, regardless of the method, the method for manufacturing an SOI wafer of the present invention provides a defect-free SOI wafer.
A high quality SOI wafer having an OI layer can be manufactured. In the present invention, especially when the SOI layer is thinned to 1 μm or less, since there is no COP, a through hole does not occur in the SOI layer, and thus the method of the present invention is highly valuable. Then, the S manufactured by this method
An OI wafer is a high-quality SOI wafer having an SOI layer with high electrical reliability, has a high device fabrication yield, and has extremely high industrial utility value.

[0066]

EXAMPLES The present invention will be described in detail below with reference to examples of the present invention and comparative examples, but the present invention is not limited to these examples. (Example 1, Comparative Example 1) A bond wafer for forming an SOI layer from a silicon single crystal by the Czochralski method is manufactured, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film. Thereafter, the bond wafer was thinned to produce an SOI wafer.

In this embodiment, first, the pulling speed (SE) of the silicon single crystal by the Czochralski method is set to 1.4.
mm / min, and the contained oxygen concentration (Oi) is 12 ppm
a, a silicon single crystal rod is grown, and the single crystal rod is sliced and processed into a silicon wafer.
0>, the conductivity type is p-type, the resistivity is 10 Ω · cm,
A silicon wafer having a diameter of 200 mm was manufactured.

An RTA device (A) is attached to this silicon wafer.
Using SHS-2800 manufactured by ST Co., Ltd., heat treatment was performed at 1200 ° C. for 10 seconds in an atmosphere of 100% hydrogen. The silicon wafer was used as a bond wafer for forming an SOI layer. The surface of the bond wafer bonded to the base wafer was polished with a polishing allowance of 10 nm, and the haze generated by the heat treatment on the wafer surface was removed.

Using this bond wafer, FIG.
(G), the thickness of the SOI layer becomes about 100
nm SOI wafers were produced. The main manufacturing conditions are as follows. 1) Oxide film formation condition: Bond wafer oxide film thickness 75n
m, base wafer oxide film thickness 325 nm, 2) hydrogen ion implantation conditions: implantation energy 20 keV,
Implantation dose: 8 × 10 ¹⁶ atoms / cm ² , 3) Stripping heat treatment condition: 500 ° C. under N ₂ gas atmosphere, 3
0 min, 4) Bonding heat treatment condition: 1100 ° C. under N ₂ gas atmosphere
2 hours.

The COP of the SOI layer of the SOI wafer thus manufactured was observed by the HF dip method.
In this HF dip method, first, an SOI wafer is HF5
When immersed in a 0% aqueous solution for about ten minutes, if there is a defect penetrating the SOI layer, HF reaches the buried oxide film through this and the oxide film is etched to form an etch pit. Then, the etch pits formed in the oxide film are observed by an optical microscope through a thin SOI layer to obtain C pits.
Observe the OP. In the microscope observation in this example, the number of pits in a total area of 20 cm ² was observed by scanning in the diameter direction of the wafer surface.

As a result of this measurement, the number of pits observed was 0, and when converted to COP density, 0 pits / cm ²
Met. From this measurement result, it is understood that an SOI wafer having a substantially defect-free SOI layer can be manufactured by the manufacturing method of the present invention.

On the other hand, as Comparative Example 1, a silicon single crystal was grown under the same conditions as in Example 1 to prepare a silicon wafer, and the SOI wafer was manufactured in the same process except that the heat treatment was not performed on the wafer by the RTA apparatus. Was manufactured. The COP of the SOI wafer of Comparative Example 1 was observed by the HF dip method as in Example 1. As a result of this measurement, the number of observed pits was 57,
In terms of COP density, it was 2.9 particles / cm ² . From the measurement results, it is expected that the wafer of Comparative Example 1 will have lower electrical reliability and lower device fabrication yield.

Example 2 and Comparative Example 2 Other than the oxygen concentration,
In substantially the same manner as in Example 1, a bond wafer for forming an SOI layer from a silicon single crystal by the Czochralski method is manufactured, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film. An SOI wafer was manufactured by thinning the bond wafer.

In this embodiment, first, a silicon single crystal rod was grown in the same manner as in Example 1 except that the oxygen content (Oi) was 16 ppma, and this single crystal rod was sliced and processed into a silicon wafer. Crystal orientation is <100>
Thus, a silicon wafer having a p-type conductivity, a resistivity of 10 Ω · cm, and a diameter of 200 mm was produced.

The silicon wafer was placed in a 100% hydrogen atmosphere using a batch heat treatment furnace.
A heat treatment was applied at 0 ° C. for 60 minutes. Then, this silicon wafer is used as a bond wafer for forming an SOI layer, and the surface of the bond wafer bonded to the base wafer has a polishing allowance of 1 mm.
Polishing was performed to a thickness of 0 nm to remove haze caused by heat treatment on the wafer surface.

Using this bond wafer, an SOI wafer was manufactured under the same steps and under the same manufacturing conditions as in Example 1. Then, as in the first embodiment, S by the HF dip method is used.
The COP of the OI layer was observed. As a result of this measurement, the number of pits observed was 6, which was 0.3 / cm ² in terms of COP density. From this measurement result,
SOI with very few defects by the manufacturing method of the present invention
It can be seen that SOI wafers having layers can be manufactured.

On the other hand, as Comparative Example 2, a silicon single crystal was grown under the same conditions as in Example 2 to produce a silicon wafer, and the SOI was performed in the same process except that the wafer was not subjected to a heat treatment in a batch type heat treatment furnace. Wafers were manufactured. The COP was observed on the SOI wafer of Comparative Example 2 by the HF dip method as in Example 2. As a result of this measurement, the number of observed pits was 62,
It was 3.1 pieces / cm ² in terms of COP density. From this measurement result, the wafer of Comparative Example 2 showed COP
It is expected that the electrical reliability and the device fabrication yield will decrease due to the above.

(Example 3 and Comparative Example 3) A bond wafer for forming an SOI layer from a silicon single crystal by the Czochralski method is manufactured, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film. Then, the bond wafer was thinned to produce an SOI wafer.

In this embodiment, first, a silicon single crystal rod was grown in the same manner as in Embodiment 1 except that the pulling speed of silicon was 0.95 mm / min and the oxygen concentration (Oi) was 16 ppma. A single crystal rod is sliced and processed into a silicon wafer, and the crystal orientation is <100>
Thus, a silicon wafer having a p-type conductivity, a resistivity of 10 Ω · cm, and a diameter of 200 mm was produced.

The same heat treatment as in Example 1 was applied to this silicon wafer. Then, this silicon wafer is S
The bond wafer for forming the OI layer was polished with a polishing allowance of 10 nm on the surface of the bond wafer bonded to the base wafer, and the haze generated by the heat treatment on the wafer surface was removed.

Using this bond wafer, FIG.
SOI wafers were manufactured by the steps shown in FIGS. The main manufacturing conditions are as follows. 1) Oxide film formation conditions: bond wafer oxide film thickness 150n
m, base wafer oxide film thickness 0 nm, 2) bonding heat treatment condition: 1100 ° C. in an O ₂ gas atmosphere
2 hours, 3) Grinding / polishing conditions: grinding / polishing until the SOI layer thickness becomes 4 μm, 4) Thinning conditions: PACE processing until the SOI layer thickness reaches 110 nm, and polishing with a polishing allowance of 10 nm.

The COP of the SOI layer was observed on the SOI wafer thus manufactured by the HF dip method as in the first embodiment. As a result of this measurement, the number of observed pits was one, which was 0.1 pits / cm ² in terms of COP density. From this measurement result, it is understood that an SOI wafer having a substantially defect-free SOI layer can be manufactured by the manufacturing method of the present invention.

On the other hand, as Comparative Example 3, a silicon single crystal was grown under the same conditions as in Example 3 to prepare a silicon wafer, and the SOI wafer was subjected to the same process except that the heat treatment was not performed on the wafer by the RTA apparatus. Manufactured. The same HF as in Example 1 was added to the SOI wafer of Comparative Example 3.
The COP was observed by the dip method. As a result of this measurement, the number of pits observed was 43,
It was 2.2 pieces / cm ² in terms of density. From this measurement result, it is expected that the wafer of Comparative Example 3 will have lower electrical reliability and lower device fabrication yield.

The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the scope of the claims of the present invention. It is included in the technical scope of the invention.

For example, in the above embodiment, the description has been made mainly on the case of manufacturing an SOI substrate by bonding two silicon wafers. However, the present invention relates to a silicon wafer manufactured by the Czochralski method and quartz, silicon carbide, or the like. In the case where an SOI substrate is manufactured by bonding an insulating substrate such as silicon nitride, alumina, sapphire, and other ceramic materials, the method is effective in reducing crystal defects in the SOI layer and is applicable. Needless to say.

Further, in the above embodiment, the case where the bond wafer forming the SOI layer is a CZ wafer having a diameter of 200 mm has been mainly described. However, the present invention is not limited to this, and the present invention is not limited to this. The present invention is also applicable to a case where the diameter is small or a case where the diameter is small, such as 150 mm or less.

Further, in the above embodiment, the SOI wafer is manufactured after the heat treatment is performed on the bond wafer.
Even if an SOI wafer is manufactured using bond wafers having the same specifications and then subjected to the same heat treatment, the same effect as the present invention can be obtained.

[0088]

As described in detail above, the SOI of the present invention
By manufacturing an SOI wafer by the method of manufacturing a wafer, an SOI wafer having almost no COP in the SOI layer can be obtained.
Wafers can be obtained with high productivity. Therefore, S
The electrical reliability of the OI wafer and the yield of device fabrication can be improved.

[Brief description of the drawings]

1 (a) to 1 (e) show S in a case where a bond wafer is thinned by a grinding / polishing method and a vapor phase etching.
1 shows an example of an OI wafer manufacturing process.

FIGS. 2A to 2G show an example of a manufacturing process of an SOI wafer in a case where a bond wafer is thinned by an ion implantation separation method.

FIG. 3 is a schematic view showing an example of an apparatus capable of rapidly heating and rapidly cooling a wafer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... SOI wafer, 2 ... Bond wafer, 3 ... Base wafer, 4 ... Oxide film, 5 ... SOI layer, 6 ... Microbubble layer (encapsulation layer), 7 ... Exfoliation wafer, 11 ... Bell jar, 12,12 '... Heating Heater, 13 ... housing, 14: water cooling chamber, 15: base plate,
16: Support shaft, 17: Stage, 18: Silicon wafer, 19: Motor, 20: Heat treatment device.

Continuation of the front page (72) Inventor Junichiro Furata 2-13-1, Isobe, Annaka-shi, Gunma Prefecture Shin-Etsu Semiconductor Semiconductor Isobe Laboratory (72) Inventor Kiyoshi Mitani 2-3-1, Isobe, Annaka-shi, Gunma Prefecture No. Shin-Etsu Semiconductor Co., Ltd. Semiconductor Isobe Laboratory F-term (reference) 4G077 AA02 AA03 BB03 CF00 EB06 EH09 FB05 FE05 FF01 FF07

Claims (9)

[Claims] 1. A bond wafer for forming an SOI layer from a silicon single crystal by a Czochralski method is produced, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film. In the method of manufacturing an SOI wafer for forming a thin film, as the bond wafer, the growth rate of a silicon single crystal by the Czochralski method is increased to 0.6 mm / min or more, and the CO content is 16 ppma or less.
Growing a silicon single crystal rod in which P exists in high density, slicing the silicon single crystal rod into a silicon wafer, and applying a heat treatment in a reducing atmosphere to the silicon wafer; SOI wafer manufacturing method. 2. A bond wafer for forming an SOI layer from a silicon single crystal by the Czochralski method is formed, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film. In the method of manufacturing an SOI wafer for forming a thin film, as the bond wafer, the growth rate of a silicon single crystal by the Czochralski method is increased to 0.6 mm / min or more, and the CO content is 16 ppma or less.
A silicon single crystal rod in which P exists at a high density is grown, the silicon single crystal rod is sliced and processed into a silicon wafer, and the silicon wafer is subjected to a 1200 heating in a reducing atmosphere by using a rapid heating / cooling apparatus. A method for producing an SOI wafer, comprising using a material subjected to a heat treatment at a temperature of not less than ° C. for at least one second. 3. A bond wafer for forming an SOI layer from a silicon single crystal by a Czochralski method is formed, and the bond wafer and a base wafer serving as a support substrate are bonded via an oxide film. In the method of manufacturing an SOI wafer for forming a thin film, as the bond wafer, the growth rate of a silicon single crystal by the Czochralski method is increased to 0.6 mm / min or more, and the CO content is 16 ppma or less.
P grows a silicon single crystal rod having a high density, slices the silicon single crystal rod into a silicon wafer, and processes the silicon wafer using a batch-type heat treatment furnace.
S characterized by using a material which has been subjected to a heat treatment at a temperature of 1200 ° C. or more for 30 minutes or more in a reducing atmosphere.
A method for manufacturing an OI wafer. 4. The bond wafer having been subjected to the heat treatment,
4. The SO as claimed in claim 1, wherein the SO wafer is polished before being bonded to the base wafer.
A method for manufacturing an I wafer. 5. The method for manufacturing an SOI wafer according to claim 4, wherein the polishing is performed with a polishing allowance of 5 to 15 nm. 6. The method according to claim 1, wherein the bonding wafer is formed into a thin film by grinding.
The SOI according to any one of claims 1 to 5, wherein the SOI is performed by a polishing method and a vapor phase etching method.
Wafer manufacturing method. 7. The method for producing an SOI wafer according to claim 1, wherein the thinning of the bond wafer is performed by an ion implantation separation method. 8. The method for manufacturing an SOI wafer according to claim 1, wherein the reducing atmosphere is a 100% hydrogen atmosphere or a mixed atmosphere of hydrogen and argon. . 9. An SOI wafer manufactured by the manufacturing method according to claim 1.