JP2000041201A5 - - Google Patents

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Publication number
JP2000041201A5
JP2000041201A5 JP1998206396A JP20639698A JP2000041201A5 JP 2000041201 A5 JP2000041201 A5 JP 2000041201A5 JP 1998206396 A JP1998206396 A JP 1998206396A JP 20639698 A JP20639698 A JP 20639698A JP 2000041201 A5 JP2000041201 A5 JP 2000041201A5
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JP
Japan
Prior art keywords
output
image
interpolation
predetermined
vertical interpolation
Prior art date
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Pending
Application number
JP1998206396A
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Japanese (ja)
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JP2000041201A (en
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Publication date
Application filed filed Critical
Priority to JP10206396A priority Critical patent/JP2000041201A/en
Priority claimed from JP10206396A external-priority patent/JP2000041201A/en
Publication of JP2000041201A publication Critical patent/JP2000041201A/en
Publication of JP2000041201A5 publication Critical patent/JP2000041201A5/ja
Pending legal-status Critical Current

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Claims (6)

入力されたインターレース画像を縮小し出力する画像縮小表示装置において、
入力されたインターレース画像の所定の画素を補間する補間手段と、
前記補間手段の出力よりあらかじめ定められた画素を間引き、縮小画像を構成する画像縮小手段とを備え、
前記補間手段は、
垂直方向の所定の画素を補間する際、現在のフィールドの画像データを用いて所定の画素を補間する第1の垂直補間手段と、
一つ前のフィールドの画像データを用いて所定の画素を補間する第2の垂直補間手段と、
前記入力されたインターレース画像の動きを検出する動き検出手段と、
前記動き検出手段の出力に基づいて前記第1の垂直補間手段の出力と前記第2の垂直補間手段の出力の混合比率を制御する合成手段と
を備えたことを特徴とする画像縮小表示装置。
In an image reduction display device that reduces and outputs an input interlaced image,
And interpolation means for interpolating a predetermined pixel of the input interlaced Resu image,
Thinning out predetermined pixels from the output of the interpolation means, and image reduction means for forming a reduced image,
The interpolation means,
First vertical interpolation means for interpolating a predetermined pixel using image data of the current field when interpolating a predetermined pixel in the vertical direction;
Second vertical interpolation means for interpolating a predetermined pixel using image data of the immediately preceding field;
Motion detection means for detecting the motion of the input interlaced image,
An image reduction display device comprising: a synthesizing unit that controls a mixing ratio of an output of the first vertical interpolation unit and an output of the second vertical interpolation unit based on an output of the motion detection unit.
前記合成手段は、
輝度信号、及び色信号の状態で入力されたインターレース画像に縮小処理を施す際、輝度信号により検出した動き検出結果に基づいて色信号の前記第1の垂直補間手段の出力と前記第2の垂直補間手段の出力の混合比率を制御するように構成した
ことを特徴とする請求項1記載の画像縮小表示装置。
The combining means includes:
When performing reduction processing on an interlaced image input in a state of a luminance signal and a color signal, an output of the first vertical interpolation unit of the color signal and the second vertical interpolation of a color signal based on a motion detection result detected by the luminance signal. 2. The image reduction display device according to claim 1, wherein the mixing ratio of the output of the interpolation means is controlled.
前記補間手段は、
輝度信号、及び色信号の状態で入力されたインターレース画像に縮小処理を施す際、色信号に関しては第1の垂直補間手段の出力のみを用いる
ことを特徴とする請求項1記載の画像縮小表示装置。
The interpolation means,
2. The reduced image display device according to claim 1, wherein when performing reduction processing on the interlaced image input in the state of the luminance signal and the color signal, only the output of the first vertical interpolation means is used for the color signal. .
色信号の信号帯域を輝度信号の半分以下に制限する帯域制限手段を備え、
前記帯域制限手段から出力される色信号のサンプル数を輝度信号のサンプル数の半分以下にして画像縮小処理を施す
ことを特徴とする請求項1、2又は3の何れかに記載の画像縮小表示装置。
A band limiting unit that limits the signal band of the color signal to half or less of the luminance signal,
4. The image reduction display according to claim 1, wherein the number of samples of the color signal output from the band limiting unit is less than half the number of samples of the luminance signal to perform image reduction processing. apparatus.
前記動き検出手段により入力信号の動きを検出する際、
所定の補間画素の前記第1の垂直補間手段の出力と前記第2の垂直補間手段の出力との差分を演算する演算手段を備え、
前記演算手段から出力される演算結果を基に前記合成手段における混合比率を制御するように構成した
ことを特徴とする請求項1、2、3又は4の何れかに記載の画像縮小表示装置。
When detecting the motion of the input signal by the motion detection means,
Calculating means for calculating a difference between an output of the first vertical interpolation means and an output of the second vertical interpolation means for a predetermined interpolation pixel;
Image reducing display apparatus according to claim 1, 2, 3 or 4, characterized by being configured to control the mixing ratio of the synthesizing means on the basis of the calculation result output from the calculation means.
前記動き検出手段により入力信号の動きを検出する際、
所定の補間画素周辺のあらかじめ定められたエリアの前記第1の垂直補間手段の出力と前記第2の垂直補間手段の出力との差分を演算する演算手段を備え、
前記所定の補間画素周辺のあらかじめ定められたエリア内の演算結果の絶対値和を基に前記合成手段における混合比率を制御するように構成した
ことを特徴とする請求項1、2、3又は4の何れかに記載の画像縮小表示装置。
When detecting the motion of the input signal by the motion detection means,
Calculating means for calculating a difference between an output of the first vertical interpolation means and an output of the second vertical interpolation means in a predetermined area around a predetermined interpolation pixel;
5. The image processing apparatus according to claim 1, wherein a mixing ratio in said combining means is controlled based on a sum of absolute values of calculation results in a predetermined area around said predetermined interpolation pixel. An image reduction display device according to any one of the above.
JP10206396A 1998-07-22 1998-07-22 Image reduction display device Pending JP2000041201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10206396A JP2000041201A (en) 1998-07-22 1998-07-22 Image reduction display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10206396A JP2000041201A (en) 1998-07-22 1998-07-22 Image reduction display device

Publications (2)

Publication Number Publication Date
JP2000041201A JP2000041201A (en) 2000-02-08
JP2000041201A5 true JP2000041201A5 (en) 2004-09-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP10206396A Pending JP2000041201A (en) 1998-07-22 1998-07-22 Image reduction display device

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JP (1) JP2000041201A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5478728B2 (en) * 2011-03-03 2014-04-23 パナソニック株式会社 3D image processing apparatus and method, and 3D image display apparatus
US9497405B2 (en) 2012-07-17 2016-11-15 Nec Display Solutions, Ltd. Display device for displaying videos side by side without overlapping each other and method for the same

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