JP2000041031A - Method and device for executing data enciphery and error code correction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To encipher error code correction(ECC) encoding data without damaging the completeness of an ECC code word and to make an ECC circuit inexpensive. SOLUTION: A system is composed of a host processor 14 connected to a computer bus 12 so as to perform error correction, a providing means 18 for ECC encoding data for one block, means 24, 26 and 28 for performing enciphering mask and drive 16 equipped with an EX-OR 30 for each bit concerning the enciphering mask and ECC encoding data for one block, and the output of the EX-OR for each bit is coupled to the computer bus so that an enciphered block can be transmitted through the computer bus to the host processor for error correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to data storage and transmission. More particularly, the present invention relates to encryption of data including codewords used for forward error correction.

[0002]

2. Description of the Related Art Forward error correction is commonly performed on data transmission channels and data storage to maintain the integrity of user data. Before transmission or storage, redundant data is added to the user data.
Hard disk drive, compact disk (CD)
In data storage devices such as players, digital video disk (DVD) players, etc., errors can occur due to defects in the storage medium and noise in the read channel. If an error is detected in the transmitted or stored data, the error can be corrected by the redundant data.

There are various ways to perform forward error correction. For example, Reed-Solomon product code ("RS-PC") is used for CD players and DVD players.

[0004] CD players and DVD players include an error correction circuit for performing forward error correction. This error correction circuit requires strong computing power,
Usually implemented in a hardwired or inflexible manner. In addition, since the error correction circuit requires a processing circuit and a high-speed memory, the cost tends to be high.

With the recent increase in the processing power of personal computers, it has become practical to perform all or some of the forward error correction in a computer host processor instead of a data storage device. As the host processor becomes able to perform error correction, more flexible error correction methods are available. For example, the host processor can execute a default routine that is fast and can correct most errors. Errors that cannot be corrected by the default routine are corrected by more complex routines, such as the "heroic data recovery" routine. Heroic recovery is particularly valuable for long-term storage of data. Hard copies of valuable data can be corrupted after being stored on a storage medium (eg, a hard drive or CD platter). After storage, long-term degradation of the storage medium may occur over many years. A typical error correction circuit of a storage device may not be able to recover all of the data from a deteriorated storage medium. If such data cannot be recovered, it can be lost forever. However, with the use of a host processor, it is more likely to recover data using a heroic data recovery routine.

The task of performing error correction can be completely or partially transferred to the host processor. As a result, the cost of the storage device can be reduced. The decoder circuit can be reduced or omitted, and the size of the expensive static random access memory (RAM) can be reduced.

Alternatively, the task of performing error correction can be assigned to the host processor and the error correction circuit of the storage device. The task of correcting an error initially enters the error correction circuit. The error correction circuit utilizes a simple error correction algorithm to identify and correct the majority of errors. If the error correction circuit fails to correct the data block, the task is transferred to the host processor utilizing a more complex error correction routine. Such flexibility allows the storage device to use fast and inexpensive error correction circuits. As a result, the cost of the storage device can be reduced, and the reliability of performing error correction can be improved.

However, in particular, error code correction (“E
CC ") After performing data encryption on the data containing the codeword, problems may occur in connection with performing error correction at the host processor. When encrypting an ECC codeword, the integrity of the codeword is usually destroyed. As a result, the host processor cannot correct errors in the data.

[0009] The need in the art to encrypt data before it is transmitted from storage to a host processor is even stronger in the industry. This is especially true for computer DVD-ROM drives. Data is transferred via a computer bus
Sent from the DVD-ROM drive to the DVD decoder card, which is not secure. The unencrypted data located on this bus is intercepted and the ability to make unauthorized copies of high quality movie, music and intellectual property data is a real problem. Should unencrypted data be sent to the host processor for error correction, the unencrypted data is vulnerable to theft and unauthorized copying. Therefore, this data is not corrected by the error code in the host processor. Instead, error code correction is performed on the data in the DVD-ROM drive. The error code corrected data is then encrypted before being transmitted to the DVD decoder card over an insecure computer bus.

[0010]

So far, it has not been possible for the host processor to perform error correction due to the need for secure transmission over the computer bus. As a result, the cost of a DVD-ROM drive could not be reduced by omitting expensive decoders for performing error correction and reducing expensive RAM. Moreover, there is no flexibility to perform different error correction routines.

[0011]

According to the present invention, some or all data encryption can be performed in a drive, and some or all error correction can be performed by a host processor. One block of ECC encoded data is read. This ECC block is
Includes error correction codeword. An encryption mask is provided and a bitwise exclusive OR is performed with the ECC block. The bitwise exclusive OR product is an encrypted ECC block, which can then be transmitted to the host processor. Codeword integrity is preserved. This allows the host processor to perform some or all error correction on the encrypted ECC block.

The user data in the ECC block can be exclusively ORed with the number in the encryption mask, or the user data can be selectively XORed with the number in the encryption mask. it can. Portions of the ECC block that are XORed with zero or not XORed at all are not encrypted.

[0013] Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As illustrated in the drawings for purposes of illustration, the present invention is embodied in a system that includes a host processor and a storage device that reads data from a storage medium (eg, a compact disk or DVD disk).
The data includes an ECC codeword. The storage device performs data encryption on data read from the storage medium,
Maintain the integrity of the error correction codeword. This allows the encrypted data to be sent to the host processor over an insecure computer bus. The host processor can then perform error correction on the encrypted data. The decryption can then be performed by a trusted entity. Thus, according to the present invention, the host computer is able to access the E without risking exposing sensitive data on an insecure computer bus.
Error correction of some or all of the CC codewords can be performed.

In the following paragraphs, the present invention will be referred to as a DVD-RO
A computer system including an M drive and associated DVD-ROM electronics is described. The present invention is not limited to DVD-ROM drives, but is merely intended to facilitate understanding of the present invention.
It should be understood that M is explained.

FIG. 1 shows various components of computer system 10. The computer system 10 includes a computer bus 12 and a host processor 14 (e.g., a central processing unit) connected to the computer bus 12. In addition, the system 10 includes a DV including a DVD-ROM reader 18.
The DVD-ROM reader 18 includes a D-ROM drive 16 and an RS-ROM drive 16 stored on a DVD-ROM disc.
Operate to read PC blocks. The RS-PC block is read from the DVD disk and the controller
Under the control of 20, it is buffered in a random access memory (RAM) 22.

Each RS-PC block includes M rows of user data, and each word of the user data is N bytes.
Each of the M words has an RS with a length of p bytes
-With PC redundant data. Therefore RS-PC
Each row in the block has (N + p) bytes, so that the RS-PC block has (N + p) columns.
Each of the (N + p) columns is accompanied by RS-PC redundant data having a length of q bytes. As a result RS-P
The C block has (M + q) × (N + p) bytes. FIG. 6 shows such an RS-PC block 602.

The DVD-ROM drive 16 does not need to perform error code correction on the buffered RS-PC blocks. Instead, DVD-ROM drive 16
Performs encryption on the buffered RS-PC blocks. A first pseudo-random number generator 24 generates M × N blocks of random numbers, each random number having a length of one byte. For example, the random number may be generated from a seed accessed from the ROM module 26.

The random numbers of the M × N blocks are supplied to the RS-PC encoder 28, and the RS-PC encoder performs the RS-PC encoding on the M × N blocks. Encoder
The output of 28 provides an encryption mask having (M + q) * (N + p) bytes. An encoder 28 having multiple linear feedback shift registers is relatively simple to implement and inexpensive. Moreover, RS-PC encoding can be performed at a relatively high speed. Encoder 28 uses the same algorithm used to generate the codeword stored on the DVD disc.

The exclusive OR circuit 30 performs an exclusive OR (XOR) for each bit of the RS-PC block and the encryption mask.
Execute FIG. 3 illustrates the bitwise exclusive OR operation and is discussed below. As a result of a bitwise exclusive OR operation, the encrypted user data and the encrypted RS-P
(M + q) × (N + p) encrypted blocks containing C redundant data result.

Under the control of controller 20, the encrypted blocks are placed on computer bus 12 and stored in buffer 32 for error correction. Even if the computer bus 12 is not secure, the user data in the encrypted block is encrypted and therefore protected. Thus, a bus sniffer device such as a data analyzer and storage scope that can analyze data transferred across the computer bus 12 cannot easily utilize user data.

The host processor 14 is instructed to perform error correction by executable instructions stored in the memory 34. This instruction is being executed by the host processor 14, but the host processor 14
RS-P to the encrypted data block stored in 32
Execute C correction.

The host processor 14 is still encrypted, but has been corrected here (M + q) × (N + p).
The block is transmitted to the DVD decoder card 36 via the computer bus 12. This encrypted block is received and stored in the buffer 37 on the DVD decoder card 36. When the DVD decoder card 36 decrypts the encrypted block, it accesses the seed stored in the ROM 26, that is, the seed where the encryption mask has been generated. Modules 38 and 40 are DVD-ROM drives
Perform authentication and exchange of seeds between 16 and DVD decoder card 36. Authentication and exchange can be performed in a conventional manner.

The second pseudo random number generator 42 of the DVD decoder card 36 generates the same series of random numbers as generated by the first pseudo random number generator 24, and the second encoder 44
Generate a × N decryption mask. The decryption mask matches the random number of M × N blocks in the encryption mask. Thus, by transmitting a minimal amount of data (ie, a seed) via authentication and exchange modules 38 and 40, a decryption mask is generated.

Next, the second exclusive OR circuit 46 performs an exclusive OR for each bit of the M × N user data in the encrypted block stored in the buffer 37 and the decryption mask. The product of the bit-wise exclusive OR is M × N blocks of user data that are not encrypted.

The DVD decoder card 36 also includes a Moving Pictures Expert Group (MPEG) decoder 48, which receives the RS-PC block and decrypts the M × N byte block based on the MPEG standard. Decode the data. MPE
G decoder 48 outputs continuous decompressed data,
This continuous decompressed data is displayed on a video display. The decompressed data is sent directly to the display or display memory. The decompressed data is not transmitted on the computer bus 12.

The error-corrected and encrypted block can be received by another entity 49 downstream of the host processor 14. The downstream entity 49 can regenerate the encrypted blocks for subsequent data transmission. The downstream entity 49 can discard the encrypted data that the downstream entity 49 does not access. If the downstream entity 49 cannot access the data in the encrypted block, the seed is not sent to this downstream entity 49.

The drive 16 can also have basic error correction capabilities. For example, the drive may include a decoder 39 to perform on-the-fly error correction. If the decoder 39 cannot modify the data block, this data block is
Sent to 14. Such flexibility allows the use of a fast and inexpensive decoder 39 for error correction. Such flexibility also allows the host processor 14 to perform more complex and more accurate error correction.

4 to 6 show the bitwise exclusive OR operation in more detail. FIG. 4 shows a simplified version 400 of the RS-PC block. The M × N block 405 of user data is
32K bytes. The RS-PC redundant data 403 and 404 are
Associated with each row and each column of block 400. RS-P
The length of the C block 400 is 182 bytes, of which
172 bytes are the user data 405. The remaining 10 bytes are RS-PC redundant data added for error recovery.
403. The number of lines of the RS-PC block 400 is 208, and 16 lines among them contain RS-PC redundant data 404. The header 401 contains information on copy protection, especially on encryption keys. Under normal circumstances, the user receives this data and receives the header 401 or RS-PC redundant data 4
You do not need to know the contents of 03 and 404. This information is extracted and checked while the data is in the drive.
The user data of the M × N block 405 also includes a lead-in area (not shown) including confidential data.

Referring to FIG. 5, row 501 of the RS-PC block includes 10 bytes of RS-PC redundant data generated from the user data in row 501 and 172 bytes of user data. The encryption mask in row 502 includes a 172-byte random number and 10-byte RS-PC redundant data generated from the 172-byte random number in row 502. Two rows 501 and 502
Are ORed bit-by-bit together to form the encrypted block of row 504. The encrypted block in line 504 is the 172 bytes of encrypted data and
Includes 10 bytes of redundant data to provide a valid RS-PC codeword for 172 bytes of encrypted data. Decryption is performed by XORing the encrypted block in row 504 with the encryption mask in row 502.

The exclusive OR operation can be extended bit by bit so as to cover all blocks. The length of the seed stored in the ROM 26 for the first pseudorandom number generator 24 is long enough to secure the required encryption strength.
After a 32K byte random number is generated, the associated RS-P
C redundant data is calculated to complete the encryption mask. Since calculating RS-PC redundant data is relatively trivial, little processing power is required to calculate RS-PC redundant data.

As a result of the above-described operation, the error correction capability of the RS-PC codeword is maintained. Referring to FIG. 6, due to noise and defects in the storage medium, the original RS-
An error is scattered throughout the PC block 602. This error is indicated by a dot. The encryption mask 601 does not contain any errors. Encryption mask 601 and RS-PC block 602
XORing maintains the integrity of the error correction capability. Therefore, the encrypted data block 603 is
Including the error in the same location as RS-PC block 602, all RS-PC codewords are aligned so that error correction can be performed successfully. Encryption mask 60
In the unlikely event that there is an error, the error can still be corrected and the encryption and subsequent error correction will be satisfactory.

The processing power required for the pseudo-random number generators 24, 42 and the RS-PC encoder 28 is negligible compared to the processing power required to perform error code correction.
Therefore, according to the present invention, a greater burden is removed from performing the error code correction, and the DVD-ROM
The drive 16 and the DVD decoder card 36 only have a small burden. Error code correction is DVD-RO
It can be distributed to the M drive 16 and the host processor 14, or can be entirely delegated to the host processor 14.

The basic steps of the present invention are as follows: 1) A seed is provided. The length of the seed is long enough to ensure the required encryption strength.

2) One block of random numbers is generated by a pseudo-random number generator, which is seeded or initialized by a seed.

3) Error correction code words are generated based on the same error correction code generation scheme used for the RS-PC blocks stored on the storage medium. In this way, a series of codewords are generated, all of which are determined by the random number seed and are consistent with the original blocks stored on the storage medium. The result is an encryption mask.

4) Bitwise exclusive OR is performed between the original RS-PC block and the encryption mask.

5) The block resulting from the bitwise exclusive OR operation also contains a valid codeword containing any errors contained in the codeword read from the storage medium. No additional errors occur because the encryption mask contains no errors. The block resulting from the bitwise exclusive OR operation is effectively encrypted and transmitted to the host processor or other processing entity for error correction without the risk of unauthorized copying of the original data 6) Error code correction is performed by the host processor. The error has been corrected, but the block still encrypted is sent downstream of the host processor without the danger of unauthorized copying of the original data.

7) If the decryption is performed by a trusted entity downstream of the host processor (eg, an MPEG decoder), only the seed needs to be transferred to the trusted entity. The seeds can be transferred in a secure manner using keys that are authenticated and exchanged based on standard techniques. The trusted entity then generates a decryption mask using the same random number pattern used by the encryption mask for encrypting the user data. The decryption mask is bitwise XORed with the user data of the error-corrected but still encrypted data block. As a result, the M × N block is decrypted, and user data with the corrected error code is generated.

8) If an entity downstream of the host processor does not decrypt the block, the seed is not transferred to this entity. Similarly, if an entity downstream of the host processor cannot access the data in the block, no seed is sent to this entity.

So far, the invention has been described with reference to encryption of the entire RS-PC block. However, RS
-A situation may arise where it is not necessary to encrypt the entire PC block. It may be necessary to encrypt only part of the RS-PC block. For example, a part of the attraction area may include confidential data related to encryption. However, the first byte of the 172 × 192 block of user data (ie, the header) contains the non-sensitive address and other header information. Therefore, the bytes of the encryption mask corresponding to the header are all zeros, and the remaining bytes are pseudo-random numbers. This allows the host processor 14
Can correct the error and confirm the block address, but cannot access sensitive data (sent by the host processor to the DVD decoder card 36).
Accordingly, some portions of the RS-PC are selectively encrypted, thereby protecting the confidentiality of the data from the host processor 14 and possibly other entities 49 downstream of the host processor 14.

In another example, an EC read from a storage medium
The C block already contains the encrypted information in a certain area. Thus, data that has already been encrypted is not at risk of being exposed on the computer bus and therefore does not need to be further encrypted by the drive.
However, the ECC block also includes title key data that is confidential in the header area. Additional header information, such as addresses, is not confidential. in this case,
Only the sensitive data in the header needs to be protected. Thus, the encryption mask includes all zeros everywhere except the sensitive header data byte location (including pseudorandom numbers). This allows the host processor to erroneously correct the ECC block, verify the address, and pass on user data without gaining access to sensitive information.

FIG. 2 shows a method for selectively encrypting data in an ECC block. An ECC block is read from the storage medium (block 200). If only some data (e.g., a byte sequence) in the ECC block needs to be kept secret, the drive (e.g., a CD ROM drive or DVD drive) will send a random number corresponding to the location containing the sensitive data and zeros elsewhere. Is provided (block 202). The location of the zero in the encryption mask can be determined by convention. For example, if the header information is protected by convention, the encryption mask contains a random number in the header location and zeros elsewhere. The encryption mask also includes random number and ECC redundant data for zero.

Next, an exclusive OR is calculated for each bit of the encryption mask block and the ECC block (block 20).
Four). The resulting partially encrypted block contains a valid ECC codeword, encrypted data in the header location, and unencrypted data elsewhere.

The partially encrypted block is sent to the host processor, which performs error code correction (block 206). In addition, the host processor
Accessing unencrypted information (Block 20
8).

The error-corrected block is then sent to one or more additional entities (block 21).
0). At each entity, the random data sequence may be reused to process subsequent data, or a new random data sequence may be generated to process each data volume. Additional encryption, either in whole or in part by each additional entity, adds an additional layer of protection. This also gives
The selected entity will be able to use the selected data. The modified non-sensitive data is immediately available. The seed is not sent to entities that have not performed decryption or have access to sensitive data.

When generating an encryption mask, it is not necessary to write a zero. Instead, a random number can be provided and a redundant byte can be generated from this random number and its location. The exclusive portion of the selected portion of the ECC block and this random number and redundant byte can then be XORed.

FIG. 3 shows that the drive performs basic ECC,
4 illustrates how the host processor performs more complex error correction. The drive reads the ECC block from the storage medium and buffers the ECC block (block 300). The drive uses a buffered EC
It includes relatively simple circuitry that implements a simple error correction algorithm to identify and correct the majority of errors in the C block (block 302). If the error correction circuit cannot correct the data block, the buffered ECC
Some or all of the blocks are encrypted (block 30
4) sent to the host processor (block 306).
The host processor then executes a more complex error correction routine to recover the error (block 308). Such flexibility allows the use of fast and inexpensive error correction circuitry in the drive, which reduces the cost of the drive and improves the speed at which error correction is performed. In addition, the ability to correct errors is improved. This is especially important for long-term storage of data.

In the following, exemplary embodiments comprising combinations of various constituent elements of the present invention will be described.

1. A computer bus (12), a host processor (14) connected to said computer bus and programmed to perform error correction, means (18) for providing a block of ECC encoded data, Means for providing a mask (24, 2)
6, 28), the encryption mask and the EC of the one block.
A drive (16) including means (30) for performing a bit-wise exclusive OR of the C-encoded data, and a product in which the product of the bit-wise exclusive OR is an encrypted block; The output of the means for performing an exclusive-or is coupled to the computer bus so that the encrypted block can be sent to the host processor via the computer bus for error correction. A system that includes:

2. Said means for forming an encryption mask (24, 26, 28) means for providing a seed (26) and a pseudo-random data generator (24) for generating a series of random numbers from said seed And the first and second parts
An ECC encoder (28) for generating an encryption mask including a portion, wherein the first portion includes a random number, and wherein the second portion includes redundant data for the first portion.
The system according to paragraph.

3. A means for receiving the encrypted block from the host processor connected to the computer bus; a means for receiving the seed from the drive; and a means for receiving the seed from the drive. A second pseudo-random data generator (42) for generating a decryption mask, and means for performing an exclusive OR of the decryption mask and a second bit of user data in the encrypted block (46)
3. The system of claim 2, wherein the second bitwise exclusive OR product provides unencrypted user data.

4. The drive (16) is a DVD-RO
M drive, and the DVD decoder card (36) includes an MPEG decoder (48), the means (37) for receiving the encrypted block, and the means (40) for receiving the seed. ), The second pseudo-random data generator (42), and the means (46) for performing an exclusive OR of the second bits.
A system according to claim 3, wherein a PEG decoder is coupled to the output of said means (46) for performing an exclusive OR of said second bits.

5. The ECC block includes a first part for user data and a second part for redundant data, and the encryption mask includes a third part and a fourth part corresponding to the first part and the second part of the ECC block, respectively. The system of claim 1, comprising:

6. The system of claim 5, wherein the third portion is filled with a plurality of random numbers, and wherein the fourth portion includes redundant data originating from the third portion.

7. The system of claim 5, wherein the third portion is selectively filled with random numbers and zeros, and wherein the fourth portion includes redundant data originating from the third portion.

8. The system of claim 1, wherein the ECC block is coded by an error correction method, and wherein the encryption mask is coded by the same error correction method.

9. The drive (16) further comprises means (39) for performing error correction, and also the host processor (14) performs error correction on the encrypted data transmitted by the drive. System.

[0059]

Thus, the invention has been disclosed for encrypting ECC encoded data without affecting the integrity of the ECC codeword. According to the present invention, the error code of the encrypted data can be corrected by the host processor and then decrypted. Then, when the host processor corrects the error code, the cost of the storage device can be reduced by reducing the expensive ECC circuit and the static RAM.

Another advantage of performing ECC on the host processor is that, unlike hardware, the host processor
The flexibility to use different ECC routines. Hardware circuits are usually limited to using the same ECC algorithm or set of algorithms for all situations, but the host processor can use different algorithms. For example, the host processor may change E without changing (ie, modifying) any data.
The entire CC block can be analyzed and the best strategy can then be determined to avoid correction errors. Miscorrection of data can be a problem, especially during on-the-fly processing. Hardware RS-PC decoders typically perform error code correction on the fly and may erroneously correct data, thereby increasing the number of errors in a data block. Miscorrections further increase the likelihood that a block will become uncorrectable. According to the more flexible approach employed by the host processor, this problem can be avoided by analyzing the data and error patterns before making any changes to the data blocks.

Another advantage is that encryption and decryption, in particular,
This is done by sending a minimum amount of sensitive information, the seed, over the computer bus.
The encryption mask is not exposed on the bus. Drive manufacturers of drives such as DVD-ROM drives typically sell decoder cards as well, so that the drive manufacturer can specify the same pseudo-random number generator that matches the drive and decoder card.

The host processor can perform error code correction without accessing the encrypted data. Alternatively, selective encryption can be performed, in which case the host processor accesses only the selected information. The modified non-sensitive data is immediately accessible for use.

Although the invention has been described with reference to a DVD-ROM drive, the invention is not so limited. The invention is particularly applicable when forward error correction is required or when it is not practical for the transmitting side to retransmit the data. Data storage devices other than DVD players include CD players and digital data storage (DD).
S) Player and digital video cassette (DV
C) A player is included. Other applications include space communication devices and mobile communication devices. Therefore ECC
The block source is not limited to a ROM drive.

The specific embodiment of the present invention has been described above.
Illustrated. However, the invention is not limited to the specific forms and arrangements of parts described and illustrated. For example, according to the present invention, error correction methods other than Reed-Solomon product codes can be used. this is,
Of course, it depends on the encryption method used for the data stored in the storage medium.

Instead of generating the seed and encryption mask, the DVD-ROM drive can access the a priori encryption mask from ROM. The DVD decoder card also accesses the encryption mask from the ROM. In addition to reducing processing power, in this embodiment, the DV
There is no need for the D-ROM drive to pass the seed to the DVD decoder card.

Accordingly, the present invention is not limited to the specific embodiments described and illustrated above. Instead, the invention is construed according to the claims that follow.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of various components of a computer system according to the present invention.

FIG. 2 is a flowchart of a method for performing error code correction and data encryption according to the present invention.

FIG. 3 is a flowchart of an alternative method for performing error code correction and data encryption according to the present invention.

FIG. 4 is a diagram showing a simplified layout of an RS-PC block.

FIG. 5 is a diagram illustrating a bit-by-bit exclusive OR operation performed by the computer system.

FIG. 6 illustrates an RS-PC block, an encryption mask, and an RS-
It is a block diagram which shows the product of the exclusive OR for every bit of a PC block and an encryption mask.

[Explanation of symbols]

 10 Computer system 12 Bus 14 Host processor 16 Driver 36 Decoder

Claims (1)

[Claims] 1. A computer bus (12), a host processor (14) connected to said computer bus and programmed to perform error correction, and means for providing a block of ECC encoded data (1). (18), means for providing an encryption mask (24, 26, 28), and means (30) for performing a bitwise exclusive OR of the encryption mask and the one block of ECC encoded data. ) And including drives (16)
And the product of the bitwise exclusive OR is an encrypted block, the output of the means for performing the bitwise exclusive OR is coupled to the computer bus,
Whereby the encrypted blocks can be transmitted to the host processor via the computer bus for error correction.