JP2000040377A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable securing read-out signal voltage being more large by applying voltage as higher as possible to a ferroelectric capacitor and increasing residual polarization in a ferroelectric memory. SOLUTION: Voltage Vpl of a selection plate line PL is set higher than a power source voltage Vcc to obtain higher read signal voltage. In such a case, Vcc is applied to a ferroelectric capacitor fro which inverting write is performed and -Vpl is applied to a ferroelectric capacitor for which non- inverting write is performed. In order to realize such operation, a plate line driving circuit PLD and a VPl generating circuit VPLG which drive the plate line PL with higher voltage than power source voltage are provided. This VPl can be generated by an internal boosting power source circuit of a charge pumping circuit and the like or a self-boosting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device using a ferroelectric thin film, and more particularly to a ferroelectric memory device utilizing dielectric polarization inversion.

[0002]

2. Description of the Related Art A nonvolatile memory device using a ferroelectric (ferroelectric random access memory, F
An eRAM (hereinafter referred to as a ferroelectric memory) performs non-volatile storage in the direction of remanent polarization of a ferroelectric capacitor. In particular, in a 2T / 2C ferroelectric memory, one memory cell is composed of two ferroelectric capacitors and two MOS transistors, and the two ferroelectric capacitors are polarized in directions opposite to each other. One-bit information is stored.

For example, the configuration of a 2T / 2C type ferroelectric memory described in Japanese Patent Application Laid-Open No. 63-201998 is as shown in FIG. The memory cells MC arranged in an array at each intersection of the positive / negative bit line pair (BLT and BLN) and the word line WL are formed by two ferroelectric capacitors FC1 and FC2 and two MOS transistors T1 and T2, respectively. Be composed. Memory cells MC forming one word, which is a unit of read and write access of storage data, are arranged on the same word line (WL). Also, each bit line pair is associated with a particular bit of the word.

The two ferroelectrics FC1 and F of the memory cell
One electrode of each of C2 is connected to transistors T1 and T2.
Are connected to a pair of a positive bit line (BLT) and a negative bit line (BLN). The other electrode is commonly connected to a plate line (PL). The gates of the two transistors T1 and T2 are connected to one word line (W
L). The word line is normally at 0 V, and Vwl is selectively applied during operation. The plate line is also usually at 0 V, and a pulse of the power supply voltage Vcc is applied during operation.

During standby, the positive and negative bit lines BLT and BLN are precharged to 0 V via the MOS transistors T3 and T4 by setting the bit line precharge signal PBL to the power supply voltage Vcc. The latch type sense amplifier SA changes the sense amplifier activation signal SAP from 0V to Vc.
By raising the potential to c, the small potential difference between the pair of positive and negative bit lines BLT and BLN is amplified, and the operation is performed such that the side showing the lower potential is set to 0 V and the side showing the higher potential is set to Vcc.

A bit line pair constituting one word is represented by Y
Via a switch circuit YSW, it is selectively connected to a positive / negative data line pair DLT and DLN which are associated one-to-one with bits constituting a word. Y switch circuit YSW
Means that only when the Y switch activation signal YSWE is at Vcc,
A specified bit line pair and a data line pair are directly connected.
A complementary input of the data amplifier DA and a complementary output of the write buffer WB are connected to each data line pair. The data amplifier DA amplifies the data appearing on the data line pair and outputs the amplified data to the outside as an output DO.

The write buffer WB guides externally applied data DI to the data line pair DLT and DLN when the write activation signal WE is at Vcc. In particular, when the Y switch circuit YSW is active and the sense amplifier SA is active, the data DI externally applied is latched to the latch type sense amplifier SA connected to the data line pair via the Y switch circuit YSW.

In the ferroelectric memory having such a configuration, the read operation is performed as follows. First, the bit line precharge signal PBL is lowered from Vcc to 0V, and the bit lines BLT and BLN are floated at 0V. Next, only one word line WL for selecting a desired word is set to Vwl. Further, when the plate line PL is raised from 0V to Vcc,
A voltage is applied to the ferroelectric capacitors FC1 and FC2 of all the cells MC on the selected word line WL. Due to this voltage, one ferroelectric capacitor undergoes polarization inversion, a large amount of charge is supplied from the capacitor, and the voltage on the bit line increases, while the other capacitor does not undergo polarization inversion, and the voltage on the bit line decreases compared to that. .

Here, it is assumed that the positive bit line BLT has a higher voltage than the negative bit line BLN for easy understanding. The difference between the positive and negative bit line voltages that appear in this way is
The sense amplifier SA is activated and amplified by the sense amplifier activation signal SAP. After the amplification, the positive bit line BLT showing a high voltage becomes Vcc, while the negative bit line BLN showing a low voltage becomes 0V.

After amplification by the sense amplifier SA, the Y switch activation signal YSWE is activated,
A desired bit line pair (BL) is connected via a switch circuit YSW.
T, BLN) to the data line pair (DLT, DLN). Finally, the signal appearing on the data line pair is amplified by the data amplifier (DA) and data (DO) is output. Here, since the positive data line has a higher voltage, the output data is “1”.

After reading the data, the voltage on the plate line PL becomes high in both of the two ferroelectric capacitors, and if the voltage at both ends of the capacitors is kept at 0 V, the directions of the remanent polarization are aligned. In order to read the same data in the next access, it is necessary to write back the data again (write back). In this conventional ferroelectric memory, write-back is performed as follows.

First, while the sense amplifier SA is being activated, the plate line is lowered from Vcc to 0 V, then the sense amplifier is deactivated, and the bit line precharge signal PBL is set to 0.
From V to Vcc, both bit lines are set to 0V. Finally, the word line is set to 0 V to disconnect the ferroelectric capacitor from the bit line. Before the plate line is pulled down, the ferroelectric capacitor that did not undergo polarization inversion at the time of reading is set to 0 on the bit line side.
V, Vcc is applied to the plate line side. On the other hand, when the plate line is pulled down, Vcc is applied to the bit line side and 0 V is applied to the plate line side for the ferroelectric capacitor whose polarization has been inverted at the time of reading. This write-back operation guarantees that the same data is read in the next read.

In such a ferroelectric memory, externally applied input data (DI) is written to an arbitrary word during a write operation as follows. First, since the ferroelectric memory is a destructive read, in order to protect the storage data of the cell sharing the word line with the desired word, the storage data of the cell on the word line is written in the same procedure as the read operation described above. Amplify / latch by sense amplifier.

Next, the Y switch circuit is activated with the input data being guided to the data line pair by the write buffer. At this time, by selectively connecting the bit line pair to the data line pair by the Y switch circuit, the input data is latched in the sense amplifier corresponding to the write target word without disturbing the data of the other sense amplifiers. After that, the plate line is turned off, the bit line is precharged to 0 V, and the word line is turned off in the same procedure as the write-back described above.

[0015]

In order to increase the capacity of a ferroelectric memory, it is essential to make the ferroelectric capacity finer and to lower the power supply voltage accordingly. At this time, the signal voltage appearing on the bit line pair at the time of reading becomes small, and it becomes difficult to secure a sufficient operation margin.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of securing a larger read signal voltage by setting a selection voltage of a plate line higher than a power supply voltage.

[0017]

According to the present invention, one terminal of each of two ferroelectric capacitors is connected to positive and negative bit lines via two transistors, and the other terminal is connected to a common plate line. , And a memory cell configured by connecting the gate terminals of two transistors to a common word line is arranged in a matrix at each intersection of the positive and negative bit lines and the word line, and the bit line voltage amplified by the sense amplifier Is a non-volatile semiconductor memory device having a first voltage higher than a ground potential or a ground potential, and performing a pulse drive of the plate line with a second voltage higher than the first voltage during a read and a write operation. As a result, a nonvolatile semiconductor memory device having the feature is obtained.

According to the present invention, one terminal of one ferroelectric capacitor is connected to a bit line via one transistor, the other terminal is connected to a plate line, and the gate terminal of the transistor is connected to a word line. The memory cells connected to the lines are arranged in a matrix at each intersection of the bit lines and the word lines, and the bit line voltage amplified by the sense amplifier becomes the ground potential or the first voltage higher than the ground potential. A nonvolatile semiconductor memory device, wherein the plate line is pulse-driven at a second voltage higher than the first voltage at the time of read and write operations.

The internal power supply having the second voltage is generated from the power supply having the first voltage by using a booster power supply circuit, and the internal power supply having the second voltage is generated by using a self-boot circuit. The plate line is driven by the.

Further, during a write-back operation in a read operation, the potential of the plate line is maintained higher than the potential of the bit line. In the write-back operation, the potential of the plate line is maintained at the second voltage. It is characterized by being driven by.

The operation of the present invention will be described. In the present invention, in order to obtain a higher read signal voltage, the voltage of the selected plate line is set higher than the power supply voltage. Here, the plate line voltage is Vpl (> Vcc). In this case, the power supply voltage Vcc is applied to the ferroelectric capacitor subjected to inversion writing, and -Vpl is applied to the ferroelectric capacitor subjected to non-inversion writing. In order to realize such an operation, a plate line driving circuit that drives the plate line at a voltage (Vpl) higher than the power supply voltage is provided. Vpl can be generated by an internal boosting power supply circuit such as a charge pumping circuit or a self-boot circuit.

In the ferroelectric memory of the present invention, the plate line is driven at a higher voltage Vpl than in the conventional ferroelectric memory in which the plate line is driven at the same power supply voltage Vcc as the bit line. For this reason, the voltage applied to the ferroelectric capacitor at the time of writing is lower than the conventional Vcc / −Vcc by Vcc / −Vcc.
−Vpl and larger. Accordingly, remnant polarization for retaining data also increases, and the signal voltage appearing on the bit line at the time of reading increases, which is effective in ensuring high reliability of the reading / writing operation, particularly in securing an operation margin when the power supply voltage is low.

Further, in the present invention, overhead occurs in terms of circuit scale and power consumption as compared with the conventional ferroelectric memory, but the merit of improving the reliability is considered to be much greater. Further, it is conceivable to use Vcc itself as an internal boosted power supply higher than the external power supply voltage. However, in this case, it is not practical because the power of the sense amplifier and the like must be supplied by the internal boosted circuit.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows 2T / 2 according to the present invention.
FIG. 6 is a diagram showing an embodiment of a C-type ferroelectric memory, and portions equivalent to those in FIG. 5 are denoted by the same reference numerals. The configuration of the present embodiment is different from the conventional 2T / 2C type ferroelectric memory of FIG. 5 in that a Vpl generating circuit VPLG for generating a high plate line selection potential Vpl from a power supply voltage Vcc is provided. And the plate line driving circuit PLD uses the plate line P
L is driven. The other configuration is the same as that of FIG. 5, and the description thereof will be omitted.

FIGS. 2 to 4 show the operation of the embodiment of the present invention. The operation will be described with reference to these drawings. FIG.
3 shows an example of a signal waveform of each part of the circuit of FIG. 1, and FIG. 3 is a diagram showing polarization characteristics (on the QV plane) of the ferroelectric capacitor. FIG. 4 shows the locus of the ferroelectric capacitor constituting the ferroelectric memory according to the embodiment of the present invention traced at the time of reading.
(A) is a locus of a ferroelectric capacitor connected to the bit line on the side showing a higher voltage in the bit line pair, and (B) is a plot of the bit line pair. 5 shows the locus of the ferroelectric capacitor connected to the bit line on the side showing the lower voltage.

In this ferroelectric memory, the read operation is performed as follows. First, the bit line precharge signal PB
L is reduced from the power supply voltage Vcc to 0V, and all bit lines are set to 0V.
And floating. Next, only one word line for selecting a desired word is set to Vwl. Further, the plate line P
When L rises from 0 V to Vpl, a voltage is applied to the ferroelectric capacitors of all cells on the selected word line.

With this voltage, one of the ferroelectric capacitors undergoes polarization reversal, a large amount of charge is supplied from the capacitors, and the voltage of the bit line and the terminal of the sense amplifier SA connected thereto increases, while the other capacitor is There is no polarization inversion, and the bit line is lower than that (timing a in FIG. 2). Here, for ease of understanding, one bit line BL of the bit line pair
Assume that T indicates a higher voltage than the other bit line BLN.

The bit line voltage difference appearing in this manner is activated and amplified by the sense amplifier SA (timing b in FIG. 2). After amplification, the BLT showing the high voltage is Vcc
On the other hand, BLN indicating a low voltage becomes 0V.
After amplification by the sense amplifier SA, the desired bit line pair (BLT, BLN) is connected to the data line pair (DLT, DLN) via the Y switch circuit YSW at the timing when the Y switch activation signal YSWE is activated ( Timing c) in FIG. Finally, the signal appearing on the data line pair is amplified by the data amplifier DA.

After reading the data, write back is performed. With the sense amplifier activated, the plate line PL
Is lowered from Vpl to 0 V (timing d in FIG. 2), then the sense amplifier is deactivated, and the bit line precharge signal P
BL is raised from 0 V to Vcc, and both bit lines are set to 0 V (timing e in FIG. 2). Finally, the word line is set to 0 V to disconnect the ferroelectric capacitor from the bit line (timing f in FIG. 2). Before the plate line PL is pulled down, the ferroelectric capacitor whose polarization has been inverted at the time of reading
Vpl and Vpl are applied to the plate line side, respectively. This capacitance becomes 0 V at both ends when the plate line is lowered to 0 V, and maintains the remanent polarization at the point B on the QV plane shown in FIG.

On the other hand, when the plate line is pulled down, Vcc is applied to the bit line side, and 0 V is applied to the plate line PL side, for the ferroelectric capacitor whose polarization was not inverted at the time of reading. This capacitance becomes 0 V at both ends when the bit line is lowered to 0 V, and maintains the residual polarization at the point A on the QV plane shown in FIG. FIG. 4 shows the locus on the QV plane of the ferroelectric capacitor at each of the timings a to f during the read operation.

When the plate line rises, the capacitance which causes the polarization inversion in reading shows the bit line voltage Vbl1 on the bit line,
Vcc is applied during write back. On the other hand, the capacitance that does not cause polarization inversion in reading is the bit line voltage V lower than Vbl1.
bl0, and -Vpl is applied during write-back.

In this ferroelectric memory, externally applied input data DI is written to an arbitrary word during a write operation as follows. First, since the ferroelectric memory is a destructive read, it is necessary to protect data stored in a cell sharing a word line with a desired word. Therefore, at this time, in the same procedure as the read operation described above,
The storage data of the cell on the word line is amplified / latched by the sense amplifier SA.

Next, the Y switch circuit YSW is activated with the input data being guided to the data line pair by the write buffer WB. By selectively connecting the sense amplifier of the word to the data line pair by the Y switch circuit, the input data is latched in the sense amplifier corresponding to the word to be written without disturbing the data of the other sense amplifiers. After that, the plate line is turned off, the bit line is precharged to 0 V, and the word line is turned off in the same procedure as the write-back described above.

By the operation described above, 2T /
In the 2C ferroelectric memory, Vcc or -Vpl is applied to the ferroelectric capacitor at the time of write-back after reading or at the time of writing data. In this embodiment, Vpl is V
Although described as an internal power supply generated by the boost power supply circuit from cc, the same effect can be obtained by driving the plate line PL at a voltage higher than the power supply voltage by the self-boot circuit without using the boost internal power supply. Needless to say.

In this embodiment, the configuration of the memory cell is 2
Although described as a T / 2C type, it goes without saying that the same effect can be obtained by the plate line driving method of the present invention even when a 1T / 1C type memory cell is used.

[0036]

As described above, according to the present invention,
In a 2T / 2C-type or 1T / 1C-type ferroelectric memory, by applying a voltage higher than a power supply voltage to a ferroelectric capacitor at the time of write-back or writing, remnant polarization during data retention is increased. There is an effect that operation at a lower power supply voltage becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing waveform examples of respective parts showing the operation of the embodiment of the present invention at the time of read and write back operations.

FIG. 3 is a diagram showing polarization characteristics of a ferroelectric capacitor.

FIG. 4 is a diagram showing, on a QV plane, a locus that a ferroelectric capacitor constituting the ferroelectric memory of the present invention traces at the time of reading.

FIG. 5 is a circuit diagram showing a conventional 2T / 2C ferroelectric memory.

[Explanation of symbols]

 BLT, BLN bit line pair DA data amplifier DLT, DLN data line pair DO, DI data FC1, FC2 ferroelectric capacitor MC memory cell PBL bit line precharge signal PL plate line PLD plate line drive circuit PLE plate line activation signal SA Sense amplifier SAP Sense amplifier activation signal T1, T2 Memory cell transistor T3, T4 Bit line precharge transistor VPLG Vpl generation circuit WB Write buffer WE Write activation signal WL Word line YSW Y switch circuit YSWE Y switch activation signal

Claims (6)

[Claims] 1. One terminal of each of two ferroelectric capacitors is connected to a positive / negative bit line via two transistors, the other terminal is connected to a common plate line, and the gate terminals of the two transistors are connected. Are arranged in a matrix at each intersection of the positive and negative bit lines and the word line, and the bit line voltage amplified by the sense amplifier is ground potential or higher than the ground potential. A non-volatile semiconductor memory device, wherein the plate line is pulse-driven at a second voltage higher than the first voltage during read and write operations. 2. A structure in which one terminal of one ferroelectric capacitor is connected to a bit line via one transistor, the other terminal is connected to a plate line, and the gate terminal of the transistor is connected to a word line. Memory cells are arranged in a matrix at each intersection of a bit line and a word line, and the bit line voltage amplified by the sense amplifier becomes a ground potential or a first voltage higher than the ground potential. A nonvolatile semiconductor memory device for performing pulse driving of the plate line at a second voltage higher than the first voltage during read and write operations. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the internal power supply having the second voltage is generated from the power supply having the first voltage by using a boost power supply circuit. . 4. The nonvolatile semiconductor memory device according to claim 1, wherein the plate line is driven by the second voltage using a self-boot circuit. 5. The nonvolatile semiconductor memory device according to claim 1, wherein a potential of said plate line is maintained higher than a potential of said bit line during a write-back operation in a read operation. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said plate line is driven by said second voltage during said write-back operation.