JP2000031757A - Constant current circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit excellent in output characteristics at a low voltage by connecting one end of the column of serially connected MIS transistors to a power source or the ground, making another end as an output terminal and controlling the gates of the respective transistors. SOLUTION: A P channel transistor 301 is connected to the power source 1, the source of the transistor 302 is connected to the drain of the transistor 301 and the drain is connected to the output terminal 9. The drain of the transistor 305 is connected to the power source 1 and the gate is connected to its own drain and a current source 5. The transistors 303-305 constitute a control circuit. The transistors 305 and 304 are operated in a saturated area and the transistor 303 is operated in a non-saturated area. The transistors 301 and 302 for receiving the voltage are respectively operated in the non-saturated area and the saturated area. Especially since the transistor 302 is operated in the saturated area, the dependency to a power supply voltage of the output terminal 9 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit technology and relates to a configuration of a constant current circuit.

[0002]

2. Description of the Related Art A constant current circuit comprising a MOS transistor has conventionally been constructed using the saturation characteristics of a MOS transistor. FIG. 27 shows this conventional circuit configuration.

[0003] 1 is a power supply, and 0 is a ground. 5 is the current source. Reference numerals 2701 to 2704 denote P-channel transistors. P-channel transistors 2703, 2 connected in series
In 704, each gate is connected to its own drain. Therefore, the transistor operates in a saturation region. Since the same current flows through the P-channel transistors 2703 and 2704, the current source 5 generates a voltage when operating in the saturation region at the drain, that is, the gate of each transistor. P-channel transistors 2701 and 2702 whose gates are connected to each other receive the voltage generated by the P-channel transistors 2703 and 2704 at their gates. A constant current is output under the condition that the voltage of the output terminal 9 is close to the ground potential and the P-channel transistor 2501 operates in the saturation region. This is a conventional constant current circuit.

[0004]

In order to obtain a constant current by the above-described configuration, a condition for a constant current is required.
Let's qualitatively consider the conditions for establishing the constant current characteristics. To operate with constant current characteristics, a P-channel transistor 2
It is necessary to operate 701 and 2702 in the saturation region. The voltage V9 of the output terminal 9 at that time is as follows: V9 = VDD−2 ・ {√ (2 · I0 / βP) + VTP} −VTP. Here, VDD indicates the voltage of the power supply 1. I0 is the current flowing through the current source 5, βP is the P-channel transistor 2701
To 2704 indicate the current driving capability. VTP indicates a threshold voltage of the P-channel transistors 2701 to 2704.

[0005] Ideally, a P-channel transistor 270
Both 1 and 2702 need to operate in the saturation region, but only the P-channel transistor 2701 exhibits a constant current characteristic in the operation in the saturation region. When the P-channel transistor 2701 operates in the saturation region, the voltage V9 at the output terminal 9 is as follows: V9 = VDD-2 ・ {√ (22I0 / βP) + VTP} -VTP-√ {VTP / β
P) + VTP}, and the constant current characteristic cannot be maintained below the voltage V9 of the output terminal 9.

Further, P-channel transistors 2703 and 2704
Considering a circuit that generates the gate voltage of the P-channel transistors, current needs to flow through the P-channel transistors 2703 and 2704. This requires a P-channel transistor 270
3, current must flow through 2704, so taking the P-channel transistor 2703, power supply 1 and node 2793
Must be equal to or higher than the threshold voltage of the P-channel transistor 2703. Similarly, the potential difference between node 2793 and node 2794 is
Must be greater than or equal to the threshold voltage. Therefore, the potential difference between the power supply 1 and the node 2794 must satisfy the following relationship: (potential difference between the power supply 1 and the node 2594)> 2 · VTP. Here, the back gate voltage of the P-channel transistor 2704 is not considered. When the potential of the substrate of the P-channel transistor 2504 is different from the potential of the source, a back gate effect is added, and a voltage of 2 · VTP or more is actually required.

For this reason, the power supply voltage must be at least equal to the potential difference between power supply 1 and node 2794. Conversely, it will not operate at a power supply voltage lower than this.

[0008] In recent years, a constant voltage operation has been required as a performance required for an IC. Therefore, as long as the conventional configuration is employed, it has been very difficult to configure a constant current circuit with low power supply voltage dependence at a low power supply voltage.

[0009]

According to the present invention, there is provided a constant current circuit comprising:
In order to solve such a problem and to realize a circuit in which the current driving capability of the transistor can be easily set and the output characteristics are good at a low voltage, (1) a constant current circuit including a plurality of MIS transistors and a current source , The MIS transistor of the first conductivity type is n
(N is a natural number) connected in series, one end of the series-connected MIS transistor row is connected to a power supply or a ground, the other end is an output terminal, and a control circuit and a current source are connected between the power supply and the ground. Connected in series, the control circuit has n outputs, the n outputs of the control circuit are respectively connected to the gates of the n MIS transistors connected in series, and the control circuit has a power supply voltage and the current Depending on the current value of the source,
It is characterized by controlling n gates of the MIS transistors connected in series.

(2) The series-connected MIS transistors described in (1) are composed of two transistors. The control circuit described in (1) has a source connected to a power supply or a ground, and a gate and a drain connected to a first node. A connected first MIS transistor of the first conductivity type, a first current source that is provided between the first node and ground or a power supply, and that flows a constant current in the direction of ground or a power supply. A second MI of the first conductivity type connected to ground and the gate connected to the second node
An S transistor, a third MIS transistor of a first conductivity type having a source connected to the drain of the second MIS transistor, and a gate connected to the first node; and a ground or power supply connected to the second node. And a second current source that flows a constant current value in the direction of the ground or the power supply, and the second node is connected to the power supply of the MIS transistor connected in series or the gate of the MIS transistor connected to the ground. The first node is connected to a gate of an MIS transistor connected to an output terminal of the MIS transistor connected in series, and the current driving capability of the MIS transistor connected in series is the same, The current values of the one current source and the second current source are the same, the current drive capabilities of the second and third MIS transistors are the same, and the first MIS transistor has the same current drive capability. The current driving capability of the second MIS transistor is twice the current driving capability of the transistor, or the current driving capability of the second and third MIS transistors is the same, and
More than twice the current drive capability of the MIS transistor
The threshold voltage of the first MIS transistor is four times or less, and the effective gate voltage of the first MIS transistor is larger than one half of the threshold voltage of the first MIS transistor.

(3) In the configuration described in (2), the first, second,
The current drive capability of the third MIS transistor is the same,
With respect to the current value of the first current source, the current value of the second current source is half, or the current value of the first current source is the second current source. That the current value of the first MIS transistor is greater than or equal to one-fourth, less than one-half, and that the effective gate voltage of the first MIS transistor is greater than one-half the threshold voltage of the first MIS transistor. Features.

(4) The series-connected MIS transistors described in (1) are composed of n + 2 transistors. The control circuit described in (1) connects the source to the power supply or the ground, and connects the gate and the drain to the first. A first MIS transistor of the first conductivity type connected to the node, a first current source installed between the first node and ground or a power supply, and a constant current flowing in the direction of the ground or the power supply; A second MIS transistor of a first conductivity type connected to the power supply or the ground, a gate connected to a second node, a source connected to a drain of the second MIS transistor, and a gate connected to the first MIS transistor; A third MIS transistor of the first conductivity type connected to the first node and the gate and the drain are connected to the (m + 2) th node (m is 1 or more).
n less than or equal to n), the source connected to the m + 3rd MIS transistor of the first conductivity type connected to the drain of the (m + 1) MIS transistor n in series, the n + A second current source installed between the second node and the ground or the power supply and flowing a constant current value in the direction of the ground or the power supply, and the second node is connected to the power supply or the ground of the MIS transistor connected in series. Connected to the gate of the connected MIS transistor, the first node was connected in series to the
Connected to the gate of the MIS transistor connected to the output terminal of the MIS transistor, and the (m + 2) th node is connected to the gate of the (m + 2) th MIS transistor counted from the power supply or the ground of the MIS transistor connected in series. In the configuration in which the current driving capabilities of the MIS transistors connected in series are the same, the current values of the first current source and the second current source are the same, and the current values of the second and third MIS transistors are the same. The driving capability is the same, and is twice as large as the current driving capability of the first MIS transistor, or the current driving capability of the second to m + 3 MIS transistors is the same, and The current driving capability of the first MIS transistor is more than 2 times and 4 times or less, and the effective gate of the first MIS transistor is more than half the threshold voltage of the first MIS transistor. Electric Constant current circuit, characterized in that large.

(5) The series-connected MIS transistor according to the first aspect is constituted by three, and the control circuit according to the first aspect connects the source to the power supply or the ground, and connects the gate and the drain to the third node. First MIS of first conductivity type connected
A transistor, a first MIS transistor of a first conductivity type having a source connected to a third node, a gate and a drain connected to the first node, and a transistor provided between the first node and ground or a power supply. A first current source flowing a constant current in the direction of ground or power supply, a second MIS transistor of a first conductivity type having a source connected to the power supply or ground and a gate connected to the second node, and a source. Is connected to the drain of the second MIS transistor, a fourth MIS transistor of the first conductivity type having a gate and a drain connected to a fourth node, and a source connected to the fourth node. A third MIS transistor of the first conductivity type connected to the first node, and a third MIS transistor disposed between the second node and a ground or a power supply, and flowing a constant current value in the direction of the ground or the power supply. A flow source, the second node is connected to a power supply of the MIS transistor connected in series or a gate of an MIS transistor connected to ground, and the fourth node is a second power supply or ground connected to the ground. The first node is connected to the gate of the MIS transistor connected to the output terminal of the MIS transistor connected in series, and the current driving capability of the MIS transistor connected in series is the same. In one configuration, the current values of the first current source and the second current source are the same, and the current drive capability of the third MIS transistor is larger than that of the other MIS transistors, and the current value of the fourth MIS transistor is larger than that of the fourth MIS transistor. The current driving capability is the same as that of the MIS transistors connected in series.

(6) In (1) to (5), the circuit in which the MIS transistor is connected to the power supply is characterized in that the first conductivity type MIS transistor is constituted by a P-channel MOS transistor. Current circuit.

(7) In (1) to (5), the circuit in which the MIS transistor is connected to the ground is the first conductive type MI.
The S transistor is configured by an N-channel MOS transistor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to specific embodiments of the present invention.

FIG. 1 is a block diagram of a constant current circuit according to the present invention. 1 indicates power, 0 indicates ground. Reference numeral 5 denotes a constant current circuit, which is connected to the ground 0. Also 10
1, 102 and 103 indicate MIS transistors of a certain conductivity type, and 10
A plurality of MIS transistors may be connected from 2 to 103. Reference numeral 104 denotes a control circuit, and the MIS transistor 10
A voltage is supplied to the gates of 1, 102 and 103.

When a constant current flows from the control circuit 104 by the current source 5, the control circuit 104 sets a voltage corresponding to the current value to 1
01, 102 and 103 are supplied to the gates of the MIS transistors.
This gate voltage is such that, under a certain voltage of the output terminal 9, the MIS transistor 101 operates in an unsaturated region, and
The third MIS transistor operates in the saturation region. In particular, since the MIS transistor 103 operates in the saturation region, a substantially constant current that does not depend on the power supply voltage is output from the output terminal 9 under a specific condition.

FIG. 2 is another block diagram of the constant current circuit of the present invention. In this example, the conductivity type of the MIS transistor and the connection position of the current source are changed. 1 indicates power, 0 indicates ground. Reference numeral 5 denotes a constant current circuit, which is connected to the power supply 1.
1. Reference numerals 201, 202, and 203 denote MIS transistors of a conductivity type different from that in FIG. 1, and a plurality of MIS transistors may be connected to the MIS transistor 202 or 203. A control circuit 204 supplies a voltage to the gates of the MIS transistors 201, 202, and 203.

The operation can be considered as in FIG. Control circuit 2
When a constant current flows from the current source 5 from 04, the control circuit 2
04 supplies a voltage according to the current value to the gates of the MIS transistors 201, 202, and 203. With this gate voltage, under a specific voltage of the output terminal 9, the MIS transistor 201 operates in the non-saturation region and the MIS transistor 203 operates in the saturation region. In particular, since the MIS transistor 203 operates in the saturation region, a substantially constant current that does not depend on the power supply voltage at the output terminal 9 under specific conditions is output from the output terminal 9.

FIG. 3 is a circuit diagram showing one embodiment of the present invention. The P-channel transistor 301 is connected to the power supply 1 and has a current driving capability of k · βP. The source of the P-channel transistor 302 is the P-channel transistor 30
The drain is connected to the output terminal 9. Similarly, the P-channel transistor 302 is k · βP
Current driving capability.

The drain of the P-channel transistor 305 is connected to the power supply 1, and the gate is connected to its own drain and the current source 5
And connected to node 395. The current drive capability of this P-channel transistor 305 is βP. The node 395 is connected to the current source 5, and the current value of the current source 5 is set to I0.

The source of P-channel transistor 303 is connected to power supply 1, and the gate is connected to node 394. The source of P-channel transistor 304 is connected to the drain of P-channel transistor 303 at node 393, and the gate is connected to node 395. P-channel transistor 304
Is connected to node 394, and node 394 is a current source
The current source 6 is connected to the current source 6, and the current source 6 is flowing a current having a current value of I0.

The constant current characteristic of this circuit will be described quantitatively. Here, it is assumed that the back gate voltage effect of each transistor has the same substrate potential as the transistor in order to make the operation easy to understand. The channel length modulation effect will be described later.

The P-channel transistor 305 operates in a saturation region as long as a current flows. The P-channel transistor 304 also operates in the saturation region, and the P-channel transistor 303 operates in the non-saturation region. At this time, the current value of each transistor is represented by the following equation.
Here, the back gate effect is ignored.

P-channel transistor 305 I0 = 1/2 · βP
・ (VDD-V395-VTP) P-channel transistor 303 I0 = k ・ βP ・ {(VDD-V394-VT
P) ・ (VDD-V393) -1/2 ・ (VDD-V393) ² } P-channel transistor 304 I0 = 1/2 ・ k ・ βP ・ (V393-
V395-VTP) ² Here, VDD indicates the voltage of the power supply 1. V395 indicates the voltage of the node 395, V393 indicates the voltage of the node 393, and V394 indicates the voltage of the node 394. The threshold voltage of each P-channel transistor is VTP.

From this equation, the voltage at each node is given by: VDD-V395 = √ (2 · I0 / βP) + VTP VDD-V393 = (k−√k) / k · (VDD-V395-VTP) VDD-V394 = (k ² -k ・ √k + 2√k) / {2 ・ k (k-1)} ・ (VDD-V395-VTP)
+ VTP.

In order for the P-channel transistor 303 to operate in the non-saturation region and the P-channel transistor 304 to operate in the saturation region, the following conditions must be satisfied.

P channel transistor 303 unsaturated region condition VDD-V394-VTP> VDD-V393 P channel transistor 304 saturated region condition V393-V394> (VDD-V395)-(VDD-V393) -VTP> 0 Substituting the condition, 0 <k <4 (k + √k) ・ (k-2) / {2 ・ k ・ (k-1)} <VTP / (VDD-V395-VTP) In the range, the operating conditions of the unsaturated and saturated regions of the P-channel transistors 303 and 304 are satisfied. From these conditions, it is preferable that 2 ≦ k <4 and VTP <2 · (VDD−V395−VTP). However, if K = 2, the conditions related to VTP become unnecessary. Here, it is considered appropriate to use K = 2.

The P-channel transistors 301 and 302 receiving these voltages operate in the non-saturation region and the saturation region, respectively. Especially P-channel transistor 302
Operates in the saturation region, the dependency of the output terminal 9 on the power supply voltage is reduced, and a constant current characteristic is obtained.

With the P-channel transistor 302, fluctuations in the gate and drain voltages of the P-channel transistor 301 are reduced, and the value of the current flowing through the P-channel transistor 301 is substantially constant. The fluctuation factor is affected by the channel length modulation effect of the P-channel transistor 302, but is kept substantially constant as the current value due to the cancellation effect with the P-channel transistor 301. Therefore, constant current characteristics with little voltage dependency can be obtained.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. This is a circuit in which a P-channel transistor is replaced with an N-channel transistor, and a constant current can be formed between a terminal and a power supply, not between a terminal and a ground.

The N-channel transistor 401 is connected to the ground 0
And has a current drive capability of k · βN. The source of the N-channel transistor 402 is connected to the drain of the N-channel transistor 401, and the drain is connected to the output terminal 9. Similarly, N-channel transistor 402 has a current driving capability of k · βN.

The drain of the N-channel transistor 405 is connected to the ground 0, and the gate is connected to the drain and the current source 5 and the node 495. The current drive capability of this N-channel transistor 405 is βN. The node 495 is connected to the current source 5, and the current value of the current source 5 is I0.

The source of N-channel transistor 403 is connected to ground 0, and the gate is connected to node 494. The source of N-channel transistor 404 is connected to the drain of N-channel transistor 403 at node 493, and the gate is connected to node 495. N-channel transistor
The drain of 404 is connected to the node 494, and the node 494 is connected to the current source 6, and the current source 6 flows a current at a current value of I0.

The circuit operation will be described as in the case of the P-channel transistor. The N-channel transistor 405 operates with a saturation characteristic as long as a current flows. The N-channel transistor 404 also operates in the saturation region, and the N-channel transistor 403 operates in the non-saturation region. At this time, the current value of each transistor is represented by the following equation. Here, the back gate effect is ignored.

N-channel transistor 405 I0 = 1/2 · βN · (V495-VTN) ² N-channel transistor 403 I0 = k · βN · {(V494-VTN) · V
493-1 / 2 ・ V493 ² } N-channel transistor 404 I0 = 1/2 ・ k ・ βN ・ (V495-V49
(3−VTN) ² where V495 is the voltage of node 495, V493 is the voltage of node 493, and V494 is the voltage of node 494. The threshold voltage of each N-channel transistor is VTN.

According to this equation, the voltage at each node is: V495 = √ (2 · I0 / βN) + VTN V493 = (k−√k) / k · (V495−VTN) V494 = (k ² -k · √ k + 2√k) / {2 · k (k-1)} · (V495-VTN) + VTN.

In order for the N-channel transistor 403 to operate in the non-saturation region and the N-channel transistor 404 to operate in the saturation region, the following conditions must be satisfied.

N-channel transistor 403 unsaturated region condition V494-VTN> V493 N-channel transistor 403 unsaturated region condition V494-V49
3>V495-V493-VTN> 0 Substituting the above condition, 0 <k <4 (k + √k) ・ (k-2) / {2 ・ k ・ (k-1)} <VTN / ( (V495-VTN) In the range of k where this condition is satisfied, the non-saturated and saturated region operating conditions of the N-channel transistors 403 and 404 are satisfied. From these conditions, it is preferable that 2 ≦ k <4 and VTN <2 · (V495−VTN). However, if K = 2, conditions relating to VTN become unnecessary. Here, it is considered appropriate to use K = 2.

N-channel transistors 401 and 402 receiving these voltages operate in the non-saturation region and the saturation region, respectively. Especially N-channel transistor 402
Operates in the saturation region, the dependency of the output terminal 9 on the power supply voltage is reduced, and a constant current characteristic is obtained.

With the N-channel transistor 402, fluctuations in the voltage of the gate and the drain of the N-channel transistor 401 are reduced, and the current flowing through the N-channel transistor 401 is substantially constant. The variation factor is affected by the channel length modulation effect of the N-channel transistor 402, but is kept substantially constant as the current value due to the cancellation effect with the N-channel transistor 401. Therefore, constant current characteristics with little voltage dependency can be obtained.

FIG. 5 shows a configuration in which the current sources 5 and 6 in FIG. 3 are replaced with N-channel transistors. The substrate potential of the P-channel transistor is set to be the same as the source. N-channel transistor 511 has a drain connected to node 594 and a source connected to ground 0. N-channel transistor 512 has a drain at node 59
It is connected to 5 and the source is connected to ground 0. N
Both gates of channel transistors 511 and 512 are nodes
Connected to 583. N-channel transistor 513 has a source connected to ground 0 and a drain connected to node 583. The current source 7 is connected to the power supply 1 and the node 583, and flows a current toward the node 583.

Since the N-channel transistor 513 has its gate and drain connected, it operates in a saturation region. When the current from the current source 7 flows, a voltage is generated at the node 583. N-channel transistors 511, 512, 513
Are transistors having the same current driving capability, the N-channel transistors 511 and 51 operate within the saturation region.
2 operates as a current source, and the same current as the current flowing in the current source 7 flows.

FIG. 6 shows a modification of the transistor shown in FIG. This allows a constant current to be used between the terminal and the power supply, rather than between the terminal and the ground. Also, the current source is connected to the power supply instead of the ground connection.

FIG. 7 has the same configuration as FIG. However, here, the current value of the current source 6 is not I0 but a value of I0 / k.
Further, the current driving capability of the P-channel transistors 703 and 704 is changed from k · βP to βP.

From the above, the constant current characteristic of this circuit will be quantitatively described as in FIG. As in FIG. 3, each transistor, substrate potential, and channel length modulation effect are not included in the calculation.

The P-channel transistor 705 operates with a saturation characteristic as long as a current flows. The P-channel transistor 704 also operates in the saturation region, and the P-channel transistor 703 operates in the non-saturation region. At this time, the current value of each transistor is represented by the following equation.
Here, the back gate effect is ignored.

P-channel transistor 705 I0 = 1/2 · βP · (VDD-V795-VTP) ² P-channel transistor 703 I0 / k = βP · {(VDD-V794-VTP) · (VDD-V793) -1 / 2 ・ (VDD-V793)
² } P-channel transistor 704 I0 / k = 1/2 · βP · (V793-V795-VTP) ² Here, VDD indicates the voltage of power supply 1. V795 indicates the voltage of the node 795, V793 indicates the voltage of the node 793, and V794 indicates the voltage of the node 794. The threshold voltage of each P-channel transistor is VTP.

According to this equation, the voltage at each node is the same as the current value shown in FIG.

VDD-V795 = √ (2 ・ I0 / βP) + VTP VDD-V793 = (k-√k) / k ・ (VDD-V795-VTP) VDD-V794 = (k ² -k√√ + 2√k) / {2 ・ k (k-1)} ・ (VDD-V795-VTP)
+ VTP.

Similarly, the following relationship is required for the P-channel transistor 703 to operate in the non-saturation region and the P-channel transistor 704 to operate in the saturation region.

0 <k <4 (k + √k) · (k−2) / {2 · k · (k−1)} <VTP / (VDD−V795-VTP) From these conditions, 2 ≦ k < 4 and VTP <2 · (VDD-V795-VTP). However, if K = 2, the conditions related to VTP become unnecessary. Here, it is considered appropriate to use K = 2. These are the same as in FIG.

Under the above conditions, a constant current having good characteristics can be obtained.

FIG. 8 is a modification of FIG. 4 as shown in FIG. 7, in which FIG. 3 is replaced with an N-channel transistor from a P-channel transistor.

As in FIG. 7, the current value of the current source 6 was not I0 but I0 / k. N-channel transistor 80
The current drive capability of 3,804 is from k · βN to βN.

The constant current characteristics of this circuit will be described qualitatively in the same manner as in FIG. As in FIG. 3, each transistor, substrate potential, and channel length modulation effect are not included in the calculation.

The N-channel transistor 805 operates with a saturation characteristic as long as a current flows. The N-channel transistor 804 also operates in the saturation region, and the N-channel transistor 803 operates in the non-saturation region. At this time, the current value of each transistor is represented by the following equation.

N-channel transistor 805 I0 = 1/2 · βN · (V895-VTN) ² N-channel transistor 803 I0 / k = βN · {(V894-VTN) · V
893) -1/2 ・ V893 ² } N-channel transistor 804 I0 / k = 1/2 ・ βN ・ (V895-V89
3-VTN) ² where V795 is the voltage at node 895, V893 is the voltage at node 893, and V894 is the voltage at node 894. The threshold voltage of each N-channel transistor is VTN.

According to this equation, the voltage at each node is the same as the current value shown in FIG.

V895 = √ (2 ・ I0 / βN) + VTN V893 = (k-√k) / k ・ (V895-VTN) V894 = (k ² -k√√k + 2√k) / {2 ・k (k-1)} · (V895-VTN) + VTN.

Similarly, the following relationship is required for the N-channel transistor 803 to operate in the non-saturation region and the N-channel transistor 804 to operate in the saturation region.

0 <k <4 (k + √k) · (k−2) / {2 · k · (k−1)} <VTN / (V895-VTN) N channels in a range of k where this condition is satisfied Unsaturated and saturated region operating conditions of the transistors 803 and 804 are satisfied. From these conditions, it is desirable that 2 ≦ k <4 and VTN <2 · (V895-VTN). However, if K = 2, conditions relating to VTN become unnecessary. Here, it is considered appropriate to use K = 2. These are the same as in FIG.

Under the above conditions, a constant current having good characteristics can be obtained.

FIG. 9 shows a case where the current sources 5 and 6 in FIG. 7 are replaced with N-channel transistors. The substrate potential of the P-channel transistor is set to be the same as the source.

Since the N-channel transistor 913 has its gate and drain connected, it operates in a saturation region. When the current source 7 causes the current of I0 to flow, a voltage is generated at the node 983. When the N-channel transistors 912 and 913 have the same current driving capability and the N-channel transistor 911 is a transistor having a current driving capability 1 / k times that of the N-channel transistors 912 and 913, the N-channel transistors 511 and 512 are saturated. In the operating range, the N-channel transistor 512 operates as a current source for flowing a current value of I0, and the N-channel transistor 511 operates as a current source of I0.
It operates as a current source that passes a current value of / k.

FIG. 10 shows a modification of the transistor shown in FIG. This allows a constant current to be used between the terminal and the power supply, rather than between the terminal and the ground. Also, the current source is connected to the power supply instead of the ground connection.

FIG. 11 has the same configuration as FIG. However, here, the current value of the current source 5 is not I0 but a value of k · I0. Further, the current drive capability of the P-channel transistors 1103 and 1104 is changed from k · βP to βP.

From the above, the constant current characteristic of this circuit will be described qualitatively as in FIG. As in FIG. 3, each transistor, substrate potential, and channel length modulation effect are not included in the calculation.

The P-channel transistor 1105 operates with a saturation characteristic as long as a current flows. The P-channel transistor 1104 also operates in the saturation region, and the P-channel transistor 1103 operates in the non-saturation region. At this time, the current value of each transistor is represented by the following equation. Here, the back gate effect is ignored.

P-channel transistor 1105 k ・ I0 = 1/2 ・ βP (VDD-V1195-VTP) ² P-channel transistor 1103 I0 = βP ・ {(VDD-V1194-VTP) ・ (VDD-V1193) -1 / 2 ・ (VDD-V119
3) ² } P-channel transistor 1104 I0 = 1/2 · βP · (V1193-V1195-VTP) ² Here, VDD indicates the voltage of power supply 1. V1195 indicates the voltage of the node 1195, V1193 indicates the voltage of the node 1193, and V1194 indicates the voltage of the node 1194. The threshold voltage of each P-channel transistor is VTP.

According to this equation, the voltage at each node is the same as the current value shown in FIG.

VDD-V1195 = √ (2 ・ I0 / βP) + VTP VDD-V1193 = (k-√k) / k ・ (VDD-V1195-VTP) VDD-V1194 = (k ² -k√√k + 2√k) / {2 ・ k (k-1)} ・ (VDD-V1195-VT
P) + VTP.

Similarly, in order for the P-channel transistor 1103 to operate in the non-saturation region and the P-channel transistor 1104 to operate in the saturation region, the following relationship is required.

0 <k <4 (k + √k) · (k−2) / {2 · k · (k−1)} <VTP / (VDD−V1195-VTP) From these conditions, 2 ≦ k < 4 and VTP <2 · (VDD-V1195-VTP). However, if K = 2, the conditions related to VTP become unnecessary. Here, it is considered appropriate to use K = 2. These are the same as in FIG.

Under the above conditions, a constant current having good characteristics can be obtained.

FIG. 12 is a modification of FIG. 4 as shown in FIG. 11 in which FIG. 3 is replaced with an N-channel transistor from a P-channel transistor.

As in FIG. 11, the current value of the current source 6 was not I0 but k · I0. Also N-channel transistor 1
The current driving capability of 203 and 1204 is changed from k · βN to βN.

From the above, the constant current characteristics of this circuit will be qualitatively described in the same manner as in FIG. As in FIG. 3, each transistor, substrate potential, and channel length modulation effect are not included in the calculation.

The N-channel transistor 1205 operates with a saturation characteristic as long as a current flows. Similarly, the N-channel transistor 1204 operates in the saturation region, and the N-channel transistor 1203 operates in the non-saturation region. At this time, the current value of each transistor is represented by the following equation.

N-channel transistor 1205 k · I0 = 1/2 ·
βN ・ (V1295-VTN) ² N-channel transistor 1203 I0 = βN ・ {(V1294-VTN) ・ V
1293) -1/2 ・ V1293 ² } N-channel transistor 1204 I0 = 1/2 ・ βN ・ (V1295-V12
93-VTN) ² where V795 is the voltage at node 1295, V1293 is the voltage at node 1293, and V1294 is the voltage at node 1294. The threshold voltage of each N-channel transistor is VTN.

According to this equation, the voltage at each node is the same as the current value shown in FIG.

V1295 = √ (2 ・ I0 / βN) + VTN V1293 = (k-√k) / k ・ (V1295-VTN) V1294 = (k ² -k√√k + 2√k) / {2 ・k (k-1)} · (V1295-VTN) + VTN.

Similarly, in order for the N-channel transistor 1203 to operate in the non-saturation region and the N-channel transistor 1204 to operate in the saturation region, the following relationship is required.

0 <k <4 (k + √k) · (k−2) / {2 · k · (k−1)} <VTN / (V1295-VTN) N channels in the range of k where this condition is satisfied Unsaturated and saturated region operating conditions of the transistors 1203 and 1204 are satisfied. From these conditions, it is desirable that 2 ≦ k <4 and VTN <2 · (V1295-VTN). However, if K = 2, conditions relating to VTN become unnecessary. Here, it is considered appropriate to use K = 2. These are the same as in FIG.

Under the above conditions, a constant current with good characteristics can be obtained.

FIG. 13 shows a configuration in which the current sources 5 and 6 in FIG. 11 are replaced with N-channel transistors. The substrate potential of the P-channel transistor is set to be the same as the source.

Since the gate and the drain of the N-channel transistor 1313 are connected, the operation is performed in a saturation region. When the current source 7 supplies the current of I0, the node 1383
Voltage is generated. N-channel transistors 1311, 131
3 have the same current driving capability, and if the N-channel transistor 1312 is a transistor having k times the current driving capability of the N-channel transistors 1312 and 1313, as long as the N-channel transistors 1311 and 1312 operate in the saturation region, The N-channel transistor 1312 operates as a current source for flowing the current value of I0,
1 operates as a current source for flowing a current value of k · I0.

FIG. 14 shows a modification of the transistor shown in FIG. This allows a constant current to be used between the terminal and the power supply, rather than between the terminal and the ground. Also, the current source is connected to the power supply instead of the ground connection.

FIG. 15 has the same configuration as FIG. However, here, the current drive capability of the P-channel transistors 1501 and 1502 is changed from k · β to m · k · β.

As in FIG. 3, P-channel transistor 150
The ranges of the voltage applied to the gates 1501 and the coefficient k are the same as those in FIG.

Here, the constant current output of the P-channel transistors 1501 and 1502 is m times as large as that of FIG. The range in which the constant current of the output terminal 9 is output at this time is the same as in FIG. Thus, it is possible to adjust the current driving capability, that is, the size of the transistor regardless of the value of the current source used.

FIG. 16 is a modification of FIG. 15 as shown in FIG. 4 in which FIG. 3 is replaced with an N-channel transistor from a P-channel transistor.

As in FIG. 15, P-channel transistor 1
The current drive capability of 601 and 1602 is changed from k · β to m · k · β.

As in FIG. 4, P-channel transistor 160
The range of the voltage applied to the gates 1, 1602 and the coefficient k are the same as those in FIG.

Here, the constant current output is m times as large as that of the N-channel transistors 1601 and 1602 because the current driving capability is m times as large as that of FIG. The range in which the constant current of the output terminal 9 is output at this time is the same as that in FIG. Thus, it is possible to adjust the current driving capability, that is, the size of the transistor regardless of the value of the current source used.

FIG. 17 shows a configuration in which the current sources 5 and 6 in FIG. 15 are replaced with N-channel transistors. The substrate potential of the P-channel transistor is set to be the same as the source.

Since the gate and the drain of the N-channel transistor 1713 are connected, the operation is performed in a saturation region. The current source 7 flows the current of I0, so that the node 1783
Voltage is generated. N-channel transistors 1711, 171
2 and 913 have the same current driving capability, so that the N-channel transistors 1711, 1712, and 171 are in a range where the N-channel transistors 1711, 1712, and 1713 operate in the saturation region.
3 operates as a current source for flowing the current value of I0.

FIG. 18 shows a circuit of the circuit shown in FIG. This allows a constant current to be used between the terminal and the power supply, rather than between the terminal and the ground. Also, the current source is connected to the power supply instead of the ground connection.

FIG. 19 has basically the same configuration as FIG. However, here, P-channel transistors are connected in multiple stages. That is the P-channel transistors 1933 to 1934. P-channel transistors 1933-1934
Has a gate and a drain connected to each other. Therefore, when the current of the current source 6 flows through these transistors, a current having a saturation region characteristic flows.

The voltage at each node is determined from the current value shown in FIG.

VDD-V1995 = √ (2 ・ I0 / βP) + VTP VDD-V1993 = (k-√k) / k ・ (VDD-V1995-VTP) VDD-V1994 = (k ² -k√√k + 2√k) / {2 ・ k (k-1)} ・ (VDD-V1995-VT
P) + VTP V1994-V1971 = √ {2 · I0 / (k · βP)} + VTP V1974-V1972 = √ {2 · I0 / (k · βP)} + VTP.

Similarly, the following relationship is necessary for the P-channel transistor 1903 to operate in the non-saturation region and the P-channel transistor 1904 to operate in the saturation region.

0 <k <4 (k + √k) · (k−2) / {2 · k · (k−1)} <V
TP / (VDD-V1995-VTP) In the range of k where this condition is satisfied, the operating conditions of the non-saturated and saturated regions of the P-channel transistors 1903 and 1904 are satisfied. From these conditions, it is preferable that 2 ≦ k <4 and VTP <2 · (VDD−V1995−VTP). However, if K = 2, the conditions related to VTP become unnecessary. Here, it is considered appropriate to use K = 2. These are the same as in FIG.

This circuit is a P-channel transistor 190
4. In the range where 1933 to 1934 operate in the saturation region and the P-channel transistor 1902 operates in the saturation region, the output terminal 9 operates as a constant current circuit.

With this circuit configuration, the voltage between the output terminal 9 and the power supply 1 is changed to the P-channel transistors 1901, 1902, 190
It will be divided from 3 to 1932. That is, the source-drain voltage of the P-channel transistors 1902, 1931 to 1932 operating in the saturation region that determines the constant current is shown in FIG.
Therefore, the influence of the channel length modulation effect is reduced, so that a current that is less dependent on the power supply voltage or the voltage of the output terminal 9 can be obtained.

FIG. 20 is a modification of FIG. 19 as shown in FIG. 8 in which FIG. 4 is replaced with an N-channel transistor from a P-channel transistor.

Here, N-channel transistors are connected in multiple stages. That is the N-channel transistor 2033
From 2034. N-channel transistors 2033 to 203
4 has a gate and a drain connected to each other. Therefore, when the current of the current source 6 flows through these transistors, a current having a saturation region characteristic flows.

The voltage of each node is calculated as follows from the current value shown in FIG. 4, V2095 = √ (2 · I0 / βP) + VTN V2093 = (k−√k) / k · (V2095-VTP) V2094 = (k ² -k ・ √k + 2√k) / {2 ・ k (k-1)} ・ (V2095-VTN) + VTN V2071-V2094 = √ {2 ・ I0 / (k ・ βN)} + VTN V2072-V2074 = √ {2 · I0 / (k · βN)} + VTN.

Similarly, the following relationship is required for the N-channel transistor 2003 to operate in the non-saturation region and the P-channel transistor 2004 to operate in the saturation region.

0 <k <4 (k + √k) · (k−2) / {2 · k · (k−1)} <VTN / (V2095-VTN) N channels in the range of k satisfying this condition The unsaturated and saturated region operating conditions of the transistors 2003 and 2004 are satisfied. From these conditions, it is desirable that 2 ≦ k <4 and VTN <2 · (VDD−V2095-VTP). However, if K = 2, the conditions related to VTP become unnecessary. Here, it is considered appropriate to use K = 2. These are the same as in FIG.

This circuit is a P-channel transistor 200
4, 2033 to 2034 operate in the saturation region, and the output terminal 9 operates as a constant current circuit in a range where the N-channel transistor 2002 operates in the saturation region.

According to this circuit configuration, the voltage between the output terminal 9 and the power supply 1 is changed to N-channel transistors 2001, 2002, and 203.
It will be split from 1 to 2032. That is, the source-drain voltage of the N-channel transistors 2002 and 2031 to 2032 operating in the saturation region that determines the constant current is shown in FIG.
Therefore, the influence of the channel length modulation effect is reduced, so that a current that is less dependent on the power supply voltage or the voltage of the output terminal 9 can be obtained.

FIG. 21 shows a case where the current sources 5 and 6 in FIG. 19 are replaced with N-channel transistors. The substrate potential of the P-channel transistor is set to be the same as the source.

Since the gate and the drain of the N-channel transistor 2113 are connected, the operation is performed in a saturation region. When the current source 7 supplies the current of I0, the node 2183
Voltage is generated. N-channel transistors 2111, 211
2 and 2113 have the same current driving capability, so that the N-channel transistors 2111, 2112, and 2113 operate within the saturation region.
3 operates as a current source for flowing the current value of I0.

FIG. 22 shows a modification of the transistor shown in FIG. This allows a constant current to be used between the terminal and the power supply, rather than between the terminal and the ground. Also, the current source is connected to the power supply instead of the ground connection.

FIG. 23 is obtained by adding P-channel transistors 2306, 2307 and 2308 to the circuit of FIG. A P-channel transistor whose gate is connected to the drain is connected in series between the power supply 1 and the P-channel transistor 2305. Similarly, a P-channel transistor whose gate is connected to the drain is connected in series between P-channel transistors 2303 and 2304. Similarly, it is assumed that a P-channel transistor 2306 is placed between P-channel transistors 2301 and 2302, and the gates of P-channel transistors 2306 and 2307 are commonly connected. It is assumed that these P-channel transistors have a current driving capability capable of flowing a sufficiently large current with respect to the flowing current I0. When a current flows through each P-channel transistor, a voltage close to the threshold voltage is generated between the P-channel transistors 2306, 2307, and 2308. Therefore, the following relationship is established.

P-channel transistor 2303 VDD-V2396> VDD-V2393 Therefore, P-channel transistor 2303 always operates in the unsaturated region.

As long as the P-channel transistor 2304 and the P-channel transistor 2302 operate in the saturation region, the current output from the output terminal 9 shows a constant current characteristic. The characteristics of this output current are the same as the current values in the circuit of FIG.

FIG. 24 is obtained by adding P-channel transistors 2406, 2407 and 2408 to the circuit of FIG. Ground 0
An N-channel transistor whose gate is connected to the drain is connected in series between the N-channel transistor 2405 and the N-channel transistor 2405. P-channel transistors 2403 and 2404
A P-channel transistor whose gate is connected to the drain is connected in series. Similarly, N-channel transistor 2 is connected between N-channel transistors 2401 and 2402.
406 is placed, and the gates of the N-channel transistors 2406 and 2407 are assumed to be commonly connected. It is assumed that these N-channel transistors have a current driving capability capable of flowing a sufficiently large current with respect to the flowing current I0.
When a current flows through each N-channel transistor, a voltage close to the threshold voltage is generated between the N-channel transistors 2406, 2407, and 2408. Therefore, the following relationship is established.

N-channel transistor 2403 VDD−V4396> V2493 Therefore, the N-channel transistor 2403 always operates in the unsaturated region.

The current output from the output terminal 9 exhibits a constant current characteristic in a range where the N-channel transistors 2404 and 2402 operate in the saturation region. The characteristics of this output current are similar to the current values in the circuit of FIG.

FIG. 25 shows a configuration in which the current sources 5 and 6 in FIG. 24 are replaced with N-channel transistors. The substrate potential of the P-channel transistor is set to be the same as the source.

Since the gate and the drain of the N-channel transistor 2513 are connected, the operation is performed in a saturation region. The current source 7 supplies the current of I0, thereby
Voltage is generated. N-channel transistors 2511, 251
2 and 2513 have the same current driving capability, so that the N-channel transistors 2511, 2512, and 251 are in a range where the N-channel transistors 2511, 2512, and 2513 operate in the saturation region.
3 operates as a current source for flowing the current value of I0.

FIG. 26 shows a circuit of the circuit shown in FIG. 24 in which the type of the transistor is changed. This allows a constant current to be used between the terminal and the power supply, rather than between the terminal and the ground. Also, the current source is connected to the power supply instead of the ground connection.

This embodiment shows only some embodiments of the present invention, and other developments can be considered.

[0127]

According to the present invention, a constant current circuit having better constant current characteristics than a conventional constant current circuit utilizing the operation of a single P-channel or N-channel transistor in the saturation region can be obtained.

Similarly, according to the present invention, there is no need to connect the gate and the drain of a P-channel transistor and connect them in series as in the conventional cascode type. It is not necessary to apply a voltage equal to or higher than the sum of the threshold voltages of the P-channel transistors connected in series in order to allow a current to flow through these P-channel transistors. Therefore, good constant current characteristics can be obtained even at a low power supply voltage equal to or lower than the threshold voltage of the P-channel transistors connected in series. Even with this power supply voltage, it is possible to obtain characteristics with little voltage dependence of the output terminal.

Further, by adopting the circuit configurations shown in FIGS. 19 to 26, it is not necessary to operate all the transistors connected in series in the saturation region as in a normal cascade-type constant current circuit. Therefore, a constant current circuit having good constant current characteristics can be obtained with a lower power supply voltage than a conventional cascode type constant current circuit.

Further, by adopting the configuration shown in FIGS. 23 to 26, the degree of freedom in setting the current driving capability of the transistor is improved, and the design becomes easier. Further, since the voltage between the source and the drain of the transistor operating in the saturation region becomes relatively small, the fluctuation of the current value with respect to the voltage of the output terminal is further reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a constant current circuit according to the present invention.

FIG. 2 is a diagram showing a configuration example of a constant current circuit according to the present invention.

FIG. 3 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 4 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 5 is a diagram of one embodiment of a constant current circuit of the present invention.

FIG. 6 is a diagram of an embodiment of a constant current circuit of the present invention.

FIG. 7 is a diagram of one embodiment of a constant current circuit of the present invention.

FIG. 8 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 9 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 10 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 11 is a diagram of an embodiment of a constant current circuit of the present invention.

FIG. 12 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 13 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 14 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 15 is a diagram of an embodiment of a constant current circuit of the present invention.

FIG. 16 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 17 is a diagram of one embodiment of a constant current circuit of the present invention.

FIG. 18 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 19 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 20 is a diagram of an embodiment of a constant current circuit of the present invention.

FIG. 21 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 22 is a diagram of an embodiment of a constant current circuit of the present invention.

FIG. 23 is a diagram of an embodiment of a constant current circuit according to the present invention.

FIG. 24 is a diagram of an embodiment of a constant current circuit of the present invention.

FIG. 25 is a diagram of an embodiment of the constant current circuit of the present invention.

FIG. 26 is a diagram of an embodiment of a constant current circuit of the present invention.

FIG. 27 is a circuit diagram of a constant current circuit according to a conventional invention.

[Explanation of symbols]

0 Ground 1 Power supply 5 Current source 9 Output terminal 5 Current source 101, 102, 103 MIS transistors 201, 202, 203 MIS transistors 301, 302, 303, 304, 305 P-channel transistors 401, 402, 403, 404, 405 N-channel Transistors 1901, 1902, 1903, 1904, 1905, 1931, 1932, 1933, 19
34, P-channel transistors 2001, 2002, 2003, 2004, 2005, 2031, 2032, 2033, 20
34, N-channel transistor 2301, 2302, 2303, 2304, 2305, 2306, 2107, 2108 P
Channel transistor 2401, 2402, 2403, 2404, 2405, 2406, 2407, 2408 N
Channel transistor

Claims (7)

[Claims] 1. A constant current circuit comprising a plurality of MIS transistors of the same conductivity type and a current source, wherein the plurality of MIS transistors connected in series between a first power supply terminal and an output terminal; A control circuit connected to the first power supply terminal, and a current source connected in series between the first power supply terminal and the second power supply terminal together with the control circuit; A constant current circuit, a plurality of MIS transistors, and a current source, wherein the gate terminals of the plurality of MIS transistors are controlled based on the voltage value of one power supply terminal and the current value of the current source. In a constant current circuit, n MIS transistors of the first conductivity type are connected in series (n is a natural number), one end of a row of the MIS transistors connected in series is connected to a power supply or a ground, and the other end is connected. An output terminal, a control circuit and a current source are connected in series between a power supply and a ground, the control circuit has n outputs, and the n outputs of the control circuit are the n MISs connected in series. A constant current circuit connected to the gates of the transistors, wherein the control circuit controls n gates of the MIS transistors connected in series according to a power supply voltage and a current value of the current source. 2. The control circuit according to claim 1, wherein the source is connected to a power supply or a ground, and the gate and the drain are connected to a first node. A first MIS transistor of the first conductivity type, a first current source installed between the first node and a ground or a power supply, and a constant current flowing in the direction of the ground or the power supply, and a source connected to the power supply or the ground. And a second MIS transistor of the first conductivity type having a gate connected to the second node, a source connected to the drain of the second MIS transistor, and a gate connected to the first node. A third MIS transistor of the first conductivity type;
A second current source installed between the second node and a ground or a power supply and flowing a constant current value in the direction of the ground or the power supply, and the second node is an MI connected in series.
An MIS transistor connected to the power supply of the S transistor or the gate of the MIS transistor connected to the ground, and the first node is connected to an output terminal of the MIS transistor connected in series.
MI connected to the gate of the transistor and connected in series
In a configuration in which the current driving capabilities of the S transistors are the same, the current values of the first current source and the second current source are the same, and the current driving capabilities of the second and third MIS transistors are the same. And twice the current driving capability of the first MIS transistor, or the second and third M
The current drive capability of the IS transistor is the same, is greater than twice and less than or equal to four times the current drive capability of the first MIS transistor, and is two minutes of the threshold voltage of the first MIS transistor. A constant current circuit, wherein the effective gate voltage of the first MIS transistor is higher than 1. 3. The configuration according to claim 2, wherein the first, second, and third MIS transistors have the same current driving capability, and the second MIS transistor has a current driving capability corresponding to the current value of the first current source. The current value of the current source is one half, or the current value of the second current source is one quarter of the current value of the first current source.
As described above, the constant current circuit is characterized in that the effective gate voltage of the first MIS transistor is smaller than half and is larger than half the threshold voltage of the first MIS transistor. 4. The control circuit according to claim 1, wherein the MIS transistor connected in series comprises n + 2 transistors, wherein the control circuit connects the source to the power supply or the ground, and connects the gate and the drain to the first node. A first MIS transistor of a first conductivity type connected to the first node, a first current source installed between the first node and a ground or a power supply, and a constant current flowing in the direction of the ground or the power supply; A second MIS transistor of a first conductivity type connected to a power supply or the ground, a gate connected to a second node, and a source connected to the second M
A third MIS transistor of the first conductivity type, which is connected to the drain of the IS transistor, and whose gate is connected to the first node, and whose gate and drain are the (m + 2) th node (m is 1
(N is an integer equal to or less than n), and connected in series to the (m + 3) th MIS transistor of the first conductivity type, the source of which is connected to the drain of the (m + 1) th MIS transistor, and +2
A second current source installed between the node and the ground or the power supply and flowing a constant current value in the direction of the ground or the power supply, and the second node is connected to the power supply or the ground of the MIS transistor connected in series. The first node is connected to the gate of the MIS transistor connected to the output terminal of the serially connected MIS transistor, and the m + 2th node is connected to the serially connected MIS transistor. Connect to the gate of the m + 2th MIS transistor counting from the power or ground of the transistor,
In the configuration in which the current driving capabilities of the MIS transistors connected in series are the same, the current values of the first current source and the second current source are the same, and the current driving capabilities of the second and third MIS transistors are changed. Ability is the same and said first
The current driving capability of the MIS transistor is twice as large, or the current driving capability of the second to (m + 3) th MIS transistors is the same, and the current driving capability of the first MIS transistor is the same. More than 2 times and not more than 4 times, and one half of the threshold voltage of the first MIS transistor
A constant current circuit, wherein an effective gate voltage of the first MIS transistor is higher than that of the first MIS transistor. 5. The control circuit according to claim 1, wherein the source and the ground are connected to the power supply or the ground, and the gate and the drain are connected to the third node. A first MIS transistor of a first conductivity type, a first MIS transistor of a first conductivity type having a source connected to a third node, and a gate and a drain connected to a first node; A first current source installed between one node and a ground or a power supply and flowing a constant current in the direction of the ground or the power supply, a first current source connected to the power supply or the ground, and a gate connected to the second node A second conductive type MIS transistor, a source connected to the drain of the second MIS transistor, and a fourth conductive type fourth MIS transistor connected to the gate and drain of the fourth node.
An MIS transistor, a third MIS transistor of a first conductivity type having a source connected to the fourth node and a gate connected to the first node, and between the second node and ground or a power supply. The second node is connected to the power supply of the MIS transistor connected in series or the gate of the MIS transistor connected to the ground, and the fourth node is connected to the MIS transistor connected to the power supply or the ground. Node is connected to the gate of the second MIS transistor from the power or ground side connected in series,
The first node is connected to a gate of an MIS transistor connected to an output terminal of the MIS transistor connected in series, and the current driving capability of the MIS transistor connected in series is the same. Source and the second current source have the same current value, and the third MIS
A constant current circuit, wherein the transistor has a higher current driving capability than other MIS transistors, and a current driving capability of the fourth MIS transistor is the same as that of the MIS transistors connected in series. 6. The constant current circuit according to claim 1, wherein the circuit in which the MIS transistor is connected to a power supply is configured such that the MIS transistor of the first conductivity type is a P-channel MOS transistor. 7. The circuit according to claim 1, wherein the circuit in which the MIS transistor is connected to the ground is a first conductive type MI.
A constant current circuit, wherein the S transistor is configured by an N-channel MOS transistor.