JP2000031408A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method by which the diffused layer of a transistor and a storage electrode buried in a trench can be connected to each other in a self-aligned way. SOLUTION: In a semiconductor device 100 having a trench capacitor 4, the trench capacitor 4 is constituted of a storage electrode section 5, a capacitor insulating film 7 covering the main body section 6, the outer periphery, and lower end face of the section 5, a first ion implantation layer 8 which covers part of the outer periphery and lower end face of the insulating film 7, a collar section 10 which is composed of an insulating layer 10 covering the outer periphery of the main body section 6 of the electrode section 5 near the upper part 9 of the section 5, and an enlarged-diameter section 12 which is provided near the upper end 11 of the electrode section 5 and has a width larger than the main body section 6 has. A capacitor insulating film 7 provided to the part of the outer peripheral edge of the enlarged-diameter section 12 of the electrode section 5 is jointed to a diffused layer 13 constituting an element 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a memory semiconductor device having a trench cell structure capable of suppressing a leakage current, and a method of self-aligning the memory semiconductor device. The present invention relates to a method that enables efficient manufacturing.

[0002]

2. Description of the Related Art In a random access memory (DRAM) having a trench cell, one of the important factors is to electrically connect a storage electrode in the trench and a diffusion layer of a transistor of the memory cell. I have. JP-A-8-
No. 46158 discloses a method of connecting a storage electrode in a trench and a diffusion layer of a transistor of a memory cell by a strap. This method will be described in accordance with the steps shown in FIGS. It becomes as follows.

First, as shown in FIG. 4A, this technique will be described with reference to FIGS. 4A, first, an ONO film 101 (oxide-nitride-oxide) and a TEOS (tetraethyl orthosilicate) film 102 are formed on a silicon substrate 100, and an upper trench 103 is formed. Thereafter, the side wall 104 is retracted by isotropically etching the side wall 104.

In FIG. 4B, an oxide film is formed by thermal oxidation, and a collar oxide film 105 is formed by etching back. In FIG. 4C, a trench is formed to a final depth, phosphorus or the like is implanted 106, and As is
And so on 107. After that, a capacitor insulating film 109 is formed, a polysilicon 110 doped with arsenic or phosphorus as a storage electrode is formed, and etch back is performed. At this time, the distance 112 from the surface to the upper end 111 of the polysilicon is not so important.

In FIG. 5A, the collar oxide film 105 is etched by wet etching so that the upper end of the collar is slightly lower than the upper end 111 of polysilicon. In FIG. 5B, a strap 116 is formed by depositing and polishing polysilicon to leave only in the trench, and a silicon oxide film 117 is formed by thermal oxidation using 101 as a mask.

FIG. 5C shows an element isolation silicon oxide film 1.
18, a gate oxide film 125 of the transistor 122 of the memory cell, a gate electrode 120, a diffusion layer 123 serving as a source / drain of the transistor, and an LDD sidewall oxide film 121 are formed. In the above conventional example, the diffusion layer of the transistor of the memory cell can be connected to the storage electrode inside the trench.

However, as shown in the conventional example, since the collar 105 is etched to be lower than the upper end of the polysilicon to form the strap polysilicon, doping of the polysilicon with impurities is insufficient. In this case, a PN junction between the strap and the P-type impurity layer of the silicon substrate is not sufficiently formed, which causes a junction leak current.

If the etching of the oxide film collar 105 is excessive, the area of contact between the strap polysilicon and the silicon substrate increases. This increases the contact area between the diffusion layer of the transistor of the N-type memory cell, the strap polysilicon, and the P-type substrate. This indicates that the PN junction area increases, which causes an increase in leakage current and an increase in junction capacitance due to an increase in the junction area. As a result, there arises a problem that the ability of the DRAM to hold the charge on the storage electrode is reduced, and that the bit line capacitance is apparently large, so that the operation speed is reduced.

[0009]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the above-mentioned conventional disadvantages and to provide a method for connecting a diffusion layer of a transistor and a storage electrode buried in a trench in a self-aligned manner. Is what you do. An object of the present invention is to provide a method for connecting the diffusion layer of the memory cell and the storage electrode buried in the trench without increasing the contact area.

[0010]

The present invention employs the following technical configuration to achieve the above object. That is, a first aspect according to the present invention is a semiconductor device including an element such as a transistor formed on a surface of a substrate and a trench capacitor formed in the substrate below the transistor element. In the trench capacitor, the storage electrode portion, a capacitance insulating film covering the outer periphery and the lower end surface of the main body portion of the storage electrode portion, a part of the outer periphery of the capacitance insulation film and a lower end surface thereof are covered. A first ion-implanted layer, and further a collar portion made of an insulating layer covering the outer periphery of the storage electrode portion main body in the vicinity of the upper portion of the storage electrode portion, provided on the upper end portion of the storage electrode portion, An enlarged diameter portion having a width larger than the width of the storage electrode portion main body portion, and the capacitance provided on a part of an outer peripheral portion of the enlarged diameter portion of the storage electrode portion. The insulating film is A second aspect according to the present invention is that a device is formed on a surface of a substrate, and a device is formed in the substrate corresponding to a portion below the device. In a method of manufacturing a semiconductor device comprising a trench capacitor including a formed storage electrode, a trench portion is formed in a semiconductor substrate and accumulated in the trench portion via an oxide film collar portion on an inner wall portion of the trench portion. In forming the electrode, at least a conductive film is provided on the substrate surface, and an etch-back adjusting oxide film for the oxide film forming the collar portion is provided on the conductive film, and after forming the trench portion, An oxide film for forming a collar portion is formed in the trench portion, and the oxide film for forming a collar portion is subjected to an etching process. As will be formed at a position lower than the surface, a method of manufacturing a semiconductor device to select the configuration of the etch-back adjustment oxide film.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device and the method of manufacturing the semiconductor device according to the present invention employ the above-mentioned technical constitution, and therefore, a film capable of obtaining an oxide film collar at the time of forming a trench capacitor and a selectivity at the time of etching. Is formed on the uppermost surface, so that the upper end of the oxide film collar can be lowered to the surface of the silicon substrate at the time of etch back to leave the oxide film collar only on the side wall.

As a result, since the storage electrode in the trench and the diffusion layer of the transistor of the memory cell are located only through the capacitor insulating film, the storage electrode and the transistor of the memory cell are self-aligned by, for example, a salicide process. It becomes possible to connect to the diffusion layer.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. That is, FIG. 1 is a cross-sectional view schematically showing the configuration of a specific example of a semiconductor device according to the present invention.
A semiconductor device 100 comprising an element 3 such as a transistor formed on a surface 2 of the substrate 1 and a trench capacitor 4 formed in the substrate 1 below the element 3. Reference numeral 4 denotes a storage electrode portion, a capacitance insulating film 7 covering the outer periphery and a lower end surface of the main body portion 6 of the storage electrode portion 5, a portion of the outer periphery of the capacitance insulation film 7 and a lower end surface thereof. A first ion-implanted layer 8, a collar portion 10 made of an insulating layer covering an outer periphery of the storage electrode portion main body 6 in the vicinity of an upper portion 9 of the storage electrode portion 5, an upper end portion of the storage electrode portion 11, an enlarged diameter portion 12 having a width larger than the width of the storage electrode portion main body portion 6, and an outer peripheral portion of the enlarged diameter portion 12 of the storage electrode portion 5. Of the capacity provided in a part of Film 8 semiconductor device 100 is bonded to the diffusion layer 13 constituting the element 3 is shown.

In the semiconductor device 100 according to the present invention, it is desirable that the position of the upper end surface 14 of the collar portion 6 is located at a position lower than the position of the substrate surface 2. or,
In the present invention, the diffusion layer 13 forming the element portion 3
It is desirable that the storage electrode portion 5 and the storage electrode portion 5 are connected to each other only at the edge of the enlarged diameter portion 12 via the capacitance insulating film 8.

In the semiconductor device 100 according to the present invention, the semiconductor device 100 is further connected to a part of the first ion-implanted layer 8 arranged on the outer periphery of the trench capacitor 4. External terminals (not shown)
It is also preferable that a second ion-implanted layer 15 connected to is provided. On the other hand, in the present invention, the diffusion layer 13 constituting the element of the semiconductor device 100 and the storage electrode 5 in the trench capacitor 4 are formed by a conductive film formed on the surface 2 of the semiconductor substrate 1. It is also desirable that they be connected by 16.

Further, the semiconductor device 10 according to the present invention
It is preferable that the semiconductor substrate 1 at 0 is a silicon semiconductor substrate and the conductive film 16 is a silicide film. Hereinafter, the semiconductor device 100 according to the present invention will be described.
As described above in detail, the feature of the present invention is that a storage cell 5 and a memory cell buried in a trench 4 are provided for a random access memory (DRAM) having a trench cell. In connection with the diffusion layer 13 forming the element 3 including the transistor and the like, while increasing the depth of the diffusion layer 13 in the element 3 such as the cell transistor and suppressing the increase of the junction leakage current, ,
And to perform the process in a self-aligned manner.

Therefore, as shown in the cross-sectional view of one embodiment according to the present invention in FIG. 1, a structure is realized in which the diffusion layer 13 of the transistor 3 of the memory cell is connected to the storage electrode 5 buried in the trench 4. For this reason, in the present invention, FIG.
As described below, a silicon oxide film 23, a silicon nitride film 24, and an adjustment oxide film 25 are stacked as a mask for trench etching.

In the present invention, as the etch-back adjusting oxide film 25, a film which can easily secure a selectivity such as a predetermined etching rate with a silicon oxide film constituting a color oxide film at the time of dry etching back, For example, it is desirable to use a silicon film 25. Reference numeral 26 denotes a resist for a mask.

By using the oxide film 25 for adjusting the etch-back, after the first trench 27 is formed by etching, the diffusion layer 13 which is a part of the element 3 such as a memory cell, for example, becomes a transfer gate is formed. In order to insulate the ion-implanted layer 8 which is a part of the counter electrode of the storage electrode 5, a silicon oxide film 10 is formed and etched back to form a silicon oxide film collar 10.

At this time, it is possible to lower the upper end of the silicon oxide film collar 10 to the surface 2 of the silicon substrate 1 by increasing the amount of over-etching during the etch back of the silicon oxide film 10 for forming the collar portion 10. Therefore, trench 4
The storage electrode 5 buried in the silicon substrate 1 is separated from the silicon substrate 1 by an oxide film collar 10 or a capacitor insulating film 7, and the upper portion of the trench is separated only by a capacitor insulating film 7 of 100A or less. By forming a conductive film silicided by the process above the trench, an effect is obtained that the diffusion layer 13 of the transistor 3 of the memory cell and the storage electrode 5 embedded in the trench 4 can be easily connected. .

In addition, since the area of the diffusion layer of the transistor 3 does not increase at the time of this connection, problems such as an increase in junction leakage current due to an increase in the area of the diffusion layer and a decrease in operating speed due to an increase in the capacitance of the diffusion layer are not caused. Further, a configuration of the semiconductor device 100 according to the present invention and a specific example of a manufacturing method thereof will be described in detail with reference to FIGS.

That is, FIG. 1 shows a sectional process drawing of one embodiment according to the present invention. In FIG. 2A, first, an element isolation silicon oxide film 20 of about 300 nm is formed on a p-type silicon semiconductor substrate 1 by a normal LOCOS method or the like.
Further, a silicon oxide film 23, a silicon nitride film 24, and a polysilicon film 25 are formed to a thickness of about 20 nm, 200 nm, and 100 nm, respectively, and the resist is formed by a photolithography process so that only the trench capacitor formation region is opened. The first trench 27 is formed by etching the film and the silicon semiconductor substrate 1 using the resist as a mask.

Next, as shown in FIG. 2B, after removing the resist 26, a silicon oxide film is separately formed to a thickness of about 100 nm for forming a collar portion, and the silicon oxide film is etched back. As a result, an oxide film collar 10 made of a silicon oxide film is formed. At this stage, in the present invention, a polysilicon layer 25 is formed to etch back the oxide film 10 until the position of the upper end 14 of the oxide film collar 10 is near the surface 2 of the silicon substrate 1. ing.

That is, the silicon layer 25 used in the present invention is referred to as an etch-back adjustment oxide film 25.
Usually, at the time of etching back the silicon oxide film, it is difficult to secure an etching selectivity with respect to the silicon nitride film 24, and when the polysilicon 25 is not formed, the silicon nitride film 24 is etched. Color part 1
It is not possible to etch back such that the upper end of 0 is flush with the surface of the silicon semiconductor substrate 1.

Next, as shown in FIG. 2C, the silicon semiconductor substrate 1 is further etched to form a second trench 28 which becomes an actual capacitance storage region. At this time, the polysilicon film 25 is simultaneously etched and disappears. Further, in order to form a counter electrode, ion implantation is performed using phosphorus or the like. For example, the ion implantation conditions are 30 to 70 keV, and the surface concentration is 1.10 ²⁰ c.
The process is performed so as to be about m ⁻³ to form the n-type ion implantation layer 8.

Next, as shown in FIG. 2D, a capacitor insulating film 7 composed of a composite film of a silicon oxide film and a silicon nitride film is formed so as to have a thickness of 100 ° or less in terms of a silicon oxide film. To form the storage electrode 5,
A film 5 made of amorphous or polysilicon containing a concentration of 10 ²⁰ cm ^-3 is formed, and is etched back so as to remain only in the trench 4.

Next, as shown in FIG. 3A, to connect the ion-implanted layers 8 of the adjacent memory cells and connect them to an external circuit, the phosphorous is doped with 1 to 2 MeV energy at 1 to 2 MeV.
By implanting 510 ¹³ cm ⁻³ , an ion implanted layer 15 is formed, and the surface of the storage electrode 5 is thermally oxidized to 30 nm or more using the silicon nitride film 24 as a mask to insulate the gate electrode and the storage electrode. Oxidation forms a cap oxide film 29.

Next, as shown in FIG. 2B, the silicon nitride film 24 and the silicon oxide film 23 are removed by etching. Next, as shown in FIG. 2C, a gate oxide film 30 having a thickness of 10 nm or less is formed, and polysilicon serving as a gate electrode 31 is formed to have a thickness of about 200 nm, and then the gate is patterned.

Next, after the N ion implantation layer 32 is formed by a general method, the silicon oxide film sidewall 3 is formed.
3 and the N ⁺ ion-implanted layer 13 are formed, and then a film for forming a silicide, for example, a Ti film is sputtered and heat-treated to form a film on the gate polysilicon 31 and the silicon semiconductor substrate 2. A silicide film 34 is selectively formed.

At this time, the ion implantation layer 13 and the storage electrode 5
Only the capacitance insulating film 8 of 10 nm or less exists between the two. Therefore, the ion-implanted layer 13 and the storage electrode 5 can be connected in a self-aligned manner due to the slight progress of silicidation that occurs during silicidation. Further, since the silicon oxide film collar 10 or the capacitor insulating film 8 is always provided between the ion implantation layer 13 and the silicon substrate 1, the diffusion layer area of the memory cell transistor does not increase, and the diffusion layer area increases. Therefore, problems such as an increase in junction leak current and an increase in junction capacitance do not occur.

In the above embodiment, the oxide film collar 10 can be replaced with the silicon nitride film 24 and another film capable of obtaining a selectivity at the time of etching. As can be understood from the above description, as one specific example of the method for manufacturing a semiconductor device according to the present invention, an element is formed on a substrate surface and formed in the substrate corresponding to a lower part of the element. In a method of manufacturing a semiconductor device comprising a trench capacitor including a storage electrode, a trench is formed in a semiconductor substrate, and a storage electrode is formed in the trench through an oxide film collar on an inner wall of the trench. At this time, at least a conductive film 24 is provided on the surface 2 of the substrate 1, and an oxide film 25 for adjusting an etch back with respect to an oxide film forming the collar 10 is provided on the conductive film 24,
After forming the trench portion 4, an oxide film 10 for forming a collar portion is formed in the trench portion 4, and the oxide film 10 for forming a collar portion is subjected to an etching process. The structure of the etch-back adjustment oxide film 25 is selected so as to be formed at a position lower than the one surface 2.

Further, in the method of manufacturing a semiconductor device according to the present invention, more specifically, the etching rate of the etch-back adjusting oxide film 25 is set to be equal to the etching rate of the color portion forming oxide film 10. It is preferable to select the oxide film 25 for etching back adjustment.
It is also desirable to select the thickness of the film in relation to the etching rate of the collar portion forming oxide film.

In the method of manufacturing a semiconductor device according to the present invention, after the collar portion 10 is formed, the capacitance insulating film 7 is formed on the inner wall surface of the trench 4, and then the inside of the trench portion 4 is formed. It is desirable to form the storage electrode 5 at the bottom.
Further, in the present invention, the enlarged diameter portion 1 wider than the storage electrode 5 main body 6 is provided at the upper end of the collar portion 10.
2 is formed.

By adopting such a configuration, a part of the enlarged diameter portion 12 is connected to a part of the diffusion region 13 constituting the element 3 in a self-aligned manner via the capacitance insulating film 7. Things are desirable. On the other hand, the present invention preferably includes a step of connecting the upper surface of the enlarged diameter portion 12 and the diffusion region 13 with a conductive film, for example, a silicide.

Further, in the present invention, a step of providing an ion implantation layer 8 on the inner wall surface of the trench 4 before the formation of the capacitance insulating film 7 in the trench 4 is performed. Is desirable. In the present invention, the ion implantation layer 8 is further extended from the ion implantation layer to form the ion implantation layer 8 in the trench capacitor integrated with an adjacent element of the semiconductor device 100. Another ion-implanted layer 15 may be formed for connection with each other.

In another aspect of the method of manufacturing a semiconductor device according to the present invention, for example, a diffusion layer of a transistor formed in a surface layer of a semiconductor substrate and a storage electrode in a trench are formed on a side wall of the trench. In forming the insulating films of the semiconductor devices separated from each other by the formed insulating film, a film of a substance having a function of controlling the amount of etching back of the insulating film is formed on the semiconductor substrate, and then the trench is formed. Is formed on the semiconductor substrate including the inside of the trench, the film body for forming the insulating film is formed, and then the film body for forming the insulating film is lowered to a height lower than the surface of the semiconductor substrate. A method for manufacturing a semiconductor device which performs etch back may be employed, in which case the substance having a function of controlling the amount of etch back of the insulating film has a lower etching rate than the insulating film. It is desirable that a substance having,
Preferably, the insulating film is a silicon oxide film, and the film of the mask functional material is a silicon film.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a specific example of a semiconductor device according to the present invention.

FIGS. 2A to 2D are cross-sectional views illustrating a procedure of a process in a specific example of a method for manufacturing a semiconductor device according to the present invention.

3 (a) to 3 (c) are cross-sectional views showing the steps of a process in a specific example of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 4A to 2C are cross-sectional views illustrating a procedure of a process in a specific example of a conventional method for manufacturing a semiconductor device.

5 (a) to 5 (c) are cross-sectional views showing a procedure of a process in a specific example of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Substrate surface 3 ... Element 4 ... Trench capacitor 5 ... Storage electrode part 6 ... Body part of storage electrode part 7 ... Capacitive insulating film 8 ... First ion implantation layer 9 ... Upper part of storage electrode part 10 ... Color Part 11: Upper end part of storage electrode part 12 ... Enlarged diameter part 13 ... Diffusion layer part 14 ... Upper end face of collar part 15 ... Second ion implantation layer 16 ... Conductive film 20 ... Element isolation film 23 ... Silicon oxide film 24 ... Silicon Nitride film 25 adjusting oxide film 26 resist 27 first trench 28 second trench 29 cap oxide film 30 gate oxide film 31 gate electrode 32 N ion implanted layer 33 silicon oxide film sidewall 34 ... Silicide film

Claims (15)

[Claims] 1. A semiconductor device comprising: an element such as a transistor formed on a surface of a substrate; and a trench capacitor formed in the substrate below the transistor element. Is a capacitor electrode, a capacitor insulating film covering the outer periphery and a lower end surface of the main body of the storage electrode portion, and a first ion implantation covering a part of the outer periphery of the capacitor insulating film and the lower end surface thereof. Layer, furthermore, a collar portion made of an insulating layer covering the outer periphery of the storage electrode portion main body in the vicinity of the upper portion of the storage electrode portion, provided on the upper end portion of the storage electrode portion, An enlarged diameter portion having a width larger than the width, and the capacitor insulating film provided on a part of an outer peripheral portion of the enlarged diameter portion of the storage electrode portion constitutes the element. Diffusing layer A semiconductor device characterized by being joined to a semiconductor device. 2. The semiconductor device according to claim 1, wherein the position of the upper end surface of the collar portion is lower than the substrate surface position. 3. The semiconductor device according to claim 1, wherein the diffusion layer and the storage electrode constituting the element section are connected to each other only through the capacitor insulating film. 4. The semiconductor device is connected to a part of the first ion implantation layer disposed on an outer peripheral portion of the trench capacitor,
2. The semiconductor device according to claim 1, further comprising a second ion implantation layer connected to an external terminal of the semiconductor device.
4. The semiconductor device according to any one of claims 3 to 3. 5. The semiconductor device according to claim 1, wherein the diffusion layer forming the element and the storage electrode in the trench capacitor are connected by a conductive film formed on a surface of the semiconductor substrate. 5. The semiconductor device according to any one of 4. 6. The semiconductor device according to claim 5, wherein the semiconductor substrate is a silicon semiconductor substrate, and the conductive film is a silicide film. 7. A method of manufacturing a semiconductor device, comprising: forming a device on a surface of a substrate; and forming a trench capacitor including a storage electrode formed in the substrate below the device and corresponding to the device. In forming a trench portion in the substrate and forming an accumulation electrode in the trench portion via an oxide film collar portion on the inner wall portion of the trench portion,
At least a conductive film is provided on the surface of the substrate, and an oxide film for adjusting an oxide film forming the collar portion is provided on the conductive film. A collar portion is formed in the trench portion after forming the trench portion. Forming an oxide film for etching, etching the oxide film for forming the collar portion, and forming the upper portion of the collar portion at a position lower than the substrate surface. A method for manufacturing a semiconductor device, comprising selecting a configuration. 8. The method of manufacturing a semiconductor device according to claim 7, wherein an etching rate of said etch-back adjustment oxide film is selected in relation to an etching rate of said collar portion forming oxide film. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the thickness of said etch-back adjustment oxide film is selected in relation to an etching rate of said collar portion forming oxide film. 10. The method according to claim 7, wherein a storage electrode is formed in the trench after forming a capacitance insulating film on the inner wall surface of the trench after the collar is formed. Of manufacturing a semiconductor device. 11. The method of manufacturing a semiconductor device according to claim 7, wherein an enlarged diameter portion wider than said storage electrode body is formed at an upper end portion of said collar portion. . 12. The device according to claim 7, wherein a part of the enlarged diameter portion is connected to a part of a diffusion region constituting the element in a self-aligned manner via a capacitance insulating film. The manufacturing method of the semiconductor device described in the above. 13. The method according to claim 12, wherein the upper surface of the enlarged diameter portion and the diffusion region are connected by a conductive film. 14. The method of manufacturing a semiconductor device according to claim 7, wherein an ion-implanted layer is provided on an inner wall surface of the trench before forming the capacitance insulating film in the trench. 15. The method according to claim 14, wherein the ion-implanted layer is further extended and connected to an external connection terminal of the semiconductor device.