JP2000031387A - Manufacture of dielectric thin film capacitor - Google Patents

Manufacture of dielectric thin film capacitor

Info

Publication number
JP2000031387A
JP2000031387A JP10198524A JP19852498A JP2000031387A JP 2000031387 A JP2000031387 A JP 2000031387A JP 10198524 A JP10198524 A JP 10198524A JP 19852498 A JP19852498 A JP 19852498A JP 2000031387 A JP2000031387 A JP 2000031387A
Authority
JP
Japan
Prior art keywords
thin film
film
dielectric thin
lower electrode
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10198524A
Other languages
Japanese (ja)
Inventor
Hisato Kato
久人 加藤
Kazuhiro Kusakawa
和大 草川
Yukinori Kawamura
幸則 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP10198524A priority Critical patent/JP2000031387A/en
Publication of JP2000031387A publication Critical patent/JP2000031387A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a small-sized dielectric thin film capacitor having large capacitance and a high breakdown voltage. SOLUTION: A titanium film 12 deposited by a sputtering method, and a lower part electrode composed of a platinum film 13 are formed on a silicon substrate 11. The surface of the electrode is roughened by a method like mechanical polishing. On the roughened surface, a dielectric film 14 of an ATO film formed by alternately laminating alumina and titania by an atomic layer epitaxy method is deposited. By depositing again a platinum film 15, an upper part electrode is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高誘電率を有する
誘電体薄膜を用いた誘電体薄膜コンデンサの製造方法に
関する。
The present invention relates to a method for manufacturing a dielectric thin film capacitor using a dielectric thin film having a high dielectric constant.

【0002】[0002]

【従来の技術】集積回路の発達にともない電子回路の小
型化はますます進展している。これに伴い、各種回路に
必須の回路素子であるコンデンサの小型化も一段と重要
になっている。従来用いられている薄膜コンデンサとし
ては、たとえば特開昭63−49385号公報に示され
ているように、誘電体として酸化けい素(SiO2 )や
酸化タンタル(Ta2 5 )などのような、誘電率がせ
いぜい20以下の材料を用いることが一般的である。ま
た最近では、コンデンサを大容量化するため、比誘電率
の大きい材料として、酸化チタン(以下TiO2 と記
す)や、ジルコニウムチタン酸鉛(Pb(Zr0.5 Ti
0.5 )O3 、以下PZTと略称する),マグネシウムニ
オブ酸鉛(Pb(Mg0.5 Nb0.5 )O3 、以下PMN
と略称する)などの鉛を含む複合ぺロブスカイト酸化物
が検討されている。
2. Description of the Related Art With the development of integrated circuits, the miniaturization of electronic circuits has been more and more advanced. Along with this, miniaturization of capacitors, which are essential circuit elements for various circuits, has become even more important. As a conventional thin film capacitor, for example, as disclosed in JP-A-63-49385, a dielectric such as silicon oxide (SiO 2 ) or tantalum oxide (Ta 2 O 5 ) is used. It is common to use a material having a dielectric constant of at most 20. In recent years, in order to increase the capacity of a capacitor, titanium oxide (hereinafter referred to as TiO 2 ) or lead zirconium titanate (Pb (Zr 0.5 Ti
0.5 ) O 3 (hereinafter abbreviated as PZT), lead magnesium niobate (Pb (Mg 0.5 Nb 0.5 ) O 3 , hereinafter PMN
, Etc.) are being studied.

【0003】[0003]

【発明が解決しようとする課題】薄膜コンデンサを作成
する場合、容量を大きくするためには、電極面積を広く
する、誘電体膜の厚さを薄くする、または比誘電率の大
きな誘電体を使うの三つの方法がある。しかし、電極面
積を広くすると、コンデンサの占有面積が大きくなる。
When a thin film capacitor is manufactured, in order to increase the capacitance, the electrode area is increased, the thickness of the dielectric film is reduced, or a dielectric having a large relative permittivity is used. There are three methods. However, when the electrode area is increased, the area occupied by the capacitor increases.

【0004】誘電体膜の厚さを薄くすると、誘電体の欠
陥などからの電極間ショートの確率が高くなり、薄膜コ
ンデンサの歩留りが落ちる。という問題があった。比誘
電率の大きい材料であるTiO2 や、PZT、PMNに
おいては、耐圧が低いという問題や製造方法に問題があ
り実用化は余り進んでいない。
[0004] When the thickness of the dielectric film is reduced, the probability of a short circuit between the electrodes due to a defect in the dielectric increases, and the yield of the thin film capacitor decreases. There was a problem. TiO 2 , PZT, and PMN, which are materials having a large relative dielectric constant, have a problem of low withstand voltage and a problem of a manufacturing method, and their practical use has not progressed much.

【0005】このような状況に鑑み本発明の目的は、小
型で容量が大きく、耐圧の高い誘電体薄膜コンデンサの
製造方法を提供することにある。
In view of such circumstances, an object of the present invention is to provide a method of manufacturing a dielectric thin film capacitor having a small size, a large capacity, and a high withstand voltage.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
本発明は、基板上に下部電極、誘電体薄膜および上部電
極を重ねて形成する薄膜コンデンサの製造方法におい
て、粗面化された下部電極を有する基板を加熱し、その
下部電極上に反応ガスを流し、表面反応を利用して誘電
体薄膜を形成する熱CVD法によるものとする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a method of manufacturing a thin film capacitor in which a lower electrode, a dielectric thin film and an upper electrode are formed on a substrate. Is heated by heating the substrate, a reactive gas is flowed over the lower electrode, and a thermal thin film is formed by using a surface reaction to form a dielectric thin film.

【0007】下部電極を粗面化することで電極面積を大
きくすることができ、また誘電体薄膜の製造方法として
基板加熱による表面反応を利用した熱CVD法を用いる
ことで、凹凸のある基板上でも均一な膜厚が得られる。
下部電極の粗面化の方法としては、ラッピングフィルム
を用いた機械的研磨、、下部電極材料の真空蒸着法、化
学的なエッチングのいずれかとする。
The surface area of the electrode can be increased by roughening the lower electrode, and by using a thermal CVD method utilizing a surface reaction by heating the substrate as a method of manufacturing a dielectric thin film, the surface of the substrate having irregularities can be formed. However, a uniform film thickness can be obtained.
As a method of roughening the lower electrode, any of mechanical polishing using a wrapping film, a vacuum deposition method of a lower electrode material, and chemical etching is used.

【0008】ラッピングフィルムを用いた機械的研磨
は、もっとも容易な粗面化方法であり、真空蒸着法、化
学的なエッチングは大面積、量産化に適する方法であ
る。熱CVD法としては、原子層エピタキシー法、MO
CVD法のいずれかとする。どちらの方法によっても、
凹凸のある基板上でも均一な膜厚が得られ、耐圧を確保
でき、電極間ショートを防ぐことができる。
[0008] Mechanical polishing using a wrapping film is the easiest surface roughening method, and vacuum evaporation and chemical etching are methods suitable for large-area and mass production. As thermal CVD, atomic layer epitaxy, MO
One of the CVD methods. Either way,
A uniform film thickness can be obtained even on an uneven substrate, a withstand voltage can be secured, and a short circuit between electrodes can be prevented.

【0009】誘電体薄膜がアルミナとチタニアとを交互
に積層した複合膜であることがよい。アルミナは、比誘
電率はそれほど大きくないが、耐圧が高く、チタニアは
比誘電率は大きいが、耐圧が高くない。両者の積層膜と
することによって、比誘電率も大きく、しかも耐圧が高
いコンデンサが実現できる。
Preferably, the dielectric thin film is a composite film in which alumina and titania are alternately laminated. Alumina has a relatively low relative dielectric constant but a high withstand voltage, and titania has a high relative dielectric constant but a low withstand voltage. By using both layers, a capacitor having a large relative dielectric constant and a high withstand voltage can be realized.

【0010】[0010]

【発明の実施の形態】[実施例1]図1は、本発明の方
法にかかる実施例1の誘電体薄膜コンデンサの模擬断面
図である。11は基板として用いた熱酸化膜付きのシリ
コンウェハ、12、13はそれぞれ厚さが20nm、3
00nmのチタン(Ti)膜、白金(Pt)膜である。
14は、Al2 3 とTiO2 とを交互に積層した複合
膜(以下ATO膜と記す)の誘電体薄膜、15は厚さ2
00nmのPtからなる上部電極である。
FIG. 1 is a schematic sectional view of a dielectric thin film capacitor according to a first embodiment of the present invention. 11 is a silicon wafer with a thermal oxide film used as a substrate, 12 and 13 each have a thickness of 20 nm,
A 00 nm titanium (Ti) film and a platinum (Pt) film.
Reference numeral 14 denotes a dielectric thin film of a composite film (hereinafter, referred to as an ATO film) in which Al 2 O 3 and TiO 2 are alternately stacked, and 15 denotes a thickness of 2
The upper electrode is made of Pt of 00 nm.

【0011】以下製造方法を説明する。シリコンウェハ
を熱酸化し、厚さ0.5μmの熱酸化膜11aを形成す
る。次に、いずれもRFマグネトロンスパッタ法でTi
膜12、Pt膜13を堆積する。続いて、ラッピングフ
ィルムを用いて下部電極の粗面化を行う。用いたフィル
ムは、超精密ラッピングフィルム(たとえば住友3M社
製#20000)であり、粗面化後の表面粗さは、約5
0nmである。
Hereinafter, the manufacturing method will be described. A silicon wafer is thermally oxidized to form a thermal oxide film 11a having a thickness of 0.5 μm. Next, in each case, Ti is used by RF magnetron sputtering.
A film 12 and a Pt film 13 are deposited. Subsequently, the lower electrode is roughened using a wrapping film. The film used was an ultraprecision wrapping film (for example, # 20000 manufactured by Sumitomo 3M), and the surface roughness after roughening was about 5
0 nm.

【0012】この後、原子層エピタキシー(ALE)法
により、厚さ各4nmのAl2 3とTiO2 と交互に
計5層積層して、厚さ20nmの誘電体薄14を形成す
る。原料には、三塩化アルミニウム(AlCl3 )、四
塩化チタン(TiCl4 )、純水(H2 O)を用い、基
板温度500℃、圧力0.4Paの条件で、堆積する。
固体のAlCl3 は加熱蒸発させ、液体のTiCl4
2 Oは、アルゴン(Ar)でバブルして輸送する。成
膜速度は、約、0.1nm/秒である。
Thereafter, a total of five layers of Al 2 O 3 and TiO 2 each having a thickness of 4 nm are alternately laminated by atomic layer epitaxy (ALE) to form a dielectric thin film 14 having a thickness of 20 nm. As a raw material, aluminum trichloride (AlCl 3 ), titanium tetrachloride (TiCl 4 ), and pure water (H 2 O) are used, and deposited at a substrate temperature of 500 ° C. and a pressure of 0.4 Pa.
Solid AlCl 3 is heated and evaporated, and liquid TiCl 4 and H 2 O are transported by bubbling with argon (Ar). The deposition rate is about 0.1 nm / sec.

【0013】その上に、上部電極としてRFマグネトロ
ンスパッタ法でPt膜15を形成する。電極直径2mm
のコンデンサとし、周波数1MHzで容量を測定し、下
部電極を粗面化していないもの(比較例1)と比較し
た。その結果容量は、40nFであった。また電極間シ
ョートも発生せず、耐圧は10V以上であった。使用時
の定格電圧は3V程度なので、耐圧は10V以上あれば
十分である。
A Pt film 15 is formed thereon by RF magnetron sputtering as an upper electrode. Electrode diameter 2mm
, And the capacitance was measured at a frequency of 1 MHz, and compared with a capacitor in which the lower electrode was not roughened (Comparative Example 1). As a result, the capacitance was 40 nF. No short circuit occurred between the electrodes, and the breakdown voltage was 10 V or more. Since the rated voltage in use is about 3 V, a withstand voltage of 10 V or more is sufficient.

【0014】比較例1の容量は、28nFであったの
で、比誘電率は約20に相当する。そして、比較例1か
らの約40%の容量増大は、電極面の粗面化の効果とい
うことになる。そして、誘電体膜が熱CVD法で成膜さ
れたため、厚さが薄くても緻密でしかも均一に形成され
たため、電極間ショートも発生しなかったと考えられ
る。
Since the capacitance of Comparative Example 1 was 28 nF, the relative dielectric constant was about 20. The increase in capacity of about 40% from Comparative Example 1 is an effect of roughening the electrode surface. It is considered that since the dielectric film was formed by the thermal CVD method, the film was dense and uniform even though the thickness was small, so that no short circuit between the electrodes occurred.

【0015】[実施例2]図2は、本発明の方法にかか
る第二の実施例の薄膜コンデンサの模擬断面図である。
21は基板として用いた熱酸化膜付きのシリコンウエハ
である。22はRFマグネトロンスパッタ法で形成した
厚さ20nmのTi膜である。23は電子線蒸着法で形
成した導電性の材料の酸化亜鉛(ZnO)である。成膜
温度は300℃、膜厚は500nmとした。表面粗さは
約30nmであり、粗面化された下部電極表面となる。
24は、実施例1と同じ条件で原子層エピタキシー法を
用いて作成したアルミナとチタニアの複合膜(ATO
膜)である。25は、RFマグネトロンスパッタ法にて
形成した厚さ200nmのPt膜である。
Embodiment 2 FIG. 2 is a simulated sectional view of a thin film capacitor according to a second embodiment of the present invention.
Reference numeral 21 denotes a silicon wafer with a thermal oxide film used as a substrate. Reference numeral 22 denotes a 20 nm-thick Ti film formed by an RF magnetron sputtering method. Reference numeral 23 denotes zinc oxide (ZnO), which is a conductive material formed by an electron beam evaporation method. The film formation temperature was 300 ° C., and the film thickness was 500 nm. The surface roughness is about 30 nm, which results in a roughened lower electrode surface.
Reference numeral 24 denotes a composite film of alumina and titania (ATO) formed by atomic layer epitaxy under the same conditions as in Example 1.
Membrane). Reference numeral 25 denotes a Pt film having a thickness of 200 nm formed by an RF magnetron sputtering method.

【0016】実施例1と同様に電極直径2mm、周波数
1MHzの条件で評価した。その結果、約36nFであ
った。また電極間ショートも発生せず、耐圧は10V以
上であった。下部電極表面を粗面化しない比較例の容量
は28nFであったので、本実施例では約30%容量が
増加したことになる。この例でも、下部電極表面を粗面
化したことによって容量が増加し、かつ熱CVD法を用
いたことにより耐圧が確保されたことを意味している。
As in Example 1, evaluation was made under the conditions of an electrode diameter of 2 mm and a frequency of 1 MHz. As a result, it was about 36 nF. No short circuit occurred between the electrodes, and the breakdown voltage was 10 V or more. Since the capacitance of the comparative example in which the lower electrode surface was not roughened was 28 nF, the capacitance was increased by about 30% in this example. This example also means that the capacitance is increased by roughening the surface of the lower electrode, and the withstand voltage is secured by using the thermal CVD method.

【0017】[実施例3]図3は、本発明の方法にかか
る第三の実施例の薄膜コンデンサの模擬断面図である。
31は基板として用いた熱酸化膜付きのシリコンウエハ
である。このウエハをウエットプロセスによりパターニ
ングして凹凸を設け基板として用いた。今回用いた凹凸
パターンは、ライン/スペース1.5μmでアスペクト
比1の順テーパ形状のパターンとした。この上に、RF
マグネトロンスパッタ法で厚さがそれぞれ20nm、2
00nmのTi膜32、Pt膜33を形成し下部電極と
した。34は、誘電体膜34としてMOCVD法を用い
て作成したSrTiO3 膜である。Sr原料としてSr
(THD)2 、Ti原料としてTiO(THD)2 、N
2 Oガスを用い、基板温度:420℃、成膜圧力:13
00Paで、厚さ100nmのSrTiO3 膜を作成し
た。なお、THDは2,2,6,6テトラメチル−3,
5ヘプタンジオンの略である。MOCVD法で成膜後、
酸素雰囲気中で600℃の熱処理を行い結晶化させた。
35は誘電体膜34上にRFマグネトロンスパッタ法に
て形成した厚さ200nmのPt膜であり、上部電極と
なる。
Embodiment 3 FIG. 3 is a simulated sectional view of a thin film capacitor according to a third embodiment of the present invention.
31 is a silicon wafer with a thermal oxide film used as a substrate. This wafer was patterned by a wet process to provide irregularities and used as a substrate. The concavo-convex pattern used this time was a forward tapered pattern having a line / space of 1.5 μm and an aspect ratio of 1. On top of this, RF
The thickness of each is 20 nm and 2 by magnetron sputtering.
A 00 nm Ti film 32 and a Pt film 33 were formed to form a lower electrode. Numeral 34 denotes an SrTiO 3 film formed as a dielectric film 34 by using the MOCVD method. Sr as Sr raw material
(THD) 2 , TiO (THD) 2 , N as Ti raw material
Using 2 O gas, substrate temperature: 420 ° C, film formation pressure: 13
An SrTiO 3 film having a thickness of 100 nm was formed at 00 Pa. In addition, THD is 2,2,6,6 tetramethyl-3,
Abbreviation for 5 heptanedione. After film formation by MOCVD method,
A heat treatment at 600 ° C. was performed in an oxygen atmosphere for crystallization.
Reference numeral 35 denotes a 200 nm thick Pt film formed on the dielectric film 34 by the RF magnetron sputtering method, and serves as an upper electrode.

【0018】作成した薄膜コンデンサは、実施例1と同
様に電極直径2mmで、周波数1MHzの条件で評価
し、凹凸を設けない基板を用いたもの(比較例2)と比
較した。その結果、比較例2では28nFであった容量
が、本実施例では約60nFと約2倍に容量が増加し
た。耐圧は10V以上であった。比誘電率は約100に
相当している。
The prepared thin film capacitor was evaluated under the conditions of an electrode diameter of 2 mm and a frequency of 1 MHz in the same manner as in Example 1, and compared with a thin film capacitor using a substrate having no unevenness (Comparative Example 2). As a result, the capacitance increased from 28 nF in Comparative Example 2 to approximately 60 nF in this example, which was approximately doubled. The withstand voltage was 10 V or more. The relative permittivity corresponds to about 100.

【0019】このように、ウェットプロセスにより基板
に凹凸をつけて下部電極の粗面化をおこなうことも可能
である。誘電体材料としては、上記のATO膜、SrT
iO3 膜に限らず、Pb(Sc 0.5 Ta0.5 )O3 (P
ST)、(Ba0.5 Sr0.5 )TiO3 (BST)、T
2 5 などさまざまな材料が適用可能である。
As described above, the substrate is formed by the wet process.
It is also possible to roughen the lower electrode by making the surface uneven
It is. As the dielectric material, the above-mentioned ATO film, SrT
iOThreeNot only film but Pb (Sc 0.5Ta0.5) OThree(P
ST), (Ba0.5Sr0.5) TiOThree(BST), T
aTwoOFiveVarious materials are applicable.

【0020】[0020]

【発明の効果】以上説明したように本発明の製造方法に
よれば、基板上に下部電極、誘電体薄膜、および上部電
極とを重ねて形成する薄膜コンデンサの製造方法におい
て、下部電極を粗面化した後、基板加熱による表面反応
を利用した熱CVD法により誘電体薄膜を形成すること
により、小型、大容量の誘電体薄膜コンデンサを実現で
きるようになった。
As described above, according to the manufacturing method of the present invention, in a method of manufacturing a thin film capacitor in which a lower electrode, a dielectric thin film and an upper electrode are formed on a substrate, the lower electrode is roughened. Then, by forming a dielectric thin film by a thermal CVD method utilizing a surface reaction due to substrate heating, a small and large-capacity dielectric thin film capacitor can be realized.

【0021】本発明は、小型電源や、IC回路等に組み
込むコンデンサの小型化、軽量化の要求を満たし、電機
機器特に携帯機器の小型化に大きく寄与するものであ
る。
The present invention satisfies the demand for miniaturization and weight reduction of a small power supply and a capacitor incorporated in an IC circuit or the like, and greatly contributes to miniaturization of electric equipment, particularly portable equipment.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の方法にかかる実施例1の誘電体薄膜コ
ンデンサの模擬断面図
FIG. 1 is a simulated cross-sectional view of a dielectric thin film capacitor according to a first embodiment of the present invention.

【図2】本発明の方法にかかる実施例2の誘電体薄膜コ
ンデンサの模擬断面図
FIG. 2 is a simulated cross-sectional view of a dielectric thin film capacitor according to a second embodiment of the present invention.

【図3】本発明の方法にかかる実施例3の誘電体薄膜コ
ンデンサの模擬断面図
FIG. 3 is a simulated sectional view of a dielectric thin film capacitor according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11、21、31 基板 12、22、32 Ti膜 13、33 Pt膜 14、24、34 誘電体膜 15、25、35 Pt膜 23 ZnO膜 11, 21, 31 Substrate 12, 22, 32 Ti film 13, 33 Pt film 14, 24, 34 Dielectric film 15, 25, 35 Pt film 23 ZnO film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 河村 幸則 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 Fターム(参考) 5E082 AB03 BC39 EE05 EE15 EE18 EE19 EE23 EE37 EE42 FF15 FG03 FG19 FG26 FG27 FG41 FG58 KK01 MM24 5F038 AC05 AC10 AC15 AC16 AC17 AC18 EZ20 5F058 BA11 BD02 BD05 BF06 BJ10 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yukinori Kawamura 1-1-1, Tanabe-shinda, Kawasaki-ku, Kawasaki-shi, Kanagawa F-term within Fuji Electric Co., Ltd. 5E082 AB03 BC39 EE05 EE15 EE18 EE19 EE23 EE37 EE42 FF15 FG03 FG19 FG26 FG27 FG41 FG58 KK01 MM24 5F038 AC05 AC10 AC15 AC16 AC17 AC18 EZ20 5F058 BA11 BD02 BD05 BF06 BJ10

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基板上に下部電極、誘電体薄膜および上部
電極を重ねて形成する誘電体薄膜コンデンサの製造方法
において、粗面化された下部電極を有する基板を加熱
し、その下部電極上に反応ガスを流し、表面反応を利用
して誘電体薄膜を形成する熱CVD法によることを特徴
とする誘電体薄膜コンデンサの製造方法。
In a method of manufacturing a dielectric thin film capacitor in which a lower electrode, a dielectric thin film and an upper electrode are formed on a substrate, a substrate having a roughened lower electrode is heated and the lower electrode is placed on the lower electrode. A method of manufacturing a dielectric thin film capacitor, which comprises flowing a reaction gas and forming a dielectric thin film using a surface reaction by a thermal CVD method.
【請求項2】下部電極の粗面化工程がラッピングフィル
ムを用いた機械的研磨であることを特徴とする請求項1
記載の誘電体薄膜コンデンサの製造方法。
2. The method according to claim 1, wherein the step of roughening the lower electrode is mechanical polishing using a wrapping film.
A method for producing the dielectric thin film capacitor according to the above.
【請求項3】下部電極の粗面化工程が下部電極材料の真
空蒸着法であることを特徴とする請求項1記載の誘電体
薄膜コンデンサの製造方法。
3. The method for manufacturing a dielectric thin film capacitor according to claim 1, wherein the step of roughening the lower electrode is a vacuum deposition method of a lower electrode material.
【請求項4】下部電極の粗面化工程が化学的なエッチン
グであることを特徴とする請求項1記載の誘電体薄膜コ
ンデンサの製造方法。
4. The method according to claim 1, wherein the step of roughening the lower electrode is a chemical etching.
【請求項5】熱CVD法が、原子層エピタキシー法であ
ることを特徴とする請求項1ないし4のいずれかに記載
の誘電体薄膜コンデンサの製造方法。
5. The method according to claim 1, wherein the thermal CVD method is an atomic layer epitaxy method.
【請求項6】誘電体薄膜がアルミナとチタニアとを交互
に積層した複合膜であることを特徴とする請求項5記載
の誘電体薄膜コンデンサの製造方法。
6. The method according to claim 5, wherein the dielectric thin film is a composite film in which alumina and titania are alternately laminated.
JP10198524A 1998-07-14 1998-07-14 Manufacture of dielectric thin film capacitor Pending JP2000031387A (en)

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Application Number Priority Date Filing Date Title
JP10198524A JP2000031387A (en) 1998-07-14 1998-07-14 Manufacture of dielectric thin film capacitor

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Publication Number Publication Date
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Family

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Country Status (1)

Country Link
JP (1) JP2000031387A (en)

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