JP2000031387A - Manufacture of dielectric thin film capacitor - Google Patents

Manufacture of dielectric thin film capacitor

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Publication number
JP2000031387A
JP2000031387A JP10198524A JP19852498A JP2000031387A JP 2000031387 A JP2000031387 A JP 2000031387A JP 10198524 A JP10198524 A JP 10198524A JP 19852498 A JP19852498 A JP 19852498A JP 2000031387 A JP2000031387 A JP 2000031387A
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Japan
Prior art keywords
method
thin film
dielectric thin
film
lower electrode
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JP10198524A
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Japanese (ja)
Inventor
Hisato Kato
Yukinori Kawamura
Kazuhiro Kusakawa
久人 加藤
幸則 河村
和大 草川
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Fuji Electric Co Ltd
富士電機株式会社
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Priority to JP10198524A priority Critical patent/JP2000031387A/en
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Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a small-sized dielectric thin film capacitor having large capacitance and a high breakdown voltage. SOLUTION: A titanium film 12 deposited by a sputtering method, and a lower part electrode composed of a platinum film 13 are formed on a silicon substrate 11. The surface of the electrode is roughened by a method like mechanical polishing. On the roughened surface, a dielectric film 14 of an ATO film formed by alternately laminating alumina and titania by an atomic layer epitaxy method is deposited. By depositing again a platinum film 15, an upper part electrode is formed.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、高誘電率を有する誘電体薄膜を用いた誘電体薄膜コンデンサの製造方法に関する。 The present invention relates to a method of manufacturing a dielectric thin film capacitor using the dielectric thin film having a high dielectric constant.

【0002】 [0002]

【従来の技術】集積回路の発達にともない電子回路の小型化はますます進展している。 Miniaturization of electronic circuits with the development of integrated circuit is more and more progress. これに伴い、各種回路に必須の回路素子であるコンデンサの小型化も一段と重要になっている。 Accordingly, it has become increasingly important miniaturization of the capacitor is an essential circuit elements to various circuits. 従来用いられている薄膜コンデンサとしては、たとえば特開昭63−49385号公報に示されているように、誘電体として酸化けい素(SiO 2 )や酸化タンタル(Ta 25 )などのような、誘電率がせいぜい20以下の材料を用いることが一般的である。 The thin film capacitor conventionally used, for example as shown in JP-A-63-49385, such as silicon oxide as a dielectric (SiO 2) and tantalum oxide (Ta 2 O 5) it is common dielectric constant used at most 20 following materials. また最近では、コンデンサを大容量化するため、比誘電率の大きい材料として、酸化チタン(以下TiO 2と記す)や、ジルコニウムチタン酸鉛(Pb(Zr 0.5 Ti Recently, in order to increase the capacity of the capacitor, as a material having a large dielectric constant, titanium oxide (hereinafter referred to as TiO 2) and zirconium lead titanate (Pb (Zr 0.5 Ti
0.5 )O 3 、以下PZTと略称する),マグネシウムニオブ酸鉛(Pb(Mg 0.5 Nb 0.5 )O 3 、以下PMN 0.5) O 3, hereinafter abbreviated as PZT), lead magnesium niobate (Pb (Mg 0.5 Nb 0.5) O 3, less PMN
と略称する)などの鉛を含む複合ぺロブスカイト酸化物が検討されている。 Composite perovskite oxide containing lead, such as abbreviated) have been studied with.

【0003】 [0003]

【発明が解決しようとする課題】薄膜コンデンサを作成する場合、容量を大きくするためには、電極面積を広くする、誘電体膜の厚さを薄くする、または比誘電率の大きな誘電体を使うの三つの方法がある。 When creating a thin film capacitor [0005] In order to increase the capacity to widen the electrode area, the thickness of the dielectric film, or using a larger dielectric having a relative dielectric constant there are three methods. しかし、電極面積を広くすると、コンデンサの占有面積が大きくなる。 However, widening the electrode area, the area occupied by the capacitor becomes large.

【0004】誘電体膜の厚さを薄くすると、誘電体の欠陥などからの電極間ショートの確率が高くなり、薄膜コンデンサの歩留りが落ちる。 [0004] When the thickness of the dielectric film, the higher the probability of a short circuit between electrodes from a defect of the dielectric, fall yield of the thin film capacitor. という問題があった。 There is a problem in that. 比誘電率の大きい材料であるTiO 2や、PZT、PMNにおいては、耐圧が低いという問題や製造方法に問題があり実用化は余り進んでいない。 The ratio TiO 2 or a material having a large dielectric constant, PZT, in PMN, practically there is a problem with the problems and manufacturing method of low withstand voltage has not progressed much.

【0005】このような状況に鑑み本発明の目的は、小型で容量が大きく、耐圧の高い誘電体薄膜コンデンサの製造方法を提供することにある。 An object of the present invention has been made in view of such circumstances, in the capacity in a small large, to provide a method of manufacturing a high withstand voltage dielectric thin film capacitor.

【0006】 [0006]

【課題を解決するための手段】上記課題を解決するため本発明は、基板上に下部電極、誘電体薄膜および上部電極を重ねて形成する薄膜コンデンサの製造方法において、粗面化された下部電極を有する基板を加熱し、その下部電極上に反応ガスを流し、表面反応を利用して誘電体薄膜を形成する熱CVD法によるものとする。 In order to solve the above problems SUMMARY OF THE INVENTION The present invention includes a lower electrode on a substrate, the method of manufacturing the thin film capacitor formed by overlapping the dielectric film and the upper electrode, the roughened bottom electrode heating the substrate having the flow of reactive gas on its lower electrode, by using the surface reaction is intended by the thermal CVD method of forming a dielectric thin film.

【0007】下部電極を粗面化することで電極面積を大きくすることができ、また誘電体薄膜の製造方法として基板加熱による表面反応を利用した熱CVD法を用いることで、凹凸のある基板上でも均一な膜厚が得られる。 [0007] The lower electrode can be increased electrode area by roughening, also by using a thermal CVD method using surface reaction by heating the substrate as a method of manufacturing a dielectric thin film, on a substrate having irregularities But uniform film thickness can be obtained.
下部電極の粗面化の方法としては、ラッピングフィルムを用いた機械的研磨、、下部電極材料の真空蒸着法、化学的なエッチングのいずれかとする。 As the method of roughening the lower electrode, a vacuum deposition method of mechanical polishing ,, lower electrode material using the lapping film, either a chemical etching.

【0008】ラッピングフィルムを用いた機械的研磨は、もっとも容易な粗面化方法であり、真空蒸着法、化学的なエッチングは大面積、量産化に適する方法である。 [0008] mechanical polishing using lapping film is easiest roughening method, a vacuum deposition method, chemical etching is a large area, a method suitable for mass production. 熱CVD法としては、原子層エピタキシー法、MO The thermal CVD method, an atomic layer epitaxy, MO
CVD法のいずれかとする。 And any of the CVD method. どちらの方法によっても、 By either method,
凹凸のある基板上でも均一な膜厚が得られ、耐圧を確保でき、電極間ショートを防ぐことができる。 Even an irregular substrate obtained uniform thickness, can be secured breakdown voltage, it is possible to prevent short circuit between electrodes.

【0009】誘電体薄膜がアルミナとチタニアとを交互に積層した複合膜であることがよい。 [0009] it is possible dielectric thin film is a composite film of alternately laminated alumina and titania. アルミナは、比誘電率はそれほど大きくないが、耐圧が高く、チタニアは比誘電率は大きいが、耐圧が高くない。 Alumina is not a dielectric constant so large, high breakdown voltage, titania is the relative dielectric constant greater, withstand voltage is not high. 両者の積層膜とすることによって、比誘電率も大きく、しかも耐圧が高いコンデンサが実現できる。 By the both laminated film, the dielectric constant is large, moreover withstand voltage can be achieved is high capacitor.

【0010】 [0010]

【発明の実施の形態】[実施例1]図1は、本発明の方法にかかる実施例1の誘電体薄膜コンデンサの模擬断面図である。 DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] FIG. 1 is a simulated cross sectional view of a dielectric thin film capacitor of Example 1 according to the method of the present invention. 11は基板として用いた熱酸化膜付きのシリコンウェハ、12、13はそれぞれ厚さが20nm、3 11 with a thermal oxidation film of the silicon wafer used as substrate, respectively the thickness 12, 13 20 nm, 3
00nmのチタン(Ti)膜、白金(Pt)膜である。 00nm of titanium (Ti) film, a platinum (Pt) film.
14は、Al 23とTiO 2とを交互に積層した複合膜(以下ATO膜と記す)の誘電体薄膜、15は厚さ2 14, Al 2 O 3 and the dielectric thin film of a composite film obtained by laminating a TiO 2 are alternately (hereinafter referred to as ATO film), 15 a thickness of 2
00nmのPtからなる上部電極である。 An upper electrode made of Pt of nm.

【0011】以下製造方法を説明する。 [0011] following the manufacturing method will be described. シリコンウェハを熱酸化し、厚さ0.5μmの熱酸化膜11aを形成する。 The silicon wafer was thermally oxidized to form a thermal oxide film 11a having a thickness of 0.5 [mu] m. 次に、いずれもRFマグネトロンスパッタ法でTi Next, Ti either by RF magnetron sputtering
膜12、Pt膜13を堆積する。 Depositing a film 12, Pt film 13. 続いて、ラッピングフィルムを用いて下部電極の粗面化を行う。 Subsequently, a roughening of the lower electrode by using a lapping film. 用いたフィルムは、超精密ラッピングフィルム(たとえば住友3M社製#20000)であり、粗面化後の表面粗さは、約5 Film used was ultra-precision lapping film (e.g., manufactured by Sumitomo 3M # 20000), the surface roughness after roughening, about 5
0nmである。 It is 0nm.

【0012】この後、原子層エピタキシー(ALE)法により、厚さ各4nmのAl 23とTiO 2と交互に計5層積層して、厚さ20nmの誘電体薄14を形成する。 [0012] Thereafter, by atomic layer epitaxy (ALE) method, by alternately laminating the Al 2 O 3 and TiO 2 in the thickness 4nm five layers, a dielectric thin 14 thick 20 nm. 原料には、三塩化アルミニウム(AlCl 3 )、四塩化チタン(TiCl 4 )、純水(H 2 O)を用い、基板温度500℃、圧力0.4Paの条件で、堆積する。 The raw material, aluminum trichloride (AlCl 3), titanium tetrachloride (TiCl 4), with pure water (H 2 O), a substrate temperature of 500 ° C., under a pressure of 0.4 Pa, is deposited.
固体のAlCl 3は加熱蒸発させ、液体のTiCl 4とH 2 Oは、アルゴン(Ar)でバブルして輸送する。 AlCl 3 in solid vaporized by heating, TiCl 4 and of H 2 O liquid is transported bubble with argon (Ar). 成膜速度は、約、0.1nm/秒である。 The deposition rate, about, is 0.1nm / sec.

【0013】その上に、上部電極としてRFマグネトロンスパッタ法でPt膜15を形成する。 [0013] thereon, to form a Pt film 15 by the RF magnetron sputtering method as an upper electrode. 電極直径2mm Electrode diameter 2mm
のコンデンサとし、周波数1MHzで容量を測定し、下部電極を粗面化していないもの(比較例1)と比較した。 A capacitor to measure the capacitance at frequency 1 MHz, and compared those not roughened lower electrode (Comparative Example 1). その結果容量は、40nFであった。 As a result volume was 40nF. また電極間ショートも発生せず、耐圧は10V以上であった。 The short circuit between electrodes does not occur, the withstand voltage were 10V or more. 使用時の定格電圧は3V程度なので、耐圧は10V以上あれば十分である。 Since the rated voltage at the time of use of about 3V, the breakdown voltage is sufficient if more than 10V.

【0014】比較例1の容量は、28nFであったので、比誘電率は約20に相当する。 [0014] capacity of Comparative Example 1, since there was a 28NF, relative dielectric constant corresponds to about 20. そして、比較例1からの約40%の容量増大は、電極面の粗面化の効果ということになる。 Then, about 40% of the capacity increase from Comparative Example 1, it comes to roughening effect of the electrode surface. そして、誘電体膜が熱CVD法で成膜されたため、厚さが薄くても緻密でしかも均一に形成されたため、電極間ショートも発生しなかったと考えられる。 Since the dielectric film is deposited by a thermal CVD method, which is also dense and uniform to form small thickness, short circuit between electrodes is also considered to have not occurred.

【0015】[実施例2]図2は、本発明の方法にかかる第二の実施例の薄膜コンデンサの模擬断面図である。 [0015] [Embodiment 2] FIG 2 is a simulated cross-sectional view of a thin film capacitor of the second embodiment according to the method of the present invention.
21は基板として用いた熱酸化膜付きのシリコンウエハである。 21 is a silicon wafer with a thermally oxidized film used as a substrate. 22はRFマグネトロンスパッタ法で形成した厚さ20nmのTi膜である。 22 is a Ti film having a thickness of 20nm formed by the RF magnetron sputtering method. 23は電子線蒸着法で形成した導電性の材料の酸化亜鉛(ZnO)である。 23 is a zinc oxide conductive formed by electron beam vapor deposition material (ZnO). 成膜温度は300℃、膜厚は500nmとした。 The film forming temperature is 300 ℃, the film thickness was 500nm. 表面粗さは約30nmであり、粗面化された下部電極表面となる。 The surface roughness was about 30 nm, the roughened surface of the lower electrode.
24は、実施例1と同じ条件で原子層エピタキシー法を用いて作成したアルミナとチタニアの複合膜(ATO 24, the composite membrane of alumina and titania were prepared using atomic layer epitaxy in the same conditions as in Example 1 (ATO
膜)である。 It is a film). 25は、RFマグネトロンスパッタ法にて形成した厚さ200nmのPt膜である。 25 is a Pt film having a thickness of 200nm was formed by RF magnetron sputtering.

【0016】実施例1と同様に電極直径2mm、周波数1MHzの条件で評価した。 [0016] Similarly electrode diameter 2mm as in Example 1, was evaluated under the conditions of frequency 1 MHz. その結果、約36nFであった。 As a result, it was about 36nF. また電極間ショートも発生せず、耐圧は10V以上であった。 The short circuit between electrodes does not occur, the withstand voltage were 10V or more. 下部電極表面を粗面化しない比較例の容量は28nFであったので、本実施例では約30%容量が増加したことになる。 Since the capacity of the comparative example without the lower electrode surface roughening was 28NF, in the present embodiment will be about 30% capacity is increased. この例でも、下部電極表面を粗面化したことによって容量が増加し、かつ熱CVD法を用いたことにより耐圧が確保されたことを意味している。 In this example, it means that the withstand voltage is secured by the capacity is increased by the roughened surface of the lower electrode, and using a thermal CVD method.

【0017】[実施例3]図3は、本発明の方法にかかる第三の実施例の薄膜コンデンサの模擬断面図である。 [0017] [Embodiment 3] FIG. 3 is a simulated cross-sectional view of a thin film capacitor of the third embodiment according to the method of the present invention.
31は基板として用いた熱酸化膜付きのシリコンウエハである。 31 is a silicon wafer with a thermally oxidized film used as a substrate. このウエハをウエットプロセスによりパターニングして凹凸を設け基板として用いた。 It was used as a substrate provided with uneven The wafer is patterned by a wet process. 今回用いた凹凸パターンは、ライン/スペース1.5μmでアスペクト比1の順テーパ形状のパターンとした。 Uneven pattern using this time, was the pattern of the forward tapered shape of an aspect ratio of 1 in the line / space 1.5μm. この上に、RF On this, RF
マグネトロンスパッタ法で厚さがそれぞれ20nm、2 Thickness respectively magnetron sputtering 20 nm, 2
00nmのTi膜32、Pt膜33を形成し下部電極とした。 Forming a Ti film 32, Pt film 33 of 00nm was lower electrode. 34は、誘電体膜34としてMOCVD法を用いて作成したSrTiO 3膜である。 34 is a SrTiO 3 film produced by MOCVD as a dielectric film 34. Sr原料としてSr Sr as Sr material
(THD) 2 、Ti原料としてTiO(THD) 2 、N (THD) 2, Ti raw material as TiO (THD) 2, N
2 Oガスを用い、基板温度:420℃、成膜圧力:13 Using 2 O gas, substrate temperature: 420 ° C., film formation pressure: 13
00Paで、厚さ100nmのSrTiO 3膜を作成した。 In 00Pa, it was to create a SrTiO 3 film having a thickness of 100nm. なお、THDは2,2,6,6テトラメチル−3, Incidentally, THD is 2,2,6,6-tetramethyl-3,
5ヘプタンジオンの略である。 5 is a schematic of heptane-dione. MOCVD法で成膜後、 After the film formation by the MOCVD method,
酸素雰囲気中で600℃の熱処理を行い結晶化させた。 In an oxygen atmosphere to crystallize by heat treatment of 600 ° C..
35は誘電体膜34上にRFマグネトロンスパッタ法にて形成した厚さ200nmのPt膜であり、上部電極となる。 35 is a Pt film having a thickness of 200nm was formed by RF magnetron sputtering on the dielectric film 34, the upper electrode.

【0018】作成した薄膜コンデンサは、実施例1と同様に電極直径2mmで、周波数1MHzの条件で評価し、凹凸を設けない基板を用いたもの(比較例2)と比較した。 The thin film capacitor is created, in likewise electrode diameter 2mm as in Example 1, evaluated at a frequency of 1 MHz, and compared those using a substrate without the irregularities (Comparative Example 2). その結果、比較例2では28nFであった容量が、本実施例では約60nFと約2倍に容量が増加した。 As a result, the capacity was 28nF In Comparative Example 2, in this example capacitance increases to about 60nF and about 2-fold. 耐圧は10V以上であった。 Breakdown voltage was 10V or more. 比誘電率は約100に相当している。 The dielectric constant is equivalent to approximately 100.

【0019】このように、ウェットプロセスにより基板に凹凸をつけて下部電極の粗面化をおこなうことも可能である。 [0019] Thus, it is possible to perform the roughening of the lower electrode with the uneven substrate by a wet process. 誘電体材料としては、上記のATO膜、SrT Dielectric as the material, the above ATO film, SRT
iO 3膜に限らず、Pb(Sc iO 3 is not limited to film, Pb (Sc 0.5 Ta 0.5 )O 3 (P 0.5 Ta 0.5) O 3 (P
ST)、(Ba 0.5 Sr 0.5 )TiO 3 (BST)、T ST), (Ba 0.5 Sr 0.5 ) TiO 3 (BST), T
25などさまざまな材料が適用可能である。 a 2 O 5 and various materials are possible applications.

【0020】 [0020]

【発明の効果】以上説明したように本発明の製造方法によれば、基板上に下部電極、誘電体薄膜、および上部電極とを重ねて形成する薄膜コンデンサの製造方法において、下部電極を粗面化した後、基板加熱による表面反応を利用した熱CVD法により誘電体薄膜を形成することにより、小型、大容量の誘電体薄膜コンデンサを実現できるようになった。 According to the manufacturing method of the present invention as described above, according to the present invention, the lower electrode on a substrate, method of manufacturing a thin film capacitor formed by overlapping the dielectric film, and an upper electrode, a lower electrode roughened after ized by forming a dielectric thin film by the thermal CVD method using surface reaction with the substrate heated, becomes small, it can be realized a dielectric thin film capacitor having a large capacity.

【0021】本発明は、小型電源や、IC回路等に組み込むコンデンサの小型化、軽量化の要求を満たし、電機機器特に携帯機器の小型化に大きく寄与するものである。 [0021] The present invention is a small power and miniaturization of the capacitor incorporated in the IC circuit or the like, meet the requirements of light weight, and contributes greatly to the miniaturization of electrical equipment, especially portable devices.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の方法にかかる実施例1の誘電体薄膜コンデンサの模擬断面図 Simulated cross-sectional view of the dielectric thin film capacitor of Example 1 according to the method of the invention, FIG

【図2】本発明の方法にかかる実施例2の誘電体薄膜コンデンサの模擬断面図 Simulated cross-sectional view of the dielectric thin film capacitor according to the second embodiment of the method of the present invention; FIG

【図3】本発明の方法にかかる実施例3の誘電体薄膜コンデンサの模擬断面図 [3] the simulated cross-sectional view of a dielectric thin film capacitor according to the third embodiment of the method of the present invention

【符号の説明】 DESCRIPTION OF SYMBOLS

11、21、31 基板 12、22、32 Ti膜 13、33 Pt膜 14、24、34 誘電体膜 15、25、35 Pt膜 23 ZnO膜 11, 21, 31 substrate 12, 22, 32 Ti film 13, 33 Pt film 14, 24, 34 dielectric layer 15, 25, 35 Pt film 23 ZnO film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 河村 幸則 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 Fターム(参考) 5E082 AB03 BC39 EE05 EE15 EE18 EE19 EE23 EE37 EE42 FF15 FG03 FG19 FG26 FG27 FG41 FG58 KK01 MM24 5F038 AC05 AC10 AC15 AC16 AC17 AC18 EZ20 5F058 BA11 BD02 BD05 BF06 BJ10 ────────────────────────────────────────────────── ─── front page of the continuation (72) inventor Yukinori Kawamura Kawasaki City, Kanagawa Prefecture Kawasaki-ku, Tanabeshinden No. 1 No. 1 Fuji Electric Co., Ltd. in the F-term (reference) 5E082 AB03 BC39 EE05 EE15 EE18 EE19 EE23 EE37 EE42 FF15 FG03 FG19 FG26 FG27 FG41 FG58 KK01 MM24 5F038 AC05 AC10 AC15 AC16 AC17 AC18 EZ20 5F058 BA11 BD02 BD05 BF06 BJ10

Claims (6)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】基板上に下部電極、誘電体薄膜および上部電極を重ねて形成する誘電体薄膜コンデンサの製造方法において、粗面化された下部電極を有する基板を加熱し、その下部電極上に反応ガスを流し、表面反応を利用して誘電体薄膜を形成する熱CVD法によることを特徴とする誘電体薄膜コンデンサの製造方法。 1. A lower electrode on a substrate, the method for producing a dielectric thin film capacitor formed by overlapping the dielectric thin film and an upper electrode, a substrate having a roughened lower electrode heated, on the lower electrode flowing a reactive gas, the production method of the dielectric thin film capacitor characterized in that by using a surface reaction thermal CVD method of forming a dielectric thin film.
  2. 【請求項2】下部電極の粗面化工程がラッピングフィルムを用いた機械的研磨であることを特徴とする請求項1 2. A method according to claim 1, roughening step of the lower electrode is characterized by a mechanical polishing using lapping film
    記載の誘電体薄膜コンデンサの製造方法。 Method for producing a dielectric thin film capacitor according.
  3. 【請求項3】下部電極の粗面化工程が下部電極材料の真空蒸着法であることを特徴とする請求項1記載の誘電体薄膜コンデンサの製造方法。 3. The method for producing a dielectric thin film capacitor according to claim 1, wherein the roughening process of the lower electrode is a vacuum deposition method of the lower electrode material.
  4. 【請求項4】下部電極の粗面化工程が化学的なエッチングであることを特徴とする請求項1記載の誘電体薄膜コンデンサの製造方法。 4. A manufacturing method of a dielectric thin film capacitor according to claim 1, wherein the roughening process of the lower electrode is a chemical etching.
  5. 【請求項5】熱CVD法が、原子層エピタキシー法であることを特徴とする請求項1ないし4のいずれかに記載の誘電体薄膜コンデンサの製造方法。 5. A thermal CVD method, a manufacturing method of the dielectric thin film capacitor according to any one of claims 1 to 4, characterized in that an atomic layer epitaxy.
  6. 【請求項6】誘電体薄膜がアルミナとチタニアとを交互に積層した複合膜であることを特徴とする請求項5記載の誘電体薄膜コンデンサの製造方法。 6. The method for producing a dielectric thin film capacitor according to claim 5, wherein the dielectric thin film is a composite film of alternately laminated alumina and titania.
JP10198524A 1998-07-14 1998-07-14 Manufacture of dielectric thin film capacitor Pending JP2000031387A (en)

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