JP2000031230A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be surely judged defective when a semiconductor chip is chipped. SOLUTION: A wiring 11 is formed on the periphery of a finalized chip 10, and a detection signal generating circuit 12 and an enabling signal generating circuit 13 are provided. The detection signal generating circuit 12 feeds a detection signal ZENF to the wiring 11. The enabling signal generating circuit 13 generates an enabling signal EN of L-level when the circuit 13 receives no detection signal ZENF. An input buffer 14 and an output buffer 16 are stopped when they receive the enabling signal EN of L level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of detecting the presence or absence of a chip in a semiconductor chip.

[0002]

2. Description of the Related Art Normally, a plurality of semiconductor chips are produced by photolithography on a single wafer and cut into individual chips. For this reason, semiconductor chips include a production chip section on which circuits and the like for operating the chip are laid out, and a dicing section for cutting a plurality of chips into individual chips.

[0003]

In the case of a circular wafer,
At the time of cutting, semiconductor chips may be chipped in the outer peripheral portion of the wafer.

When a main circuit is present in the missing portion, the chip does not operate normally, and it is necessary to reliably make the chip defective. Even when there is no main circuit in the chipped part, it is good to consider the chip reliability, but it is good to make the chip defective, but in this case the chip may operate normally, so it is not necessarily defective May not be possible.

[0005] As means for detecting such chipping of a chip, Japanese Patent Application Laid-Open Nos.
9. Japanese Patent Application Laid-Open No. Hei 8-139057 discloses an example in which a wiring is provided on an outer peripheral portion of a chip and the wiring is cut by chipping of the chip to detect chipping of the chip. However, these examples only detect the presence / absence of chipping of the chip, and cannot make the chip defective.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device which can reliably make a semiconductor chip defective when a chip is generated. It is to be.

[0007]

A semiconductor device according to one aspect of the present invention includes a semiconductor chip, wiring, and control means. The semiconductor chip has an internal circuit. The wiring is formed on the periphery of the semiconductor chip. The control means
The circuit is provided on the semiconductor chip and operates the internal circuit when the wiring is not broken, and stops the internal circuit when the wiring is broken.

In the above-described semiconductor device, if the periphery of the semiconductor chip is chipped, the wiring is broken. When the wiring is broken, the control circuit stops the internal circuit. This allows
When a chip is generated in a semiconductor chip, the internal circuit can be stopped to make the chip surely defective.

Preferably, the control means includes a detection signal generation means and an enable signal generation means, and the internal circuit operates when the enable signal is active and stops when the enable signal is inactive. The detection signal generation means generates a detection signal and supplies it to one end of the wiring. The enable signal generating means is connected to the other end of the wiring and generates an active enable signal when receiving a detection signal through the wiring, and generates an inactive enable signal when not receiving the detection signal.

In the above-described semiconductor device, when there is no chip on the periphery of the chip, the enable signal generation circuit receives the detection signal through the wiring and generates an active enable signal. The internal circuit operates by the enable signal. On the other hand, if chipping occurs at the periphery of the chip, the wiring is broken. Therefore, the enable signal generating means does not receive the detection signal and generates an inactive enable signal. The internal circuit is stopped by this enable signal. Thus, when a chip is generated in the semiconductor chip, the internal circuit is stopped, and the chip can be reliably made defective.

Preferably, the detection signal generation means supplies a ground voltage to a wiring, and the enable signal generation means includes a precharge means and a latch circuit. The precharge means charges the wiring to a power supply voltage for a predetermined time after the power is turned on. The latch circuit latches the voltage of the wiring.

In the above-described semiconductor device, if the chip is not chipped, the wiring is at the ground voltage even after the semiconductor device is turned on. The ground voltage is latched by a latch circuit, and the enable signal generating means generates an active enable signal in accordance with the output of the latch circuit. The internal circuit operates by the enable signal. On the other hand, if chipping occurs at the periphery of the chip, the wiring is broken. When the power of the semiconductor device is turned on in this state, the wiring from the disconnection portion to the enable signal generation means is charged to the power supply voltage by the precharge means. The power supply voltage is latched by a latch circuit, and the enable signal generating means generates an inactive enable signal according to the output of the latch circuit. The internal circuit is stopped by this enable signal.
Thus, when a chip is generated in the semiconductor chip, the internal circuit is stopped, and the chip can be reliably made defective.

A semiconductor device according to another aspect of the present invention includes a semiconductor chip, first to fourth wirings,
To 4th detection signal generation means and enable signal generation means. The semiconductor chip has an internal circuit. The first to fourth wirings are formed corresponding to the four corners of the semiconductor chip. First to fourth detection signal generation means generates a detection signal and supplies it to one end of the first to fourth wirings. The enable signal generating means is connected to the other end of the first to fourth wirings, generates an active enable signal when receiving a detection signal through each of the first to fourth wirings, and inactivates otherwise. Generate an enable signal. Further, the internal circuit operates when the enable signal is active and stops when the enable signal is inactive.

In the above-mentioned semiconductor device, when any of the four corners of the chip is not chipped, the enable signal generation circuit receives the detection signal through each of the first to fourth wirings and activates the active enable signal. Generate a signal.
The internal circuit operates by the enable signal. on the other hand,
If any of the four corners of the chip is chipped, the corresponding one of the first to fourth wires is disconnected. As a result, the enable signal generating means does not receive the detection signal through the disconnected wire, and generates an inactive enable signal. The internal circuit is stopped by this enable signal. Thus, when a chip is generated in the semiconductor chip, the internal circuit is stopped, and the chip can be reliably made defective.

Preferably, the first to fourth detection signal generating means supplies a ground voltage to the first to fourth wirings,
The enable signal generating means includes: a precharge means;
The circuit includes first to fourth latch circuits and an AND circuit. The precharge means is provided for a predetermined time after the power is turned on, for the first to fourth times.
To the power supply voltage. The first to fourth latch circuits latch the voltages of the first to fourth wirings, respectively. The AND circuit outputs an enable signal in response to output signals of the first to fourth latch circuits.

In the above-mentioned semiconductor device, if any of the four corners of the chip is not chipped, the first to fourth wirings remain at the ground voltage even after the power of the semiconductor device is turned on. . The ground voltage is latched by the first to fourth latch circuits, and the enable signal generating means generates an active enable signal in accordance with the outputs of the first to fourth latch circuits. The internal circuit operates by the enable signal. On the other hand, if any of the four corners of the chip is chipped, the corresponding one of the first to fourth wires is disconnected. When the power supply of the semiconductor device is turned on in this state, the corresponding enable signal generating means from the broken portion of the corresponding wiring is charged to the power supply voltage by the precharge means. This power supply voltage is latched by a latch circuit. On the other hand, the wires that are not disconnected have the ground voltage, and the corresponding latch circuit latches the ground voltage. The enable signal generating means generates an inactive enable signal according to the outputs of these latch circuits. The internal circuit is stopped by this enable signal. Thus, when a chip is generated in the semiconductor chip, the internal circuit is stopped, and the chip can be reliably made defective.

Preferably, the internal circuit includes an input buffer. The input buffer generates an internal signal in response to an external signal when the enable signal is active, and stops when the enable signal is inactive.

Preferably, the internal circuit includes an output buffer. The output buffer generates an external signal in response to the internal signal when the enable signal is active, and stops when the enable signal is inactive.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a block diagram showing an overall configuration of a semiconductor chip according to a first embodiment of the present invention. Referring to FIG. 1, the semiconductor chip includes a dicing unit 1 and a production chip 10.

The dicing unit 1 is for cutting a plurality of semiconductor chips photoengraved on one wafer into individual semiconductor chips. The production chip 10 includes the wiring 1
1, a detection signal generation circuit 12, an enable signal generation circuit 13, pads Pi and Po, an input buffer 14,
It includes a signal processing circuit 15 and an output buffer 16.

The wiring 11 is formed on the periphery of the production chip 10. The detection signal generation circuit 12 generates a detection signal ZENF and supplies it to one end of the wiring 11. The enable signal generation circuit 13 is connected to the other end of the wiring 11, generates an H (logic high) level enable signal EN when receiving the detection signal ZENF through the wiring 11, and outputs the detection signal ZENF.
When it is not received, an enable signal EN of L (logic low) level is generated. The pad Pi is connected to an external input pin (not shown) and receives an external input signal ESi from the outside. The input buffer 14 has an H level enable signal E
N, the internal signal I according to the external input signal ESi
It generates Si and stops when it receives an L-level enable signal EN. The signal processing circuit 15 performs signal processing according to the internal signal ISi and outputs an internal signal ISo. Output buffer 16 generates external output signal ESo in response to internal signal ISo when receiving H-level enable signal EN, and stops when receiving L-level enable signal EN. Pad Po receives an external output signal ESo from output buffer 16, and is connected to an external output pin (not shown).

FIG. 2 is a block diagram showing an internal configuration of the detection signal generation circuit 12 and the enable signal generation circuit 13 shown in FIG. Referring to FIG. 2, in detection signal generation circuit 12, wiring 11 is connected to ground node GND. Therefore, L-level detection signal ZENF is supplied from detection signal generation circuit 12 to one end of wiring 11. Enable signal generating circuit 13 includes a P-channel MOS transistor PT and inverters IV1 and IV2.
P channel MOS transistor PT is connected to power supply node Vd
and a power-on reset signal / POR received at the gate. Inverters IV1 and IV2 constitute a latch circuit, and invert and hold the voltage of wiring 11. The output from the latch circuit composed of the inverters IV1 and IV2 becomes the enable signal EN.

Next, the operation of the semiconductor chip configured as described above will be described in the case where (a) the production chip 10 has no chipping and (b) when the production chip 10 has chipping.

(A) When there is no chip in the production chip 10 The detection signal generation circuit 12 supplies an L level detection signal ZENF to the wiring 11, and the wiring 11 becomes L level.

Next, referring to FIG. 3, when the power of the semiconductor chip is turned on at time t0, power supply voltage Vdd rises. The power-on reset signal / POR goes low for a predetermined time after the power is turned on, and the P-channel MOS transistor PT is turned on. Thereafter, power-on reset signal / POR attains H level, and P-channel MOS transistor PT is turned off. Since the L-level detection signal ZENF is inverted by the inverter IV1, the enable signal E
N goes to the H level. In response to the enable signal EN, the input buffer 14 and the output buffer 16 operate.

(B) When there is a chip in the production chip 10 Consider a case where a chip occurs in the semiconductor chip at A0-A1 in FIG.

At this time, the wiring 11 is disconnected as shown in FIG. As a result, the L-level detection signal ZE is applied to the wiring 11a between the detection signal generation circuit 12 and the disconnection portion a.
Although NF is supplied, the detection signal ZENF is not supplied to the wiring 11b between the disconnection portion b and the enable signal generation circuit 13, and the line 11b is in a floating state.

Next, referring to FIG. 5, when the power of the semiconductor chip is turned on at time t0, power supply voltage Vdd rises. The power-on reset signal / POR goes low for a predetermined time after the power is turned on, and the P-channel MOS transistor PT is turned on. As a result, the wiring 11b from the disconnection portion b to the enable signal generation circuit 13 is precharged to the power supply voltage Vdd (H level). After that, the power-on reset signal / POR becomes H level and the P-channel MOS transistor PT turns off, but the wiring 11b from the disconnection part b to the enable signal generation circuit 13 remains at H level. Since the H level detection signal ZENF is inverted by the inverter IV1, the enable signal EN is at L level. Upon receiving this enable signal EN, the input buffer 14 and the output buffer 16 stop. As a result, the semiconductor chip does not accept an input from outside and does not output to the outside, and thus does not operate normally. In this way, by stopping the operation of the semiconductor chip, it is possible to reliably make the chip defective.

As described above, according to the first embodiment, since the wiring 11, the detection signal generation circuit 12, and the enable signal generation circuit 13 are provided, if the periphery of the production chip 10 is chipped, the input buffer 14 and the output buffer 16 stop. Thereby, when a chip is generated in a semiconductor chip, the chip can be reliably made defective.

Although the power-on reset signal / POR is generated inside the semiconductor chip here, it may be used as a reset signal from outside the semiconductor chip.

Although the input buffer 14 and the output buffer 16 are stopped when the semiconductor chip is chipped, it may be another main part in the operation of the semiconductor chip.

[Second Embodiment] Usually, a semiconductor chip is rectangular, and chip chipping occurs at any one of the four corners. Therefore, it is not always necessary to provide wiring on the entire periphery of the chip as described in the first embodiment.

FIG. 6 is a block diagram showing an overall configuration of a semiconductor chip according to the second embodiment of the present invention. Referring to FIG. 6, this semiconductor chip includes dicing unit 1 and production chip 20.

The production chip 20 includes wirings 21-24, detection signal generation circuits 31-34, enable signal generation circuits 40, pads Pi and Po, an input buffer 14, a signal processing circuit 15, and an output buffer 16 And

Each of the wirings 21-24 is connected to the production chip 1
0 are formed on the periphery of the first to fourth corners of the four corners. The detection signal generation circuits 31-34 generate the detection signals ZENF1-ZENF4, respectively, and
24 to one end. Enable signal generation circuit 40
Is connected to the other end of the wiring 21-24, and the wiring 21-24
, Generate an H (logic high) level enable signal EN when receiving the detection signals ZENF1 through ZENF4 through each of them, and otherwise generate an L (logic low) level enable signal EN.

FIG. 7 is a block diagram showing an internal configuration of detection signal generation circuits 31-34 and enable signal generation circuit 40 shown in FIG. Referring to FIG. 7, each of detection signal generation circuits 31-34 has a corresponding wiring 21-2.
4 is connected to ground node GND. Accordingly, L-level detection signals ZENF1-ZENF4 are supplied from detection signal generation circuits 31-34 to one ends of corresponding wirings 21-24. The enable signal generation circuit 40 includes P-channel MOS transistors PT1 to PT4 and an inverter IV.
ij (i = 1-4, j = 1, 2) and the NAND circuit 41
And an inverter 42. P-channel MOS transistors PT1-PT4 are connected between power supply node Vdd and corresponding wires 21-24, and receive power-on reset signal / POR at their gates. Inverters IVi1, I
Vi2 (i = 1-4) constitutes a latch circuit, and inverts and holds the voltage of the corresponding wiring 21-24. Outputs from the latch circuits formed by the inverters IVi1 and IVi2 (i = 1 to 4) are respectively provided as enable signals E
N1-EN4. NAND circuit 41 and inverter 42 output the logical product of enable signals EN1-EN4. This logical product becomes the enable signal EN.

Next, the operation of the semiconductor chip configured as described above will be described with respect to (a) the case where the production chip 20 has no chip and (b) the case where the production chip 20 has chip.

(A) When there is no chip in the production chip 20 Referring to FIG. 8, a latch composed of inverters IVi1 and IVi2 (i = 1-4) in the same manner as shown in the first embodiment. H level enable signal EN from the circuit
1-EN4 is output. Therefore, an H-level enable signal EN is output from enable signal generation circuit 40. In response to the enable signal EN, the input buffer 14 and the output buffer 16 operate.

(B) When there is a chip in the production chip 20 Consider a case where the semiconductor chip is chipped at the portion B0-B1 in FIG.

Referring to FIG. 9, at this time, wiring 21 is disconnected, and enable signal E is turned on in the same manner as shown in FIG.
N1 is at the L level. On the other hand, as in the case of (a), the enable signals EN2-EN4 are at the H level.
Therefore, an L-level enable signal EN is output from enable signal generation circuit 40. Upon receiving this enable signal EN, the input buffer 14 and the output buffer 16 stop. As a result, the semiconductor chip does not accept an input from outside and does not output to the outside, and thus does not operate normally. In this way, by stopping the operation of the semiconductor chip, it is possible to reliably make the chip defective.

As described above, according to the second embodiment, the wires 21-24 and the detection signal generation circuits 31-34
And the enable signal generation circuit 40, when any one of the four corners of the production chip 10 is chipped, the input buffer 14 and the output buffer 16
Stops. Thereby, when a chip is generated in a semiconductor chip, the chip can be reliably made defective.

Although the power-on reset signal / POR is generated inside the semiconductor chip, it may be used as a reset signal from outside the semiconductor chip.

Although the input buffer 14 and the output buffer 16 are stopped when the semiconductor chip is chipped, it may be another main part in the operation of the semiconductor chip.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0046]

The semiconductor chip according to one aspect of the present invention is provided with the wiring formed on the periphery of the semiconductor chip and the control means. Therefore, if the periphery of the semiconductor chip is chipped, the wiring is broken. The control circuit stops the internal circuit.
Thereby, when a chip is generated in a semiconductor chip, the chip can be reliably made defective.

The control means includes a detection signal generation means,
The internal circuit operates when the enable signal is active and stops when the enable signal is inactive, so that if a chip is generated in the semiconductor chip, the chip can be surely made defective. it can.

Further, the detection signal generation means supplies a ground voltage to the wiring, and the enable signal generation means includes the precharge means and the latch circuit. To be defective.

The semiconductor device according to another aspect of the present invention includes first to fourth wirings, first to fourth detection signal generation means, and enable signal generation means. When chipping occurs, the chip can be reliably made defective.

The first to fourth detection signal generation means supplies a ground voltage to the first to fourth wirings, and the enable signal generation means includes a precharge means and the first to fourth detection means.
And the AND circuit, the internal circuit can be stopped when the semiconductor chip is chipped, and the chip can be reliably made defective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a detection signal generation circuit and an enable signal generation circuit shown in FIG.

3 is a timing chart for explaining an operation when chipping of the semiconductor chip shown in FIG. 1 does not occur;

FIG. 4 is a block diagram showing a state of wiring when the semiconductor chip shown in FIG. 1 is chipped.

5 is a timing chart for explaining an operation when the semiconductor chip shown in FIG. 1 is chipped.

FIG. 6 is a block diagram showing an overall configuration of a semiconductor chip according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing an internal configuration of a detection signal generation circuit and an enable signal generation circuit shown in FIG. 6;

FIG. 8 is a timing chart for explaining an operation when chipping of the semiconductor chip shown in FIG. 6 does not occur;

FIG. 9 is a timing chart for explaining an operation when the semiconductor chip shown in FIG. 6 is chipped.

[Explanation of symbols]

10, 20 production chip, 11, 21-24 wiring, 1
2, 31-34 detection signal generation circuit, 13, 40 enable signal generation circuit, 14 input buffer, 16 output buffer, GND ground voltage, Vdd power supply voltage, ZE
NF, ZENF1-ZENF4 detection signal, EN enable signal, ESi external input signal, ISi, ISo
Internal signal, ESo External output signal.

Claims (7)

[Claims] A semiconductor chip having an internal circuit; a wiring formed on a peripheral edge of the semiconductor chip; a semiconductor chip provided on the semiconductor chip; operating the internal circuit when the wiring is not disconnected; A control unit for stopping the internal circuit when the wiring is disconnected. 2. The control means includes: a detection signal generation means for generating a detection signal and supplying the detection signal to one end of the wiring; and an enable enable connected to the other end of the wiring and receiving the detection signal through the wiring. And an enable signal generating means for generating an inactive enable signal when the detection signal is not received, wherein the internal circuit operates when the enable signal is active and stops when the enable signal is inactive The semiconductor device according to claim 1, wherein 3. The detection signal generating means supplies a ground voltage to the wiring, the enable signal generating means charges a wiring to a power supply voltage for a predetermined time after power-on, and a precharging means; 3. The semiconductor device according to claim 2, further comprising: a latch circuit for latching a voltage. 4. A semiconductor chip having an internal circuit, first to fourth wirings formed corresponding to four corners of the semiconductor chip, and a first to fourth wiring for generating a detection signal. First to fourth detection signal generation means for supplying one end of the first wiring to the other end of the first to fourth wirings, and receiving the detection signal through each of the first to fourth wirings And an enable signal generating means for generating an inactive enable signal at other times, wherein the internal circuit operates when the enable signal is active and is inactive when the enable signal is inactive. Stop the semiconductor device. 5. The first to fourth detection signal generating means supplies a ground voltage to the first to fourth wirings, and the enable signal generating means operates the first to fourth detection signal for a predetermined time after power-on. Precharging means for charging a fourth wiring to a power supply voltage; first to fourth latch circuits for latching the voltages of the first to fourth wirings; outputs of the first to fourth latch circuits; The semiconductor device according to claim 4, further comprising: an AND circuit that outputs the enable signal in response to a signal. 6. The internal circuit includes an input buffer that generates an internal signal in response to an external signal when the enable signal is active and stops when the enable signal is inactive. The semiconductor device according to claim 5. 7. The internal circuit includes an output buffer that generates an external signal in response to the internal signal when the enable signal is active, and stops when the enable signal is inactive. The semiconductor device according to claim 6.