JP2000031142A - Semiconductor device and production thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress fluctuation in the lifetime of wiring by feeding a wiring formed on a substrate with a current at a current density of specified level or above and arranging the generating conditions of void in the wiring thereby reducing variance of the accumulated failure rate caused by the void. SOLUTION: A lower layer wiring 12 and an upper layer wiring 14 are formed on an insulating substrate 11 and connected through a plug 13 filling a via hole on the cathode side. The lower layer wiring 12 is then fed with a current at high current density of 1×106 A/cm2 or above and micro bores, i.e., voids 21, or nuclei thereof are generated in the lower layer wiring 12. Subsequently, generating conditions of void 21 are arranged such that only the void 21 are grown and enlarged even under actual use conditions, i.e., low acceleration conditions, thus reducing variance of accumulated failure rate caused by the void 21. According to the method, fluctuation in the lifetime of wiring can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a metal wiring as an internal wiring of a semiconductor integrated circuit device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the degree of integration and miniaturization of semiconductor integrated circuits has increased, the cross-sectional area of metal wiring used therein has tended to decrease year by year, and the current density flowing through the wiring has increased. Therefore, so-called electromigration, in which metal in the wiring moves under a high current density, is likely to occur. Electromigration is a serious problem because it causes an increase in wiring resistance and disconnection.

Therefore, improvement of electromigration resistance is very important for improving reliability of a semiconductor integrated circuit device. Conventionally, an electromigration resistance is evaluated by performing a life test of a wiring, and the life test of the wiring is performed as follows. That is, first, the wiring is maintained at a high temperature, a current having a high current density is applied to the wiring, and the time until the wiring is disconnected or a certain amount of resistance rise is measured.

Next, the measured life is written on a lognormal plot paper. In this case, since the wiring life generally follows a lognormal distribution, it is approximated by a straight line as shown in FIG. Based on this straight line, a time tlife until a predetermined percentage of failures in the total number of samples occurs is determined. Then, based on the effect of Tlife and temperature acceleration T and the current acceleration j, black formula ^{tlife = A · j -n · exp} (Ea / kT) ··· (1) where, A: constant j: current n = 1 to 2 k: Boltzmann's constant Ea = 0.7 to 0.9 eV T: Absolute temperature is used to calculate the constant A.

Further, using the constant A, extrapolation is made to conditions T and j for actually using the integrated circuit, and the conditions T and j are extrapolated.
The life tlife at j is calculated.

[0006]

By the way, conventionally, various methods have been used to extend the average life t50, that is, the time until 50% of the wiring of the total number of samples reaches the life. However, no matter how long the average life t50 is, if the straight line in FIG. 7 is curved, that is, if the inclination is small, the initial failure occurs very quickly. In this case, the semiconductor device still has a possibility of causing a fatal failure.

Therefore, in order to improve the reliability of wiring in a semiconductor integrated circuit, it is necessary not only to increase the average life t50 but also to increase the time tlife until a few initial failures occur. Here, the slope of the straight line in FIG. 7 corresponds to the variation in the life, and it can be said that the greater the slope, the smaller the variation. Therefore, in order to improve the reliability of the wiring in the semiconductor integrated circuit, it is extremely important to reduce the variation in the life and extend the tlife.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and provides a semiconductor device capable of reducing variation in wiring life and extending wiring life, and a method of manufacturing the same. It is.

[0009]

In order to solve the above-mentioned problems, the present invention relates to a method for manufacturing a semiconductor device, in which a current having a current density of 1 × 10 ⁶ A / cm ² or more is supplied to a wiring formed on a substrate. Thus, the variance of the cumulative failure rate caused by the holes is reduced by making the states of the holes generated in the wiring uniform.

In the present invention, a current density of 1 × 10 ⁶ A / cm ² or more is caused to flow through the wiring formed on the substrate, and the generation state of vacancies generated in the wiring, for example, the generation position and the generation time are made uniform. This reduces the variance of the cumulative failure rate caused by the vacancies. Since the variance of the cumulative failure rate is reduced, the straight line plotted on the lognormal plot paper becomes more prominent. That is, the inclination increases. This means
If a sample that is extremely deteriorated due to the application of a large current is removed in advance, this corresponds to uniforming the generation state of holes in the wiring before the energization test, that is, the generation location and generation timing.

[0011] In other words, this corresponds to the fact that the life time until the failure becomes uniform over all the samples. As a result, it is possible to prolong the place where the cumulative failure rate is small, that is, the time until a small number of failures first occur. For example, the period during which the current flows is determined by monitoring a change in the resistance value of the wiring. That is, it can be until the resistance value of the wiring increases to a predetermined value or until the resistance increases by a predetermined change amount from the initial value. This makes it possible to make the state of generating holes uniform.

Further, a method of manufacturing a semiconductor device according to the present invention
A containing refractory metal, Al, Cu, Ti or Si
It can be applied to a wiring made of l or Cu. Further, by using a multilayer wiring in which upper and lower wiring layers are connected by connecting conductors, and by setting the connecting conductor side to the low potential side and flowing a large current through the wiring via the connecting conductor, a predetermined current is applied from a large current application. After time, the vacancies, which are vacancies of the elements, gather near the cathode and near the connecting conductor. Thereafter, the position of the hole is constant regardless of the application time of the current without moving over the connection conductor.

Thus, the positions of the holes in the wiring before the energization test can be further aligned, and the variance of the cumulative failure rate can be reduced. In the present invention, since a large current having a current density of 1 × 10 ⁶ A / cm ² or more is passed, the above state can be realized in a short time. Further, if the ambient temperature is set high in advance, preferably 100 ° C. or higher, the effect of shortening the time can be enhanced.

At this time, if a large current flows through the wiring and the heat generated from the wiring is large, a pulsed current may be applied. Thereby, occurrence of a failure mode due to application of high heat can be prevented. Further, when connecting conductors are provided at both ends of the wiring, holes can be moved near the connecting conductors at both ends of the wiring by passing an alternating current having an appropriate frequency and waveform. Therefore, the holes are gathered closer to the connection conductor closer to the position of the holes in the wiring, so that the time for applying the current can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (1) First Embodiment of the Present Invention The inventor of the present application considered that various generation states of voids (voids) in a wiring are related to the cause of the variation in life as follows. .

That is, Al or A, which is currently mainstream,
In a laminated wiring structure in which the upper and lower portions of the 1 alloy layer are covered with a metal film of Ti or TiN, the resistance of the wiring increases due to voids generated in the Al or Al alloy layer. For this reason, it is considered that non-uniformity in the way of generation of the voids, for example, the timing and position of the voids, causes uneven resistance increase, that is, variation in life.

In order to confirm the above, the inventors of the present application conducted a failure analysis of the wiring when current was applied under various acceleration conditions. Al-based laminated wiring was used as the sample, and the OBIRCH method (Nikawa et al., Jpn. JAP, 34
(1995) 2260). The OBIRCH method is to irradiate the surface of a wiring portion with a laser beam which is narrowed down while scanning, thereby heating a minute area portion and simultaneously measuring a change in resistance of the wiring.

That is, when there is a void in the wiring, the heat conduction in the void becomes larger than that in the surrounding part and appears as a change in wiring resistance. By creating an image in which this resistance change is scanned in synchronization with laser scanning, an image of a void can be imaged (OBIRCH image). 1B and 2B are cross-sectional views of the prepared wiring.
These wirings 12 and 14 are 200 μm in length and 2.5 μm in width.
A TiN film 111 having a thickness of 50 nm and a
0.5% Cu-containing Al film 112 and a 20 nm thick T film
It is made of a laminated metal including an i film 113 and a 30 nm thick TiN film 114.

On the cathode side, there is a tungsten (W) plug 13 embedded in the via hole.
The lower wiring 12 and the upper wiring 14 are connected via the. FIG. 1A shows an OBIR of a cathode portion of a wiring to which a current is applied under a high acceleration condition of a current density of 2 × 10 ⁶ A / cm ^2.
5 schematically shows a CH image. As shown in FIG. 1A, the cathode side of the wiring 12, especially the plug 13
, It was found that one void 21 was generated. Then, from the portion other than immediately below the plug 13 on the cathode side shown in FIG. 1 (a), no image like a void was observed.

A plurality of wirings were examined by the same method and under the same conditions. In each case, the same tendency was observed, that is, only one void was found at the terminal end on the cathode side in the wirings after the current was applied, and the other parts were not. Did not show any voids. As described above, a void is generated in a certain place by applying a large current, but it may occur in that place from the beginning, but both void generation and further movement in the current direction may occur. May happen and eventually end up in that location. Which of these is occurring is currently unknown.

As a result of the continuous life test, the variation in the life was extremely small by the application of the above-mentioned large current, and the dispersion value σ representing the variation in the life was 0.1 or less. On the other hand, as a comparative example, the same wiring 1 as above was used.
And a current density of 2 × 10 ⁵ A / cm
Wiring 12 which is the current applied in the ^second low acceleration conditions OBIRCH
FIG. 2A shows an example in which an image is taken. A cross-sectional view of the wiring is shown in FIG.

According to FIGS. 2A and 2B, FIG.
As in (a) and (b), only one void was found in the wiring 12. However, the position was farther than the position immediately below the cathode-side plug 13 in the wiring 12. This tendency was observed for all the wirings to which the current was applied under the low acceleration condition. When the life test of this wiring was performed, the dispersion of the life was extremely large, and the dispersion value σ of the dispersion of the life was as large as about 1.

When the state of formation of voids in the wiring 12 and the resistance value were examined, after about 500 hours had passed, FIG.
(A) and (b), not only wirings in which voids were generated and the resistance increased, but also wirings in which no voids were observed and the resistance did not increase. From the above experimental facts, it is considered that the variation in the wiring life under the low acceleration conditions such as the actual use conditions is caused by the fact that the void generation location and the generation timing differ for each wiring.

On the other hand, according to the present invention, minute voids or void nuclei are formed by applying a current having a high current density of 1 × 10 ⁶ A / cm ² or more to the metal wiring 12 in advance. Can be. At this time, as can be seen from the above-described experimental fact, the void is always generated near the plug 13 on the cathode side, so that the place where the void is generated can be made constant.

According to the experiment, only one void was generated under both low acceleration and high acceleration conditions. From this, small voids were previously obtained under high acceleration conditions,
Alternatively, even after the void nucleus is formed, even if the void is used under a low acceleration condition, which is an actual use condition, it is considered that this void only grows and expands and no new void is generated in another place.

In the present invention, since a high-density current is applied to the manufactured wiring 12 to form minute voids, the average life t is longer than that of the wiring 12 in which no current flows as usual.
50 itself becomes a little shorter. However, by reducing the variation in the service life, it is possible to greatly increase the tlife. Therefore, shortening of the average life t50 is not so problematic.

Further, while a high-density current is passed, the wiring resistance
Monitoring the current to stop the current at a predetermined value, or
Or when the resistance increase is 1% or less of the initial value
It is easy to stop exactly. In addition, high-density
To shorten the time for flowing the current, the current density is set to, for example, 5 × 1
0 ⁶A / cm^TwoAbove, or the wiring 12
Increase the temperature to 100 ° C or more, and even 200 ° C or more
Is effective, which reduces the time it takes to create voids.
Can be shortened.

The present invention is extremely effective for a multilayer wiring structure in which wiring is connected to another layer, for example, an upper layer wiring by a plug embedded in a via hole in a stacked wiring. This is because, as shown in FIG. 1, in the multilayer wiring, voids are always generated in a specific place immediately below the plug (connection conductor), so that variations in life can be suppressed. Although the voids 21 are formed in the lower wiring 12 in the above description, the voids 21 may be formed in the upper wiring 14. In this case, a current flows from the upper wiring 14 to the lower wiring 12 through the plug 13. That is, the plug 13 is arranged on the cathode side in the upper wiring 14.

(2) Second Embodiment of the Present Invention FIG. 3 is a sectional view showing the structure of a wiring according to a second embodiment of the present invention. After a current having a high current density was passed through the test wiring shown in FIG. 3, a life test was conducted by flowing a current having a lower current density, and the wiring life was examined. The experimental results are described below.

The wiring has a film thickness of 50 nm as shown in FIG.
TiN film and Al containing 0.5% Cu with a thickness of 500 nm
It has a laminated wiring structure composed of a film and a 30 nm-thick TiN film. The lower wiring 2 and the upper wirings 4a and 4b are connected to both ends of this wiring via W plugs 3a and 3b embedded in the via holes. The width of the lower layer wiring 2 is 2.5 μm, and the length between the two plugs 3a and 3b is 30 μm.
0 μm.

The plugs 3a and 3b have a columnar shape.
The diameter was 1 μm and the height was 1 μm. Since these plugs 3a and 3b have a relatively large cross-sectional area, the heat generated from plugs 3a and 3b can be neglected even when a high-density current flows. Note that the upper wirings 4a and 4b already have a width of 10 μm or more from directly above the plugs 3a and 3b, and the effect of electromigration in this part can be ignored.

The experiment was performed as follows. That is, the test wiring was placed in an oven set at a temperature of 250 ° C. And while monitoring the voltage in that state,
A direct current of 62.5 mA was passed from the anode side (plug 3b side) to the cathode side (plug 3a side). This corresponds to a current density of 5 × 10 ⁶ A / cm ² in the Al alloy layer in the wiring.

When the calculated resistance value rises by 0.5% from the initial value, the current is stopped. A total of 20 TEGs were used, averaging about 13 minutes. Thereafter, the current density was increased to 2 × 10 ⁵ A / c.
m ² , that is, ^2.5 mA, and the oven temperature was set to 225 ° C., and a normal life test was performed on the test wiring.

The life was defined as the time until the resistance increased by 25% of the initial value. At the same time, for comparison, a life test of a sample which was not subjected to the above-described acceleration test of applying a large current was also performed on test wirings having exactly the same wiring structure. FIG.
(A) shows an example of a resistance change during the life test. FIG. 4B shows the result of the comparative experiment.

As shown in FIG. 4A, in the sample subjected to the acceleration test in which a large current is applied, the state of void formation is already uniform until the resistance slightly increases.
There is no latent period like. Further, since the positions and sizes of the voids of all the samples according to the embodiment were uniform, the manner of the subsequent resistance increase was fairly uniform.

On the other hand, in the sample of the comparative example, FIG.
As shown in the figure, at the beginning of the life test, there is a latent time (incubation time) in which the resistance does not rise, and thereafter, the resistance starts to rise. However, the way of the rise varied greatly depending on the wiring. FIG. 5 is a graph in which the life data obtained from the test results is logarithmically plotted.

As shown in FIG. 5, the average life time t50 of the test wiring to which a large current is applied is slightly shorter than the average life time t50 of the test wiring to which a large current is not applied. This substantially corresponds to the absence of a latent period in FIG. On the other hand, the slope of the straight line indicating the relationship between the cumulative failure rate of the test wiring to which a large current was applied and the time was clearly higher than that of the test wiring to which a large current was not applied, and the slope of the test wiring to which the large current was applied was larger. This shows that the variation of the cumulative failure rate is extremely smaller than that of the comparative example.

Further, the life tlife until 0.5% of the total number of test wirings becomes defective is tlife = 98 hours in the test wiring according to the present embodiment, whereas in the comparative example, tlife = 65 hours, and it was found that the test wiring according to the present embodiment is about 1.5 times longer than the comparative example. The current applied to the test wiring is not limited to DC, but may be AC having an appropriate frequency and waveform.
Thereby, voids can be simultaneously generated at both ends of the wiring.

(3) Third Embodiment The structure of the test wiring used in this embodiment is exactly the same as that of the second embodiment. In this case, unlike the first and second embodiments, the acceleration test was performed at room temperature while applying a pulsed current.

FIG. 6 shows the waveform of the pulse current. The current pulse has a rectangular shape with a pulse period of 100 ms and a pulse width of 50 ms, and its current value is 125 mA. This one
A current value of 25 mA corresponds to a current having a current density of 1 × 10 ⁷ A / cm ² flowing through the Al alloy layer in the laminated metal of the wiring. The same test was performed on a total of 20 test wirings, and current was continued to flow until the resistance value of each test wiring increased by 0.5% of the initial value. The measurement of the resistance value for detecting the end point was performed by reading the average DC voltage when the pulsed current was passed and estimating the resistance value. This acceleration test was completed in 10 to 20 minutes for each test wiring.

Thereafter, at a temperature of 225 ° C. and an applied current density of 2 ×
A normal life test was performed under the conditions of 10 ⁵ A / cm ² , and the resistance change, life, variation and the like were measured. As a result, all the values, such as the resistance change, the life, and the variation, were almost the same as those in the first embodiment. Further, under actual use conditions, the time tlife until 0.5% of the wiring becomes defective is determined by the comparative example (tlife =
65 hours) about 1.45 times tlife = 94
Time stretched.

As described above, in the third embodiment, in particular, it is possible to make the state of the void uniform by applying a pulsed current, and to prolong the life until the initial failure. Further, since a pulsed current is applied, Joule heat from the wiring can be suppressed. Therefore, the occurrence of another failure mode due to the application of high heat can be prevented.

As described above, according to the embodiment of the present invention, a large current is caused to flow through the wiring, particularly the upper and lower multilayer wirings connected via the plugs embedded in the via holes, before the life test. In addition, the generation time of holes or nuclei in the wiring is made uniform, and the holes or nuclei in the wiring are generated near the plug on the cathode side, thereby reducing the variation in the life of the wiring.

That is, in the life test, the time range from the time when the initial failure starts to the time when all the failures occur is reduced. For this reason, it is possible to greatly increase the time required for a statistically small number of wirings to become defective, which is important for quality assurance of the integrated circuit. Thus, the reliability of the wiring of the integrated circuit can be improved.

In the embodiment, the present invention is applied to a multilayer wiring having a plug. However, the present invention is not limited to this and may be applied to a single-layer wiring. Also in this case, the variance of the cumulative failure rate can be reduced by aligning the void generation state.
In addition, as a wiring, a TiN film is formed on the upper and lower sides.
% Cu-containing Al film is used, but 0.5% Cu-containing A
1 film itself, or another conductive film, for example, a refractory metal film, a pure Al film, or an A film containing Ti or Si.
These conductive films in which an l film, a Cu film itself, or a TiN film or the like is formed on the upper or lower portion may be used.

Further, although tungsten is used as a material for the plug, a high melting point metal other than tungsten, pure A
Al, Cu containing 1, Cu, Ti or Si, or Cu may be used.

[0047]

As described above, according to the present invention, before the life test, a large current is applied to the wiring, particularly the upper and lower multilayer wirings, to make uniform the vacancies or the nuclei thereof in the wiring.
The variation in wiring life is reduced. That is, the range of time from the time when the initial failure starts to the time when all the failures occur during the life test is reduced.

For this reason, important for the quality assurance of the integrated circuit,
The time required for a small number of wirings to become defective statistically can be greatly extended, which greatly contributes to the improvement of the reliability of the wiring of the integrated circuit.

[Brief description of the drawings]

FIG. 1A is a plan view of a void generated in a wiring used in a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG. FIG. 2 is a sectional view of FIG.

FIG. 2A is a plan view of a void generated in a wiring used in a method of manufacturing a semiconductor device according to a comparative example, and FIG. 2B is a cross-sectional view of FIG. 2A. FIG.

FIG. 3 is a cross-sectional view showing a wiring used in a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4A is a graph showing a state of a change in resistance of a wiring used in a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 5 is a graph showing a state of a change in resistance of a wiring used in a method for manufacturing a semiconductor device according to an example.

FIG. 5 is a graph showing a result of a life test of a wiring used in a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a method of applying a current to a wiring used in a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a graph showing a life of a wiring used in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 1,11 insulating substrate, 2,12 lower wiring, 3a, 3b, 13 plug, 4a, 4b, 14 upper wiring, 5,15 insulating film, 21 void, 101,103,111,114 TiN film, 102 Al film , 112 Al-Cu film, 113 Ti film.

Claims (7)

[Claims] A wiring formed on a substrate has a current density of 1 ×
A method of manufacturing a semiconductor device, characterized in that a current of 10 ⁶ A / cm ² or more is caused to flow to make the state of vacancies generated in the wiring uniform, thereby reducing the variance of the cumulative failure rate caused by the vacancies. Method. 2. The semiconductor device according to claim 1, wherein the vacancy generation state indicates one of a vacancy generation position and a vacancy generation time in the wiring. Manufacturing method. 3. The wiring is one of multilayer wirings connected to a wiring of another layer by a connection conductor at least at one place of the wiring, and the connection conductor side is kept at a low potential, The method according to claim 1, wherein the current flows through the connection conductor. 4. The method according to claim 1, wherein a period during which the current flows is determined by monitoring a change in a resistance value of the wiring. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring is heated to a temperature higher than room temperature while a current is flowing through the wiring. . 6. The method according to claim 5, wherein the temperature of the wiring is 100 ° C. or higher. 7. A wiring having a current density of 1.times.
A semiconductor device, comprising: a wiring in which a current of 10 ⁶ A / cm ² or more is caused to flow and a state of generation of holes generated in the wiring is made uniform.