JP2000030446A - Default operation mode setting change circuit of semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a default operation mode setting change circuit of a semiconductor storage which can change an operation mode of default after completion of a chip. SOLUTION: A (p)channel MOS transistor 107 and a fuse 109 are connected between a node N1 and a power source, a fuse 110 and a (n) channel MOS transistor 108 are connected between the node N1 and ground, an operation mode is set at the time of default in accordance with a ZPOR signal or a POR signal by cutting off either of fuses, and a mode signal is latched to a latch circuit consisting of inverters 103, 104 through inverters 101, 102 from ADD inputted at the time of setting an external mode and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a default operation mode setting change circuit for a semiconductor memory device, and more particularly to a default operation mode setting change circuit capable of setting or changing a plurality of operation modes according to the timing of an input signal.

[0002]

2. Description of the Related Art For example, in a synchronous DRAM or the like, a plurality of operation modes can be set by an address input level at the time of a mode setting command. Before setting the mode such as when the power is normally turned on, a default value is set so that the mode can be set internally. Hereinafter, the mode setting circuit will be described. Note that the default value refers to a period from when the power is turned on to when the operation mode is set by an external command.

FIG. 3 is a block diagram showing a conventional mode setting circuit, FIG. 4 is an electric circuit diagram of the MADD generating circuit shown in FIG. 3, and FIG. 5 is a circuit diagram showing a mode decoder shown in FIG. FIG. 6 is a diagram showing the truth table, and FIG. 7 is a timing chart for explaining the operation of the mode setting circuit.

In FIG. 3, a mode setting circuit is a MAD
., N and a mode decoder 10. The MADD generation circuits 1, 2,..., N set the default value to “L” or “H” level,
There are two types shown in FIGS. 4A and 4B, and the mode decoder 11 is configured as shown in FIG.

The MADD generating circuit 1a shown in FIG. 4A is composed of inverters 101 to 104 and a p-channel MOS transistor 105.
Is set. The MADD generation circuit 1b shown in FIG.
It is configured by the S transistor 106, and sets <0> at default.

The mode decoder 11 shown in FIG. 5 includes inverters 111 to 118 and NAND gates 121 to 124. The mode decoder 11 applies MADD <0> and MADD <1> set by MADD generation circuits 1, 2,. In response, mode signals 1 to 4 shown in the truth table of FIG. 6 are output.

Next, referring to the time chart of FIG.
The operation of the conventional mode setting circuit will be described.

When power supply Vdd rises to "H" level as shown in FIG. 7A, ZPOR shown in FIG.
The (zero power-on reset) signal is at the “L” level for a fixed time, and the POR (power-on reset) signal shown in FIG. 7C is at the “H” level for a certain time. When the ZPOR signal goes to "L" level, p-channel MOS transistor 105 of MADD generating circuit 1a turns on, node N1 goes to "H" level, and the level of node N1 is a latch circuit comprising inverters 103 and 104. , And "L" level MADD <0> is output regardless of the input ADD as shown in FIG. 7 (g). Also, when the POR signal becomes “H” level,
N channel MOS transistor 106 shown in FIG.
Is turned on, the node N2 goes to the "L" level, and the node N2
2 is latched by a latch circuit composed of inverters 103 and 104, and as shown in FIG.
“H” level MADD <1> is output irrespective of DD.

[0009] Such MADD <0>, MADD
According to the <1> signal, the mode decoder 11
Mode 2 and mode 3 signals as shown in (i) and (j) are output. Thus, the default value is set when the power is turned on.

Next, when a mode set command is input from the outside, a one-shot M as shown in FIG.
A SET signal is generated, and an input ADD signal is captured by inverters 101 and 102 shown in FIGS.

Now, as shown in FIGS. 7 (e) and 7 (f), A
Assuming that DD <0> = "H" and ADD <1> = "L" level, MADD <0> as shown in FIGS. 7 (g) and 7 (h).
= “H”, MADD <1> = “L”, and the mode signal 3 shown in FIG.

[0012]

SUMMARY OF THE INVENTION The MA shown in FIG.
When the ZPOR signal is input, the DD generation circuit 1a
D <0>, and the MADD generating circuit 1b shown in FIG. 4B outputs MADD <1> when the POR signal is input. That is, in the conventional MADD generation circuits 1a and 1b, the default operation mode is fixed and cannot be changed.

If the default operation mode can be changed by changing the mask or process, the IC is operated without setting the operation mode after completion of the IC, and it is checked which mode is in effect by changing the mask or process. Chip information can be obtained.

SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a default operation mode setting change circuit of a semiconductor memory device which can change a default operation mode after completion of a chip.

[0015]

The invention according to claim 1 is
An input circuit in which a default operation mode is set at power-on and another operation mode signal is input in response to an external command signal in a semiconductor memory device which can be set to another operation mode in response to an external command signal; And a fuse circuit for setting the output of the input circuit to the first reference potential or the second reference potential when the power is turned on to change the operation mode to another operation mode.

According to a second aspect of the present invention, a wire bond connection circuit is provided in place of the fuse circuit of the first aspect.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an M according to an embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an ADD generation circuit. 1, inverters 101 to 104 are connected in the same manner as in FIG. 4 described above, and a p-channel MO is connected between a power supply and node N1.
S transistor 107 and fuse 109 are connected in series, and fuse 110 and n-channel MOS transistor 108 are connected in series between node N1 and ground. The gate of p-channel MOS transistor 107 is supplied with a ZPOR signal, and the gate of n-channel MOS transistor 108 is supplied with a POR signal.

In such a MADD generation circuit, the default value set by the ZPOR signal or the POR signal can be changed by laser trimming one of the fuses 109 and 110. That is, if the fuse 109 is cut, the n-channel MOS transistor 108 is turned on by the POR signal, the node N1 goes to "L" level, and MADD goes to "H" level. If fuse 110 is cut, ZPOR
The signal causes the p-channel MOS transistor 107 to conduct,
Node N1 attains "H", and MADD attains "L" level.

If ADD <0> is input to the MADD generation circuit and the fuse 108 is cut, and ADD <1> is input to another MADD generation circuit and the fuse 109 is cut, the configuration shown in FIG. The behavior is the same.

As described above, if the default operation mode can be set at the time of laser trimming, the information can be obtained from the completed chip by changing the default value according to certain information. This information becomes a chip history and can be used for failure analysis and the like. As a check method after the default, it is sufficient to test whether or not to operate in the default operation mode.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. The embodiment shown in FIG. 2 is different from the fuses 107 and 108 shown in FIG.
31 to the power supply Vdd or wire 132
Is grounded. With this, the same effect as in FIG. 1 can be obtained.

[0022]

As described above, according to the present invention, the fuse for setting the output of the input circuit to the first reference potential or the second reference potential when the power is turned on is included in the default operation mode setting change circuit. By providing the circuit or the wire bond connection circuit, the default operation mode can be easily changed after completion of the chip, and this information can be used as a chip history for failure analysis and the like.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a MADD generating circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a MADD generation circuit according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional mode setting circuit.

4 is an electric circuit diagram of the MADD generating circuit shown in FIG.

FIG. 5 is a circuit diagram showing the mode decoder shown in FIG. 3;

FIG. 6 is a diagram showing a truth table of the mode decoder.

FIG. 7 is a time chart for explaining the operation of the mode setting circuit.

[Explanation of symbols]

101-104 inverter, 107 p-channel MO
S transistor, 108 n-channel MOS transistor, 109, 110 fuse, 131, 132 wire bond line.

Claims (2)

[Claims] 1. A semiconductor memory device capable of setting a default operation mode at power-on and changing setting to another operation mode in response to an external command signal, wherein the other operation mode signal is input in response to the external command signal. And a fuse circuit for setting an output of the input circuit to a first reference potential or a second reference potential when the power is turned on to change the operation mode to the other operation mode. Device default operation mode setting change circuit. 2. A semiconductor memory device capable of setting a default operation mode at power-on and changing the operation mode to another operation mode in response to an external command signal, wherein the other operation mode signal is changed in response to the external command signal. An input circuit to be inputted, and a wire bond connection circuit for setting the output of the input circuit to a first reference potential or a second reference potential at the time of power-on and changing to the other operation mode, A default operation mode setting change circuit for a semiconductor memory device.