JP2000029852A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately measure simultaneously executed user's CPU time independently of the size of a program to be executed by a processor of each user. SOLUTION: In this multiprocessor system, a system timer 3 for managing the execution time of the system, a memory 4 for sampling time from the timer 3 and storing the sampled time and two or more processors 100 to 102 for executing respective programs 150 to 152 while driving respective timers 140 to 142 are connected to a bus 2. The timer 3 is always driven, the timers 140 to 142 are stopped in kernel mode operation and driven in user mode operation and the memory 4 measures the program execution time of the user mode operation based on the time sampled from the timers 140 to 142 and the timer 3 and stored in its inside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly, to a tightly coupled multiprocessor system capable of accurately measuring the execution time when a parallel processing program is simultaneously executed by a plurality of users.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system, in order to manage the time of a processor used by each user, the system is provided with one timer, the time is transferred to each processor, and the same time is held in each processor. I was letting it. As an example of such a conventional multiprocessor system, FIG. 6 shows a "time management system" disclosed in Japanese Patent Application Laid-Open No. 3-188513.

According to FIG. 6, in the above-mentioned "time management system", a time taken out from a timer provided in a system control unit is loaded into a shift register also provided in the system control unit. For each of the predetermined bits divided and extracted from, the delay of the time that occurs until all the values have been transferred is corrected in advance, and the bits are sequentially transferred to the processors and the shift registers 11-1 and 12-1 of the processors are used. , And each processor holds the same time.

[0004]

However, the conventional technique as described above has a problem that the user time is measured larger than the actual time.

The reason is that, as shown in FIG. 7, the measurement of the concurrently executing user CPU time requires control between the multiprocessors, so that it must be calculated using a system timer which exists only in the system. Because there is no. That is, when the processor b in FIG. 7 shifts from the user mode to the kernel mode, it is necessary to obtain a system timer value by the operation system (OS) every time the program starts executing in the kernel mode. Therefore, there is a time difference from time C at which execution is started to time A at which the system timer value is acquired.
Similarly, if the time of transition from the kernel mode to the user mode is time D, a time difference occurs because the OS needs to acquire the system timer value at time E immediately before the transition to the user mode. This time difference is accumulated each time the user mode transitions to the kernel mode, and the time difference appears remarkably when a program having a large number of transitions per unit time is executed.

Accordingly, an object of the present invention is to accurately measure the concurrently executing user CPU time regardless of the size of a program executed by each user's processor.

[0007]

A system according to the present invention for solving the above-mentioned problems includes a system timer for managing the execution time of the system, a memory for collecting and storing time from the system timer, and a program for each program. A multi-processor system in which two or more processors that execute while activating the timer are connected to a bus, wherein the system timer operates constantly regardless of whether the processor is operating in a kernel mode or a user mode. The timer is stopped during the kernel mode operation, and is operated during the user mode operation, and the memory is configured to execute the program in the user mode operation based on the time collected and stored from the timer and the system timer. The execution time is measured.

Further, the method of the present invention comprises a system timer for managing the execution time of the system, a memory for collecting and storing the time from the system timer, and two or more programs for executing each program while operating each timer. Using a multiprocessor system with a processor and a bus connected,
A program execution time management method for calculating the program execution time in a user mode, wherein the memory calculates the program execution time in the user mode based on a time measured by the system timer, and And based on the time measured by the timer, calculate the time to transition from the user mode to the kernel mode and the time to transition from the kernel mode to the user mode, based on each calculation, the user mode in the user mode The program execution time is corrected and calculated.

That is, in the present invention, each processor is also provided with a timer, time correction is performed, and the simultaneous execution user CPU time is calculated without error.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multiprocessor system according to the present invention. As shown in FIG.
In the multiprocessor system of the present invention, a plurality of processors 100, 101, 102
It is connected to the memory (main memory) 4 of the unit. The memory 4 is equipped with a simultaneous execution user CPU time measurement mechanism 5, and includes an exclusive control mechanism 6, a time collection mechanism 7, a simultaneous execution number counter 8, a user CPU time storage area 9, and a time storage area G10 allocated to all processors. , Time storage area H allocated to the processor operating in the user mode
11, a timer value storage area 12, and a correction counter 13 are included. The system timer 3 which is solely present in the present system and the timers 140, 141 and 142 which exist for each processor are used to represent the time. FIG. 1 shows only three processors for simplicity.

Next, each component of the system will be described.

A timer 140 for each processor;
141 and 142 are programs 15 for each processor.
Timers that operate (count up) only when 0, 151, and 152 are executed in the user mode. That is, while the programs 150, 151, and 152 are executed in the kernel mode, the timers 140, 141, and 14 are executed.
2 is stopped.

The system timer 3 is a timer which always operates (counts up) during operation of the computer system.
It is not affected by the operation states of the processors 100, 101, 102 and the state of the memory 4. The time interval unit of the count-up is the same as that of the timers 140, 141, and 142.

The exclusive control mechanism 6 is used to acquire and release the right to exclusively refer to and update the concurrent execution number counter 8, the user CPU time storage area 9, and the time storage area G10 allocated to all processors. Mechanism.

The time collecting mechanism 7 is a mechanism for obtaining the times of the system timer 3 and the timers 140, 141 and 142.

The concurrent execution number counter 8 counts the number of processors operating in the user mode.

The user CPU time storage area 9 indicates the concurrently executing user CPU time, and allocates a storage area to each processor to store the time during which each processor operates in the user mode.

The time storage area G10 allocated to all processors and the time storage area H11 allocated to the processor operating in the user mode respectively include a system timer 3
Area for storing the value of

The timer value storage area 12 stores each processor 1
Timers 140, 1 held by 00, 101, 102
This area stores the values of 41 and 142.

The correction counter 13 copies the value of the simultaneous execution number counter and uses it at the time of time correction.

Next, the operation of the execution time measuring system of the present invention will be described with reference to FIGS. Less than,
For simplicity, a case where the processor a and the processor b simultaneously operate in the user mode as shown in FIG. 7 will be described. That is, in FIG. 7, the maximum number of simultaneous executions is two.

First, with reference to FIG. 2, an operation when the processor a transitions the execution from the kernel mode to the user mode will be described. Here, the kernel mode is a mode in which a program is executed only by a processor provided by the user. The user mode is a mode in which a user program is executed using an arithmetic device provided in the multiprocessor management system.

First, a lock is set to perform exclusive control of processing with another processor (step S1).

Next, the simultaneous execution number counter 8 is incremented (step S2). This is to record that the number of simultaneous executions has increased from 1 to 2 when the processor a starts executing in the user mode.

Next, the current time (system timer 3) is collected, and the time storage area G10 and the time storage area H11 are collected.
Is stored (step S3). Here, in the time storage area G10, addresses are provided and stored for all processors including the processor a. On the other hand, in the time storage area H11, an address is provided and stored for each concurrently executing processor operating in the user mode, including the processor a. Therefore, in this case, an address is given to the processor a and the processor b in the time storage area H11.

Next, the value of the timer in the processor a is obtained, and the time B shown in FIG. 7 is stored in the address for the processor a in the timer value storage area 12 (step S4).

Finally, the lock is released (step S5).

Next, with reference to FIG. 3, an operation when the processor b transitions the execution from the user mode to the kernel mode will be described.

First, a lock is set in order to perform exclusive control of processing with another processor (step S10).

Next, the simultaneous execution number counter 8 is decremented (step S20). This is to record that the number of simultaneous executions decreases when the processor b starts executing in the kernel mode.

Next, time A is collected from the system timer 3 (step S30).

Next, from the time storage area H, the processor a
Acquires the time B at which the kernel mode was terminated immediately before (step S40).

Next, the time B obtained in step S40 is subtracted from the time A obtained in step S30. (Step S50). This subtraction result value (AB) is the simultaneous execution user CPU time before correction.

In the present invention, the following processing is further performed to perform the correction.

First, the time C at which the processor b transits from the user mode to the kernel mode is obtained from the timer of the processor b (step S60).

Next, from the timer value storage area 12, the time D when the processor b transited from the kernel mode to the user mode last time (more precisely, the time D when the processor b transited from the user mode to the kernel mode last time (to be precise, the kernel time) The time of the timer of the processor being executed in the mode does not advance)) is acquired (step S70).

Next, the time D obtained in step S70 is subtracted from the time C obtained in step S60 (step S80).

Next, the time E at the time of the previous kernel termination of the processor is obtained from the area corresponding to the identification number of the processor b from the time storage area G10 (step S9).
0), from time A obtained in step S30 to step S
The time E obtained at step 90 is subtracted (step S10).
0). Further, the subtraction result Y performed in step S80 is subtracted from the subtraction result Z performed in step S100 (step S110). This value H (= (Z−Y)) is the correction value.

Accordingly, the correct concurrent execution user CPU time T is calculated by subtracting the correction value H (from the concurrent execution user CPU time X before correction (step S12).
0).

Normally, the value generated here should be added to the user CPU time storage area 9 corresponding to the current value of the simultaneous execution number counter 8, but if the time executed by the user is too short, Since the generated value may be negative and the addition result may be negative, it is necessary to perform a process of adding to a number smaller than the current value of the concurrent execution number counter 8. Specifically, the value generated in step S120 and the concurrent execution user CPU time corresponding to the correction counter 13 (the initial value is the same value as the concurrent execution number counter) are added, and it is checked whether the addition result is positive. (Step S130).

If the result is positive, the value is stored in the concurrent execution user CPU time storage area 9 (step S140),
Finally, release the lock. (Step S150).

If the result is negative, 0 is stored in the simultaneous execution user CPU time storage area 9 corresponding to the correction counter (step S160). Then, the added value in step S130 is regarded as the value generated in step S120 (step S170), and the correction counter is decremented (step S180). Then, the process of step S130 is performed with the new correction counter value. Thereafter, this is repeated until the result of step S130 becomes Y.

As described above, one embodiment of the present invention has been described. In particular, in the flowchart of FIG. 5, step S130, step S160, step S170,
Step S180 forms a loop. However, according to this flowchart, when the number of processors is large, overhead may be increased and a problem may occur in performance.

In another embodiment of the present invention suitable for such a case, the result of the judgment processing in step S130 is N
In the case of, it is conceivable to immediately proceed to step S150 to end the processing.

With this system, measurement of the concurrently executing user CPU time without any problem in performance can be realized. In the present embodiment, the correction is insufficient compared with the flowchart of FIG. 5, so that a slight error occurs in the concurrently executed user CPU time. Appears only when a special program that causes a large number of occurrences is executed. When a general program is executed, little error occurs and no problem occurs.

[0047]

According to the present invention described above, the simultaneous execution user CPU time without error can be measured. The reason is that a correction process is performed on the conventionally calculated value.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor system of the present invention.

FIG. 2 is a flowchart illustrating the operation of the multiprocessor system of the present invention when the number of simultaneous executions increases.

FIG. 3 is a flowchart for explaining the operation of the multiprocessor system of the present invention when the number of simultaneous executions decreases.

FIG. 4 is a flowchart (continued) for explaining the operation of the multiprocessor system of the present invention when the number of simultaneous executions decreases.

FIG. 5 is a flowchart for explaining processing when the execution time in the user mode is short.

FIG. 6 is a block diagram showing a configuration of a conventional time management system.

FIG. 7 is a time chart for explaining a transition between a kernel mode and a user mode.

[Explanation of symbols]

2 Bus 3 System timer 4 Memory 5 Simultaneous execution user CPU time measurement mechanism 6 Exclusive control mechanism 7 Time sampling mechanism 8 Simultaneous execution number counter 9 User CPU time storage area 10 Time at which addresses are assigned to all processors and the system timer value is stored Storage area G 11 Time storage area H 12 for assigning an address to a processor operating in user mode and storing a system timer value 12 Timer knowledge storage area 13 Correction counter 100, 101, 102 Processor 140.141, 142 Timer 150 , 151, 152 programs

Claims (5)

[Claims] 1. A system timer that manages the execution time of a system, a memory that collects and stores time from the system timer, and two or more processors that execute each program while operating each timer are provided on a bus. A connected multiprocessor system, wherein the system timer always operates regardless of whether the processor is operating in the kernel mode or the user mode, and the timer is stopped during the operation in the kernel mode. The multiprocessor system is operated during a mode operation, wherein the memory measures a program execution time in the user mode operation based on a time taken and stored from the timer and the system timer. 2. The memory according to claim 1, further comprising: a time sampling mechanism for sampling the time of the system timer and the timer; and reading addresses of the system timer from the time sampling mechanism by assigning addresses to all of the two or more processors. A first time storage area for reading and storing, a second time storage area for giving an address to the processor in the user mode operation and reading and storing the time of the system timer from the time collecting mechanism, and the two or more processors A timer value storage area for reading and storing the times of all the timers from a time collection mechanism, wherein each of the first time storage area, the second time storage area, the timer value storage area, and the system timer Measuring the program execution time in the user mode operation based on the time collected and stored from the Multiprocessor system according to claim 1, wherein. 3. The memory according to claim 2, wherein the memory includes a concurrent execution counter for counting the number of processors simultaneously operating in the user mode, an exclusive control mechanism for performing processing on only one of the processors, 3. The apparatus according to claim 2, further comprising: a correction counter for correcting an execution time; and a user CPU time storage area for summing execution times corrected by the correction counter for processors involved in simultaneous execution. Multiprocessor system. 4. A bus comprising: a system timer for managing the execution time of the system; a memory for collecting and storing time from the system timer; and two or more processors for executing each program while operating each timer. A program execution time management method for managing the program execution time in a user mode using a connected multiprocessor system, wherein the memory executes the program execution in the user mode based on a time measured by the system timer. Calculating a time, based on a time measured by the system timer and the timer, calculating a time of transition from the user mode to the kernel mode and a time of transition from the kernel mode to the user mode; In the user mode based on A program execution time management method for correcting the program execution time. 5. The program execution time management as claimed in claim 5, wherein when the result of said correction calculation is negative, the result of said correction calculation is regarded as zero, and said program execution times are summed up for processors involved in simultaneous execution. Method.