JP2000029695A - Processor and arithmetic processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor capable of achieving a high operation frequency. SOLUTION: In this processor for dividing instruction into (n) (n>=2) pieces of stages, successively performing it, parallelly executing the different stages of continuous plural instructions based on clock signals and performing a pipeline processing, an arithmetic operation module 12a for performing an arithmetic operation and a logical operation module 12b for performing a logical operation are mutually independently designed by using a hardware description language and arranged in different areas on a substrate and the arithmetic operation and the logical operation are respectively executed within one clock cycle of the clock signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a processor for performing instruction pipeline processing and an arithmetic processing system having the processor.

[0002]

2. Description of the Related Art In recent processors, RISC (Reduce
(ed Instruction Set Computer) type architecture has become mainstream. RISC type processor is CISC
(Complex Instruction Set Computer) type processors increase the instruction function level to reduce the number of executed instructions and increase the speed, while using the instruction pipeline to enable the average required number of clock cycles per instruction The speed is increased by approaching 1 as much as possible. Therefore, RIS
In a C-type processor, the function of an instruction is simplified so as to be suitable for instruction pipeline processing, and static code scheduling is performed by a compiler so that an instruction pipeline is not delayed.

[0003] Instruction pipeline processing is a technique of increasing the overall throughput by dividing instruction execution into a plurality of stages (stages) and executing the plurality of stages in an overlapping manner.

FIG. 5 is a diagram for explaining a five-stage instruction pipeline process. As shown in FIG. 5, in the five-stage instruction pipeline processing, execution of one instruction is performed by IF (Instruction).
Fetch), RF (Register Fetch), EX (EXecution),
It is divided into five stages of MEM (MEMory access) and WB (Write Back), and each stage is executed in one clock cycle. Briefly describing the processing of each stage, in the IF stage, after updating the address on the external memory indicated by the program counter, the instruction is read (fetched) from the updated address. In the RF stage, the read instruction is decoded, and if necessary,
Reads data from general-purpose registers. The EX stage performs an operation using the data read by the RF stage, if necessary. In the MEM stage, an external memory is accessed as needed. In the WB stage, RF
When an operation is performed in the / EX stage, the result of the operation is written to a register.

In the above-described five-stage instruction pipeline processing,
As shown in FIG. 5, in clock cycle “5”, IF,
The RF, EX, MEM, and WB stages are executed in parallel, compared with the case where instruction pipeline processing is not adopted.
The apparent calculation speed can be increased five times.

In the instruction pipeline processing, the time of one clock cycle that determines the operating frequency is determined according to the execution time of the stage requiring the longest execution time (a critical path) among a plurality of stages. .
Therefore, in order to increase the number of operation rounds, it is necessary to reduce the execution time of a stage that becomes a critical path. In the five-stage instruction pipeline system shown in FIG. 5, the EX stage performing the arithmetic processing is a critical path for determining the time of one clock cycle, and has been a bottleneck in improving the operation speed.

In the processor, in the EX stage, the ALU
(Arithmetic Logic Unit) performs arithmetic logic operation processing. The ALU of the conventional processor includes an arithmetic operation unit that performs arithmetic operations such as addition, subtraction, multiplication and division, arithmetic shift, and comparison operation on numerical data, and a logic that performs logical operations such as logical operation and logical shift on non-numeric data. Computing units, and these computing units are referred to as Verilo, for example.
g-HDL (Hardware Description Language) or other hardware description language and a compiler of the language are used to automatically and integrally design. In conventional processors,
For example, the operating frequency is 45 (MHz), and the time of one clock cycle is 22 (sec).

The internal states of the processor include a normal operating state in which instructions are sequentially executed and a standby state in which an interrupt signal is externally input. Also in the state, the clock signal is supplied to all the modules in the processor that operate based on the clock signal, and these modules are operated as in the normal operation.

[0009]

However, in the above-mentioned conventional processor, since the entire ALU is automatically designed integrally using a hardware description language and a compiler of the language, the components of each arithmetic unit are required. It is distributed over a wide range, and it is difficult to improve the calculation speed.

In the conventional processor described above, a clock signal is supplied to all the modules in the processor that operate based on the clock signal in the standby state, as in the normal operation, and these modules are operated. Therefore, there is a problem that power consumption increases.

The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a processor capable of achieving a high operating frequency. Another object of the present invention is to provide an arithmetic processing system capable of reducing power consumption.

[0012]

SUMMARY OF THE INVENTION To solve the above-mentioned problems of the prior art and achieve the above-mentioned object, the processor of the present invention divides instruction execution into n (n ≧ 2) stages. A processor for performing pipeline processing by sequentially executing different stages of a plurality of continuous instructions based on a clock signal, and performing an arithmetic operation, and a logical operation module for performing a logical operation Are arranged in different regions on the substrate, and the arithmetic operation and the logical operation are each performed by one of the clock signals.
Execute within a clock cycle.

In the processor of the present invention, since the arithmetic operation module and the logical operation module are arranged in different areas on the substrate, when the components of the arithmetic operation module and the logical operation module are mixed in the same area. The components in each module can be arranged closer to each other. As a result, each of the arithmetic operation in the arithmetic operation module and the logical operation in the logical operation module can be executed at high speed, and the time of one clock cycle of the pipeline processing can be reduced.

In the processor according to the present invention, specifically, the arithmetic operation module and the logical operation module mutually execute a design performed by compiling a circuit design program described using a hardware description language with a compiler. They are arranged independently.

Further, the arithmetic processing system of the present invention includes a clock signal supply device for supplying a clock signal, and an instruction execution divided into n (n ≧ 2) stages and sequentially performed.
An arithmetic processing system comprising: a processor that executes different stages of a plurality of continuous instructions in parallel based on a clock signal from the clock signal supply device to perform a pipeline process, wherein the processor includes A program counter that indicates an address of the external memory in which an instruction to be read is stored; and a decoder that decodes the read instruction and decodes the low power consumption mode instruction instruction to output the low power consumption mode instruction signal to the clock signal. Decoding means for outputting to the supply device;
When using an arithmetic operation module for performing an arithmetic operation and a logical operation module for performing a logical operation arranged in different regions on the substrate, an operation means for performing an operation in accordance with the result of the decoding and an interrupt signal are input, the clock signal Interrupt control means for outputting a low power consumption mode release signal to the supply device. Further, the clock signal supply device constantly supplies a clock signal to the interrupt control means of the processor, and when the low power consumption mode instruction signal is input, a clock signal to the program counter, the decode means, and the arithmetic means. Stop supplying the signal,
When the low power consumption mode release signal is input, supply of a clock signal to the program counter, the decoding means, and the arithmetic means is started.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a processor and an arithmetic processing system according to an embodiment of the present invention will be described.
FIG. 1 shows a processor 1 and an external memory 2 according to this embodiment.
FIG. 4 is a diagram for explaining a connection relationship with the STA. As shown in FIG. 1, the processor 1 includes an instruction bus 3 and a data bus 4
Is connected to the external memory 2 via the. External memory 2
Stores instructions and data processed by the processor 1 and supplies the instructions and data to the processor 1 via the instruction bus 3 and the data bus 4, respectively.

FIG. 2 is a configuration diagram of a processor 1 and a clock signal supply circuit 40 as a clock signal supply device that constitute the arithmetic processing system of the present embodiment. As shown in FIG. 2, the processor 1 includes a general-purpose register group 10, a bypass logic module 11, an ALU module 1
2, a multiplication module 13, a division module 14, a program counter 15, an address operation module 16, an instruction decoder 17, a control register group 18, and an interrupt controller 19. Here, the interrupt controller 19 corresponds to the interrupt control means of the present invention.

Further, as described later, the processor 1
It operates based on two clock signals, a clock signal S53 which is always operating and a clock signal S52 which is operated / stopped according to the execution of the sleep command. The clock signals S53 and S52 are input from the clock signal supply circuit 40. When receiving the clock signal S52, the processor 1 supplies the input clock signal S52 to all components other than the interrupt controller 19 that operates based on the clock signal. On the other hand, processor 1
Receives the clock signal S53, supplies the clock signal S53 only to the interrupt controller 19, and operates only the interrupt controller 19.

The processor 1 has an operating frequency of 54 (MH)
z), and the time of one clock cycle is 1 / (54
× 10 ⁶ ) (sec). Processor 1 is a RIS
A C-type processor that executes a 16-bit fixed-length instruction and employs a stack machine architecture based on a load (read) instruction and a store (write) instruction for a general-purpose register of the general-purpose register group 10. I have. It also has a branch instruction having various branch conditions similar to those of the CISC type processor.

The general-purpose register group 10 has 32 32-bit general-purpose registers. As shown in FIG. 3, the bypass logic module 11 executes the instruction execution in the IF stage 30, the RF stage 31, the EX stage 32, the M
When the instruction pipeline is performed in the order of the EM stage 33 and the WB stage 34, a bypass that supplies the result of the EX stage 32 to the EX stage 32 and the RF stage 31 again without passing through the MEM stage 33 and the WB stage 34; , The data that has passed through the MEM stage 33 is transferred to the RF stage 3 again without passing through the WB stage 34.
1 to provide a bypass. According to the bypass logic module 11, when the operation result of the EX stage of the previous instruction is used in the EX stage of the subsequent instruction, for example, the operation result obtained in the EX stage of the previous instruction is used in the WB stage. Instead of writing to the register and then reading from the register at the RF stage of the subsequent instruction, the ALU shown in FIG.
By supplying the module 12, the multiplication module 13, and the division module 14, the EX stage of the subsequent instruction can be executed at an early timing.

The ALU module 12 has an arithmetic operation module 12a, a logical operation module 12b, and a shift operation module 12c. Arithmetic operation module 12
“a” includes an adder that performs addition to numerical data, a subtractor that performs subtraction, a comparison operation unit that performs a comparison operation, and the like. The logical operation module 12b includes a logical operation unit that performs a logical operation on non-numeric data, a bit field operation unit that performs a bit field operation, a data converter that performs data conversion, and the like. Shift operation module 1
2c includes an arithmetic shifter and a logical shifter. The multiplication module 13 includes a multiplier. The division module 14 includes a divider.

In the processor 1, the arithmetic operation module 1
2a, logical operation module 12b, shift operation module 12c, multiplication module 13, and division module 1
4 are individually, for example, Verilog-HDL
(Hardware Description Language) or the like, a design program is described using a hardware description language, and the design program is automatically designed by compiling the program using a compiler. Therefore, the arithmetic operation module 12
a, logical operation module 12b, shift operation module 12c, multiplication module 13, and division module 14
Are arranged independently of each other in different regions on the substrate. In this way, by designing each module individually using the hardware description language, the components in each module can be arranged close to each other on the board, and the speed of signal processing can be increased. As a result, the time required for the EX stage shown in FIG. 3 can be reduced, and the time for one clock cycle can be reduced as described above.

The program counter 15 indicates the address of the next fetched instruction on the external memory 2 shown in FIG. External memory 2 pointed to by program counter 15
Address is, in principle, every clock cycle,
It is automatically incremented at predetermined intervals. The update of the address indicated by the program counter 15 is based on the I
This is performed before the instruction is read in the F stage.

The address operation module 16 calculates an address of data to be accessed on the external memory 2.
The address is generated by an automatic increment function according to a byte boundary of the address.

The instruction decoder 17 decodes an instruction read from the external memory 2 and transmitted on the instruction bus to generate a control signal, and controls the instruction pipeline processing. The processor 1 employs a five-stage instruction pipeline system including an IF stage 30, an RF stage 31, an EX stage 32, a MEM stage 33, and a WB stage 34, as shown in FIG. Here, IF stage 30, RF stage 31, EX stage 32, MEM stage 33 and WB stage 34
Correspond to the instruction fetch stage, the decode stage, the operation stage, the memory access stage, and the write back stage of the present invention, respectively.

The processing of each stage will be briefly described.
In the F stage 30, the address on the external memory 2 indicated by the program counter 15 is updated, and the instruction is read (fetched) from the updated address. The RF stage 31 decodes the instruction read by the IF stage 30, and reads data from the general-purpose (data) registers of the general-purpose register group 10 as necessary. Also, E
In the X stage 32, if necessary, the RF stage 31
The arithmetic operation module 12a, the logical operation module 12b, the shift operation module 12c, the multiplication module 13, and the division module 14 perform the operation using the data read from the general-purpose register. M
In the EM stage 33, the external memory 2 is accessed as needed. In the WB stage 34, the EX stage 3
When the operation is performed in step 2, the result of the operation is written to a general-purpose register.

Upon decoding the sleep command, the command decoder 17 outputs a sleep signal S51 to the clock signal supply circuit 40. Here, the sleep instruction corresponds to the low power consumption instruction instruction of the present invention, and the sleep signal S51
Corresponds to the low power consumption mode instruction signal of the present invention.

The control register group 18 includes ten 32-bit control registers used for interrupt control and debugging. Interrupt controller 19
Performs overall control of interrupt control such as saving the address indicated by the program counter 15 at the time of an interrupt to the external memory 2 and operating a stack pointer. When the interrupt signal S50 is input from outside, the interrupt controller 19 performs a predetermined interrupt process according to the content of the interrupt signal S50. The interrupt controller 19 outputs the wake-up signal S54 to the clock signal supply circuit 40 when the interrupt signal S50 is to release the standby state by executing the sleep command. Here, the wake-up signal S54 corresponds to the low power consumption mode release signal of the present invention.

In a normal state in which the sleep signal S51 is not input from the instruction decoder 17 of the processor 1, the clock signal supply circuit 40 supplies clock signals S52 and S5.
3 are supplied to the processor 1. When the clock signal supply circuit 40 receives the sleep signal S51 from the instruction decoder 17 of the processor 1, the clock signal supply circuit 40 stops supplying the clock signal S52 until a wake-up signal S54 is input from the interrupt controller 19. When the clock signal supply circuit 40 receives the wake-up signal S54 from the interrupt controller 19, the clock signal supply circuit 40 restarts the supply of the clock signal S52 to the processor 1.

Hereinafter, the operation of the processor 1 will be described. Operation of Instruction Pipeline Processing FIG. 4 is a diagram for explaining instruction pipeline processing of the processor 1. The processing contents in the IF, RF, EX, MEM, and WB stages are as described above. Clock cycle "1": The IF stage of the instruction 60 is performed, and the address of the external memory 2 shown in FIG. 1 indicated by the program counter 15 shown in FIG. 2 is incremented by the fixed length "2" to the address "PC". The instruction 60 read from the address “PC” is transmitted (fetched) to the instruction bus.

Clock cycle “2”: The RF stage of the instruction 60 fetched in the clock cycle “1” is performed, and the instruction 60 is decoded by the instruction decoder 17. Further, the IF stage of the instruction 61 is performed, the address of the external memory 2 indicated by the program counter 15 is incremented to the address “PC + 2”, and the instruction 61 stored at the address “PC + 2” is fetched.

Clock cycle "3": EX of instruction 60
The stage and the RF stage of instruction 61 are performed. Further, the IF stage of the instruction 62 is performed, the address of the external memory 2 indicated by the program counter 15 is incremented to the address “PC + 4”, and the address “P + 4” is set.
The instruction 62 stored in "C + 4" is fetched.

Clock cycle "4": ME of instruction 60
The M stage, the EX stage of the instruction 61 and the RF stage of the instruction 62 are performed. Further, the IF stage of the instruction 63 is performed, the address of the external memory 2 indicated by the program counter 15 is incremented to the address “PC + 6”, and the instruction 63 stored at the address “PC + 6” is fetched.

Clock cycle "5": WB of instruction 60
Stage, MEM stage of instruction 61, EX of instruction 62
The stage and the RF stage of instruction 63 are performed. Further, the IF stage of the instruction 64 is performed, the address of the external memory 2 indicated by the program counter 15 is incremented to the address “PC + 8”, and the address “P + 8” is set.
The instruction 64 stored in "C + 8" is fetched.

Clock cycle “6”: WB of instruction 61
Stage, MEM stage of instruction 62, EX of instruction 63
The stage and the IF stage of instruction 64 are performed.

Clock cycle "7": WB of instruction 62
The stage, the MEM stage of the instruction 63 and the EX stage of the instruction 64 are performed.

Clock cycle "8": WB of instruction 63
The stage and the MEM stage of instruction 64 are performed.

Clock cycle "9": WB of instruction 64
The stage takes place.

As described above, in the five-stage instruction pipeline processing of the processor 1, the execution of the instruction 60 ends at the clock cycle "5", the execution of the instruction 61 ends at the clock cycle "6", and the clock cycle The execution of the instruction 62 is completed at “7”, and the instruction 6 is executed at the clock cycle “8”.
3 is completed, and in the clock cycle “9”, the instruction 64 is executed.
Execution is terminated. Therefore, according to the processor 1, 1
Execution of the instruction apparently ends in one clock cycle. Further, according to the processor 1, as described above, the arithmetic operation module 12a, the logical operation module 12b,
Since the shift operation module 12c, the multiplication module 13 and the division module 14 are individually designed for each module using a hardware description language and a compiler of the language, these modules are mounted on a board as shown in FIG. In different regions. As a result, the execution time of each module can be reduced, the time required for the EX stage shown in FIG. 3, which is a critical path for determining a clock cycle, is reduced, and the time of one clock cycle is reduced to 1 / ( 54 × 10 ⁶ ) (sec)
Can be shortened to

Operation When Executing Sleep Command As a premise for explaining the operation, a sleep instruction is described in a program executed by processor 1 after an instruction for waiting for input of interrupt signal S50. First, the instruction for waiting for the input of the interrupt signal S50 is issued by the IF
Fetched on stage. At this time, the clock signals S52 and S
53 are supplied.

Next, the RF stage of the instruction for waiting for the input of the interrupt signal S50 is performed, and the instruction is decoded by the instruction decoder 17. As a result, the processor 1 enters a state of waiting for the input of the interrupt signal S50. Also, a sleep instruction is fetched in the IF stage. Next, the instruction decoder 17 performs an RF stage of a sleep instruction, and the instruction decoder 17 outputs a sleep signal S51 to the clock signal supply circuit 40. As a result, the supply of the clock signal S52 from the clock signal supply circuit 40 to the processor 1 is stopped, and the clock signal S53 is supplied only from the clock signal supply circuit 40 to the interrupt controller 19. Therefore, only the interrupt controller 19 is in the operating state, and the processor 1
The components other than the interrupt controller 19 are stopped.

Next, when the interrupt signal S50 is input to the interrupt controller 19, the interrupt controller 1
9 outputs a wake-up signal S54 to the clock signal supply circuit 40. When the wake-up signal S54 is input to the clock signal supply circuit 40, the clock signal supply circuit 40 starts supplying the clock signal S52 to the processor 1. Thus, all the components in the processor 1 are activated based on the clock signal S52.

As described above, according to the processor 1, by using the sleep command, when the CPU 1 enters the standby state for waiting for the input of the interrupt signal S 50, the processor 1 outputs the clock signal to the components other than the interrupt controller 19. The supply can be stopped and the operation of these components can be stopped. As a result, low power consumption can be achieved when the processor 1 is in a state of waiting for the input of the interrupt signal S50. Although the amount of reduction in power consumption depends on the time of the standby state according to the execution of the program, the processor 1 can reduce the power consumption to about 1/4 as compared with the case where the conventional sleep instruction is not used. it can. Also, the interrupt controller 19
, The clock signal S53 is always supplied, so that the processing according to the input of the interrupt signal S50 can be appropriately performed.

The present invention is not limited to the above embodiment. For example, in the embodiment described above, the case where “n” in the present invention is “5” is exemplified, but “n” may be other than “5” as long as “n” is 2 or more. That is, the number of stages of instruction pipeline processing is not limited to five.

[0045]

As described above, according to the processor of the present invention, the time required for the operation stage of the instruction pipeline processing can be shortened, the time of one clock cycle can be shortened, and the operating frequency can be reduced. Can be improved. Further, according to the arithmetic processing system of the present invention, low power consumption can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a connection relationship between a processor and an external memory according to an embodiment of the present invention;

FIG. 2 is a configuration diagram of a processor shown in FIG. 1;

FIG. 3 is a diagram for explaining a five-stage instruction pipeline processing and a bypass logic module of the processor shown in FIG. 2;

FIG. 4 is a diagram for explaining an execution state of the five-stage instruction pipeline processing shown in FIG. 2;

FIG. 5 is a diagram for explaining general five-stage instruction pipeline processing;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor, 2 ... External memory, 10 ... General-purpose register group, 11 ... Bypass logic module, 12 ... ALU
Module, 12a: arithmetic operation module, 12b: logical operation module, 12c: shift operation module, 1
3 Multiplication module, 14 Division module, 15 Program counter, 16 Address calculation module, 1
7 Instruction decoder, 18 Control register group, 19 Interrupt controller, 40 Clock signal supply circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yukihiro Sakamoto 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo F-term in Sony Corporation (reference) 5B013 AA11

Claims (6)

[Claims] 1. A processor for executing pipeline processing by dividing an instruction execution into n (n.gtoreq.2) stages and sequentially performing different stages of a plurality of continuous instructions in parallel based on a clock signal. Wherein an arithmetic operation module for performing an arithmetic operation and a logical operation module for performing a logical operation are arranged in different areas on a substrate, and the arithmetic operation and the logical operation are respectively performed within one clock cycle of the clock signal. Processor. 2. The arithmetic operation module and the logical operation module are arranged independently of each other by performing a design by compiling a circuit design program described using a hardware description language with a compiler. The processor according to claim 1. 3. A multiplication module for performing a multiplication, a division module for performing a division, and a shift operation module for performing a shift operation, wherein the arithmetic operation module performs an arithmetic operation excluding multiplication, division, and a shift operation. The arithmetic operation module, the logical operation module, the multiplication module, the division module, and the shift operation module are arranged in different areas on a substrate, and the arithmetic operation, the logical operation, the multiplication, the division, 2. The processor of claim 1, wherein each of the shift operations is performed within one clock cycle of the clock signal. 4. The arithmetic operation module, the logical operation module, the multiplication module, the division module, and the shift operation module are independent from each other in design performed by compiling a circuit design program described using a hardware description language with a compiler. 4. The processor according to claim 3, wherein the processor is arranged to operate. 5. A program counter for indicating an address of the external memory in which an instruction to be read from an external memory is stored; a decoding unit for decoding the read instruction; An arithmetic unit for performing an arithmetic operation by selecting and using one of an arithmetic operation module and the logical operation module; and a plurality of data registers for storing data, wherein the n stages are configured such that: An instruction fetch stage for reading an instruction from an address in an external memory; a decode stage for decoding the read instruction by the decoding unit; and an operation for performing an operation by the operation unit as necessary based on a decoding result of the decoding unit. Stage and, if necessary, the external memory A memory access stage to be accessed, at least a processor and a write back stage for writing the result of the arithmetic operation as required to the data register. 6. A clock signal supply device for supplying a clock signal, and an instruction is divided into n (n.gtoreq.2) stages and sequentially executed, and different stages of a plurality of continuous instructions are supplied to the clock signal supply device. A processor for executing pipeline processing in parallel based on a clock signal from the device, wherein the processor reads an address of the external memory in which an instruction to be read from the external memory is stored. A program counter for pointing; a decoding means for decoding the read instruction and outputting a low power consumption mode instruction signal to the clock signal supply device when decoding the low power consumption mode instruction instruction; Arithmetic operation module for performing the arranged arithmetic operation and logical operation module for performing the logical operation And an interrupt control unit that outputs a low power consumption mode release signal to the clock signal supply device when an interrupt signal is input to the clock signal supply device. The apparatus, when constantly supplying a clock signal to the interrupt control unit of the processor and inputting the low power consumption mode instruction signal, stops supplying the clock signal to the program counter, the decoding unit and the arithmetic unit, An arithmetic processing system which starts supplying a clock signal to the program counter, the decoding means and the arithmetic means when a low power consumption mode release signal is input.