JP2000029664A - Digital arithmetic processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the overflow of data occurable in the middle of an arithmetic operation to perform various improvement such as the reduction of a circuit scale, simplification of circuit constitution and reduction in cost and to be suitable for constituting an FFT arithmetic processing circuit. SOLUTION: This circuit is provided with an arithmetic part 55 for a digital arithmetic operation to data signals read from a memory part 53 and turning arithmetic output data signals obtained by that to the ones to be written in the memory part 53 or the ones to be sent out to the outside. The arithmetic part 55 is provided with a data shifter 65 for performing bit shift for the data signals held in a data register 64 as the ones relating to the digital arithmetic operation a shift setting register 66 for sending out shift setting data signals for setting the form of the bit shift in the data shifter 65 and a shift execution signal generation part 67 for supplying shift execution signals for selectively taking the state of performing the bit shift to the data shifter 65.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The invention described in the claims of the present application includes a memory unit for writing and reading an input data signal, and a data processing read from the memory unit includes a butterfly operation process and the like. And a calculation unit for performing a digital calculation to obtain a desired calculation output data signal.

[0002]

2. Description of the Related Art Audio broadcasting, which is often called "radio broadcasting", has been used for many years to transmit audio information signals as amplitude-modulated (AM) audio information signals. FM) Analog audio broadcasting such as FM audio broadcasting transmitted as an audio information signal has been described. In recent years, however, audio broadcasting has been changed to digital audio information in order to improve the quality of audio information transmitted and received. It has been proposed to make a digital audio broadcast transmitted as an audio information signal. In particular, in the European region, digital audio broadcasting has already been put to practical use as a system called DAB (Digital Audio Broadcasting) in a part thereof.

[0003] Audio information signals transmitted and received under digital audio broadcasting, that is, digital audio broadcasting signals, include not only audio information data forming digital audio signals, but also digital audio signals.
In addition to this, for example, service information data containing, for example, weather forecast, traffic information, etc., is also transmitted, and the receiving side needs to obtain a digital voice signal based on voice information data or service data based on service information data. Control information data containing the control information to be transmitted is transmitted. The digital audio broadcast signal is obtained by converting digital data such as audio information data, service information data, and control information data into orthogonal frequency multiplexed modulation (Or
thogonal Frequency Divison Multiplex-ing: OFD
This is a modulated wave signal obtained by being modulated by the M) method.

Digital data such as voice information data, service information data, control information data, etc.
A digital audio broadcast signal receiver is used to receive a digital audio broadcast signal which is a modulated wave signal obtained by modulation by the DM method.

In a digital audio broadcast signal receiver, a digital audio broadcast signal transmitted from each broadcasting station performing digital audio broadcast is selectively received by a channel selection operation, and demodulation and demodulation of the received digital audio broadcast signal are performed. Decoding processing, data selection, and the like are performed to obtain voice information data, service information data, and control information data. Further, decoding processing is performed on the voice information data and the service information data, and digital voice signals and services are obtained. The data is played.

FIG. 3 shows an example generally considered as such a digital audio broadcast signal receiver. This figure 3
In the digital audio broadcast signal receiver shown in
The digital audio broadcast signal transmitted from the broadcast station and captured by the antenna 21 is selectively received by the channel selection operation of the channel selection receiving unit 22. The tuning operation in the tuning receiving unit 22 is performed according to a tuning control signal STD supplied from the control unit 40. Then, the tuning receiving unit 22
In the above, an amplification process, a frequency conversion process, and the like are performed on the digital audio broadcast signal selectively received to form an intermediate frequency (IF) signal SID for the digital audio broadcast signal selectively received, and the IF signal SID is The signal is supplied to an analog / digital (A / D) converter 23.

The A / D converter 23 outputs the IF signal SID
Is obtained, and is supplied to the quadrature demodulation unit 24. The quadrature demodulation unit 24 performs quadrature demodulation processing on the digital IF signal DID, thereby obtaining a pair of quadrature demodulated outputs, an I data signal DI and a Q data signal DQ.

[0008] The I data signal DI and the Q data signal DQ obtained from the quadrature demodulator 24 are subjected to a fast Fourier transform (FF).
T) It is supplied to the differential demodulation unit 25. FFT differential demodulation unit 2
5, the I data signal DI and the Q data signal DQ
Is converted from a time domain signal to a frequency domain signal, and the FFT differential demodulation unit 25 outputs control information data DCD representing control information transmitted by a fast information channel (FIC).
And composite data DXD formed by the voice information data and the service information data representing the voice information and the service data transmitted by the main service channel (MSC), respectively. The audio information data and the service information data forming the composite data DXD include a time
Interleave processing is applied.

The control information data DCD obtained from the FFT differential demodulation unit 25 is supplied to a Viterbi decoding unit 26, while the composite data DX obtained from the FFT differential demodulation unit 25 is supplied.
D is supplied to the program selection unit 27.

The program selecting section 27 includes a control unit 4
The program selection control signal SSP from 0 is also supplied, and in the program selection unit 27, any one of the plurality of program information data included in the audio information data forming the composite data DXD in accordance with the program selection control signal SSP. Alternatively, data selection for selecting any one of the plurality of program information data included in the service information data forming the composite data DXD is performed, and the time interleave process selected from the program selection unit 27 is performed. The program information data DPD is transmitted and supplied to the time deinterleave unit 28.

The time deinterleaving section 28 performs time deinterleaving processing on the selected time interleaved program information data DPD supplied through the program selecting section 27. Then, from the time deinterleave unit 28, program information data DPD 'that has been subjected to the time deinterleave processing is obtained.

The time-deinterleaved program information data DPD 'obtained from the time deinterleaving section 28 is supplied to the Viterbi decoding section 26. In the Viterbi decoding unit 26, the control information data DCD from the FFT differential demodulation unit 25
An error correction process is performed on the program information data DPD ′ from the time deinterleave unit 28 using the maximum likelihood decoding method. Then, the Viterbi decoding unit 26
, An error-corrected program information data DPD 'is obtained and supplied to the program selection unit 30, and the error-corrected control information data DPD'
The CD is obtained and supplied to the control unit 40.

From the program selector 30, audio program data DAD or service program data DSD based on the error-corrected program information data DPD 'from the Viterbi decoder 26 is derived.

The audio program data DAD derived from the program selector 30 is supplied to a high-efficiency decoder 31. The high-efficiency decoding unit 31 performs high-efficiency decoding processing on the audio program data DAD,
The data compressed by the high-efficiency decoding process is decompressed,
Decoded audio data DA is obtained. Further, from the high-efficiency decoding unit 31, program-related data DPA included in the audio program data DAD is obtained and supplied to the control unit 40.

The decoded audio data DA obtained from the high-efficiency decoding unit 31 is digital / analog (D /
A) The reproduced audio signal S which is supplied to the conversion unit 32 and is converted into an analog signal,
A is derived.

The service program data DSD derived from the program selector 30 is supplied to a decoder 33. The decoding unit 33 performs a decoding process on the service program data DSD, and derives reproduction service data DS based on the service program data DSD from the decoding unit 33.

The control unit 40 controls the control information data DCD from the Viterbi decoding unit 26, the program-related data DPA from the high-efficiency decoding unit 31, and the input operation unit 4.
Command signal C supplied from 1 in response to the operation in it
The control data DVD formed according to X or the like is supplied to the Viterbi decoding unit 26, and the operation of the Viterbi decoding unit 26 is controlled.

Under these circumstances, the I data signal DI and the Q data signal DQ obtained from the quadrature demodulation unit 24 are supplied, and the control information data DCD and the composite data DXD based on the I data signal DI and the Q data signal DQ are converted. Get FFT
The differential demodulation unit 25 writes and takes in the I data signal DI and the Q data signal DQ as an input data signal in the memory unit once, and then performs a complex operation on the I data signal DI and the Q data signal DQ read from the memory unit. The FFT operation, which is a digital operation including processing, is performed.
It comprises an arithmetic processing circuit.

FF performed in the FFT operation processing circuit
For T calculation, 16 points, 32 points, 64 points
The number of points, such as points and 128 points, is set. In the case of the FFT operation in which the number of points is N (N is a positive integer), that is, in the case of the N-point FFT operation, each stage is processed by a _log2 N-stage butterfly operation performed by N / 2 butterfly operation units. Is done.

The individual butterfly operation units are, for example, as shown in FIG.
, A pair of input terminals 43 and 44, a pair of output terminals 45 and 46, and a pair of data adders 47 and 4
8 and a complex coefficient unit 49. The complex coefficient unit 49 gives a complex coefficient called a twiddle factor, and the twiddle factor is represented by the following equation 1.

[0021]

(Equation 1)

That is, the twiddle factor is formed by a cosine coefficient forming a real part and a sine coefficient forming an imaginary part.

Then, two input complex data signals x1 and x2 are supplied to a pair of input terminals 43 and 44, respectively.
Two output complex data signals y1 and y2 are obtained at a pair of output terminals 45 and 46, respectively.

[0024]

In this manner, the FF
When an FFT operation, which is a digital operation, is performed in the T operation processing circuit, there is a possibility that data overflows during the operation, and if an overflow actually occurs, the effect is exerted in a form that causes inconvenience in the operation result. Become. Therefore, conventionally, as a countermeasure against such data overflow that may occur during the operation, it has been proposed to perform a floating-point operation using a barrel shifter or the like, a block floating-point operation, or the like.

However, in performing the floating-point operation, the block floating-point operation, and the like using the barrel shifter and the like as described above, it is necessary to provide a barrel shifter and a data value detection unit having a very large circuit scale.
It is said that it is difficult to reduce the circuit scale, simplify the circuit configuration, and reduce the cost of the FFT operation processing circuit.

In view of the above, the invention described in the claims of the present application provides a memory unit in which an input data signal is written and read, and a butterfly signal applied to a data signal read from the memory unit. An arithmetic unit for performing a digital operation including an arithmetic process to obtain a desired operation output data signal, the operation unit can suppress an overflow of data that may occur during the operation, and Improvements such as reduction in size, simplification of circuit configuration, reduction of cost, etc. are to be achieved, and the FFT provided in the FFT differential demodulation unit in the digital audio broadcast signal receiver
A digital arithmetic processing circuit suitable for forming an FT arithmetic processing circuit is provided.

[0027]

According to a first aspect of the present invention, there is provided a digital processing circuit for writing a data signal input through an input interface. And performing a digital operation on the data signal read from the memory unit, and outputting an operation output data signal obtained by the digital operation to the above-mentioned memory unit or transmitted through an output interface. A data shifter for performing a bit shift on a data signal held in a data register as being related to a digital operation, and shift setting data for setting a bit shift mode in the data shifter. A shift setting register that sends out signals, and a data It is intended to comprise a shift execution signal generating section supplies a shift execution signal to take the bit shift operation states selectively in motor configured.

In the digital operation processing circuit according to any one of the first to fourth aspects of the present invention, in the operation unit, the shift setting register includes In supplying a shift setting data signal to cause the shifter to perform a bit shift in a preset manner, for example, the bit shift in the preset manner may be performed by suppressing occurrence of data overflow in an arithmetic unit. The shift execution signal generation unit supplies a shift execution signal for causing the data shifter to perform a bit shift state before the occurrence of data overflow in the arithmetic unit, for example.

Thus, in the data shifter, a bit shift is performed on the data signal held in the data register in accordance with the shift execution signal from the shift execution signal generation unit before the data overflow occurs in the operation unit. The state is taken, and the bit shift of the data signal held in the data register is
According to the shift setting data signal from the shift setting register, it is possible to perform a bit shift that suppresses the occurrence of data overflow in the arithmetic unit.

Therefore, in the digital arithmetic processing circuit according to any one of the first to fourth aspects of the present invention, a barrel shifter and a data value detection circuit whose circuit scale is extremely large are provided. With such a configuration that does not require the provision of a unit or the like, the circuit scale can be reduced, the circuit configuration can be simplified, the cost can be reduced, and the like, the data overflow that can occur during the calculation in the calculation unit can be suppressed. Therefore, the digital arithmetic processing circuit according to any one of claims 1 to 4 in the claims of the present application provides an FFT differential demodulation in a digital audio broadcast signal receiver as shown in FIG. This is suitable for configuring an FFT operation processing circuit provided in the unit.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of a digital arithmetic processing circuit according to any one of the first to fourth aspects of the present invention.

In the example of the digital processing circuit shown in FIG. 1, for example, a pair of quadrature demodulated output signals obtained from the quadrature demodulation unit 24 included in the digital audio broadcast signal receiver shown in FIG. I data signals DI and Q
A data signal DIN such as a data signal DQ is input through an input interface 51, and further written and stored in a memory unit 53 via a data bus 52. At this time, the input interface 51 monitors the input state of the data signal DIN, and outputs a necessary amount of the data signal DI.
When N is input and stored in the memory unit 53, an operation command signal SQ is supplied to the control circuit unit.

The control circuit 54 generates various sequence control signals CSC in response to the operation command signal SQ from the input interface 51, supplies them to the arithmetic unit 55, An operation state in which digital operation including the butterfly operation process as described above using FIG.

In the arithmetic section 55 to which the sequence control signal CSC is supplied from the control circuit section 54, the memory section 5
The data signal DIN written and stored in 3 is read from the memory unit 53 and supplied via the data bus 52. Data signal DIN supplied to operation unit 55
Are distributed to an X-register 61 and a Y-register 62, and are stored as X data DX by the X-register 61 and are also stored as Y data DY by the Y-register 62.

The X data DX held by the X-register 61 and the Y data D held by the Y-register 62
Y is subjected to a multiplication process by the multiplication unit 63, and as a result, the multiplication output data signal DMP obtained from the multiplication unit 63 is held by the data register 64. The multiplied output data signal DMP held by the data register 64 is
The data is supplied to the data shifter 65.

The data shifter 65 includes a data register 64 as a part related to digital operation in the operation part 55.
The bit shift of the multiplied output data signal DMP held by is selectively performed to form a shifted output data signal DBS. In such a bit shift, the data shifter 65 sets the multiplied output data signal DMP as it is, that is, a state in which the multiplied output data signal DMP is converted into a shift output data signal DBS without causing a bit shift, or A state is obtained in which a shift output data signal DBS corresponding to a bit shift of a preset number of bits is generated on the upper bit side.

The data shifter 65 is supplied with a shift setting data signal DSF from a shift setting register 66 and a shift execution signal DON from a shift execution signal generator 67. The shift execution signal DON is sent to the data shifter 65,
The state in which the bit shift is performed on the multiplied output data signal DMP held by the data register 64, and the multiplied output data signal DM held by the data register 64
The state in which the bit shift for P is not performed is selectively taken. The shift setting data signal DSF sets the bit shift mode of the multiplied output data signal DMP performed by the data shifter 65, that is, the bit shift mode of the multiplied output data signal DMP in the data shifter 65.

For example, the shift execution signal DON from the shift execution signal generator 67 selectively takes a high level state and a low level state, and when the shift execution signal DON takes the high level state, the data shifter 65 outputs the multiplied output data signal DMP. When the bit shift is performed, and when the low level state is set, the data shifter 65 is set to perform the bit shift for the multiplied output data signal DMP. Further, the shift setting data signal DSF from the shift setting register 66 selectively takes a state representing each of "00", "01" and "10". The bit shift mode of the multiplied output data signal DMP is not substantially performed, that is, the multiplied output data signal DMP
As it is, and thus without bit shifting,
When the mode is set to be the shift output data signal DBS and the state representing "01" is taken, the bit shift mode of the multiplication output data signal DMP in the data shifter 65 is set to the lower bit side of the multiplication output data signal DMP. When the state is set such that a shift output data signal DBS corresponding to a one-bit shift is generated and a state representing "10" is taken, the bit shift state of the multiplied output data signal DMP in the data shifter 65 is set. Is set in such a manner that a shifted output data signal DBS corresponding to the one obtained by shifting the multiplied output data signal DMP to the upper bit side by one bit is obtained.

Thus, the data shifter 65 outputs the shift execution signal DON from the shift execution signal generator 67 and the shift setting data signal D from the shift setting register 66.
In accordance with the SF, for example, the bit output of the multiplied output data signal DMP held by the data register 64 is not performed, and the multiplied output data signal DMP is transmitted as it is as the shifted output data signal DBS. Multiplied output data signal DM
A state in which a bit shift is performed for P and a shift output data signal DBS corresponding to a signal obtained by shifting the multiplied output data signal DMP by one bit to the lower bit side is sent out, and the multiplied output held by the data register 64 A bit output data signal DMP is shifted, and a shifted output data signal D corresponding to a signal obtained by shifting the multiplied output data signal DMP by one bit toward the upper bit side.
The state for transmitting the BS is selectively taken.

The shift output data signal DBS sent from the data shifter 65 is supplied to the adder 68. The output data from the adder 68 is supplied to an accumulator 69, and the accumulator 69 adds the output data DAD.
And the addition output data DAD held by the accumulator 69 is supplied to the addition unit 68.

The added output data DAD obtained from the accumulator 69 is processed by the limiter 70 to be output data DUT. The output data DUT obtained from the limiter 70 is derived from the arithmetic unit 55 and transmitted via the data bus 52, and is written and stored in the memory unit 53, or transmitted to the outside through the output interface 71. It is supposed to be done.

Under such circumstances, the shift execution signal generation section 67 performs a bit shift on the multiplication output data signal DMP to the data shifter 65 before the occurrence of data overflow that may occur in the arithmetic section 55. For example, a high level state shift execution signal DON for supplying a state is supplied to the data shifter 65.
The time before data overflow that may occur in the arithmetic unit 55 occurs before the data signal DIN supplied to the arithmetic unit 55 via the data bus 52, the content of the digital arithmetic performed in the arithmetic unit 55, and the like. And can be assumed in advance.

Therefore, the shift execution signal generator 67 presumes a point in time before the occurrence of data overflow that may occur in the arithmetic unit 55, and sets the data shifter 65 at a point in time set by such an assumption. For example, a high level state shift execution signal DON is supplied to the data shifter 65 in order to cause the multiplication output data signal DMP to perform a bit shift state. Then, the shift execution signal generating section 67 applies the multiplication output data signal DMP to the data shifter 65 during a period other than the period including the time point set as described above.
For example, a shift execution signal DON that takes a low level state to take a state in which the bit shift is not performed for
Is supplied to the data shifter 65.

On the other hand, when the data shifter 65 performs a bit shift on the multiplication output data signal DMP in response to, for example, the shift execution signal DON attaining a high level state, the shift setting register 66 sets the data shifter 65 at that time. In order to suppress the data overflow that may occur in the arithmetic unit 55, the bit shift mode according to
A mode is set in which a shifted output data signal DBS corresponding to a signal obtained by shifting the multiplied output data signal DMP by one bit to the lower bit side is obtained, for example, “01”.
Is set, for example, "10" to obtain a shift setting data signal DSF or a multiplication output data signal DMP, which is a shift output data signal DBS corresponding to a signal obtained by shifting the upper bit side by one bit. Is supplied to the data shifter 65.

In order for the bit shift mode in the data shifter 65 to suppress the data overflow that may occur in the arithmetic unit 55, for example, the shift setting data signal DSF representing "01" is set. And a shift setting data signal DS representing "10"
Which one of F and F should be supplied to the data shifter 65 is determined based on the data signal DIN supplied to the arithmetic unit 55 via the data bus 52, the content of the digital arithmetic performed in the arithmetic unit 55, and the like. Can be set in advance.

Therefore, the shift setting register 66 is preset to suppress the data overflow that may occur in the arithmetic unit 55 when the data shifter 65 should perform the bit shift on the multiplied output data signal DMP. For example, a shift setting data signal DSF representing "01" or a shift setting data signal DSF representing "10" is supplied to the data shifter 65. When the bit shift does not need to be performed, for example, a shift setting data signal DSF representing “00” is supplied to the data shifter 65.

Since the data shifter 65 including the shift setting register 66 and the shift execution signal generating section 67 is provided, the arithmetic section 55 has a barrel shifter and a data Under a configuration that does not require the provision of a value detection unit and the like, data overflow that may occur during the
It will surely be suppressed.

FIG. 2 shows a specific configuration example of the data shifter 65 in the example shown in FIG. This specific configuration example is used when the multiplication output data signal DMP held by the data register 64 in the example shown in FIG. 1 is 6-bit data.

In the specific configuration example of the data shifter 65 shown in FIG. 2, the input bit terminals I0, I1, I2, I3, I4 and I4 to which the multiplication output data signal DMP is supplied are provided.
5, six switches S0, S1, S2, S3, S4, and S5 are connected between output bit terminals O0, O1, O2, O3, O4, and O5 from which a shift output data signal DBS is obtained. . Each of the switches S0 to S5 is
The movable contact a connected to any of the corresponding output bit terminals O0 to O5, the fixed contact b connected to any of the corresponding input bit terminals I0 to I5, the input bit terminal on the lower bit side (only the switch S0 is referenced) It has a fixed contact c connected to a potential terminal) and a fixed contact d connected to an input bit terminal (an input bit terminal I5 corresponding only to the switch S5) on the upper bit side. (In FIG. 2,
The display of a, b, c and d is regarded as the switch S0, and the switches S1 to S5 are omitted. The movable contacts a of the switches S0 to S5 are linked with each other.

An AND circuit 73 is provided in common for each of the switches S0 to S5. A shift setting data signal DSF sent from the shift setting register 66 and the shift execution signal generator 67 in the example shown in FIG.
And a shift execution signal DON. The shift setting data signal DSF is, for example, one of “00”, “01”, and “10”, and the shift execution signal DON is in a high level state or a low level state. . Then, from the AND circuit 73,
Shift setting data signal DSF and shift execution signal DON
Control signal DCS that changes according to the contents of
, Which are supplied to switches S0-S5 to control each of them.

The switch control signal DCS obtained from the AND circuit 73 represents "00" regardless of the content of the shift setting data signal DSF, when the shift execution signal DON is in a low level state. You. When the switch control signal DCS indicates “00”, the movable contact a of each of the switches S0 to S5 is connected to the fixed contact b. As a result, the multiplied output data signals DMP supplied to the input bit terminals I0, I1, I2, I3, I4 and I5 of the switches S0 to S5 are directly used as output bit terminals O0, O1,
It is derived to O2, O3, O4 and O5. That is, the bit shift of the multiplication output data signal DMP is not performed.

The switch control signal DCS obtained from the AND circuit 73 is low when the shift setting data signal DSF indicates “00” under the condition that the shift execution signal DON assumes a high level state. As in the case of taking the level state, "00" is represented, and the shift setting data signal DSF is set to "01".
, "01" is represented accordingly, and the shift setting data signal DSF is set to "1".
When "0" is represented, "10" is represented accordingly.

Even when the shift execution signal DON is in the high level state, the switch control signal DCS is "00".
In each of the switches S0 to S5, the movable contact a is connected to the fixed contact b. Thereby, the input bit terminals I0, I1, I2, I of the switches S0 to S5
Multiplied output data signal DM supplied to I3, I4 and I5
P, as it is, as the shift output data signal DBS,
Output bit terminals O0, O1, O of switches S0-S5
2, O3, O4 and O5.

When the switch control signal DCS is "01"
In each of the switches S0 to S5, the movable contact a is connected to the fixed contact c. Thereby, the input bit terminals I0, I1, I2, I3 of the switches S0 to S5
A shift output data signal DBS corresponding to a signal obtained by shifting the multiplied output data signal DMP supplied to I4 and I5 by one bit toward the lower bit side is provided by switches S0 to S0.
The output bit terminals of S5 are led out to O0, O1, O2, O3, O4 and O5.

Further, when the switch control signal DCS is "1"
When "0" is represented, each of the switches S0 to S5 has the movable contact a connected to the fixed contact d. Thereby, the input bit terminals I0, I1, I2, I of the switches S0 to S5.
Multiplied output data signal DM supplied to I3, I4 and I5
A shift output data signal DBS corresponding to a signal obtained by causing a one-bit shift of P to the upper bit side is generated by a switch S.
0 to S5 output bit terminals O0, O1, O2, O3, O
4 and O5.

[0056]

As is apparent from the above description, in the digital operation processing circuit according to any one of the first to fourth aspects of the present invention, the operation unit When the shift setting register supplies the shift setting data signal to cause the data shifter to perform the bit shifting in a preset mode, for example, the bit shift in the preset mode is performed by the data shifter in the arithmetic unit. No bit shift and no occurrence of overflow,
The shift execution signal generating unit supplies a shift execution signal for causing the data shifter to perform a bit shift state before the data overflow occurs in the arithmetic unit. Before the data overflow occurs in the arithmetic unit in response to the shift execution signal from the CPU, the bit shift of the data signal held in the data register is performed, and the data signal held in the data register is shifted. In accordance with the shift setting data signal from the shift setting register, it is possible to suppress the occurrence of data overflow in the arithmetic unit.

Therefore, according to the digital operation processing circuit according to any one of the first to fourth aspects of the present invention, the barrel shifter and the data value whose circuit scale is extremely large With a configuration that does not require the provision of a detection unit, etc., the circuit size can be reduced, the circuit configuration can be simplified, the cost can be reduced, and so on.
It is possible to suppress overflow of data that may occur during the calculation in the calculation unit. The digital arithmetic processing circuit according to any one of the first to fourth aspects of the present invention is a digital audio broadcasting signal receiver as shown in FIG. This is suitable for configuring an FFT operation processing circuit provided in the demodulation unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a digital arithmetic processing circuit according to any one of claims 1 to 4 of the present application.

FIG. 2 is a circuit configuration diagram showing a specific configuration example of a data shifter in the example shown in FIG.

FIG. 3 is a block diagram illustrating an example of a digital audio broadcast signal receiver.

FIG. 4 is a circuit connection diagram for describing a butterfly operation unit used in FFT operation processing.

[Explanation of symbols]

21 ... antenna, 22 ... tuning receiver, 23 ...
A / D converter, 24: Quadrature demodulator, 25: F
FT differential demodulator, 26... Viterbi decoder, 27, 30
... Program selection unit, 28 ... Time deinterleave unit, 31 ... High-efficiency decoding unit, 32 ...
D / A conversion unit, 33: decoding unit, 40: control unit, 41: input operation unit, 51: input interface, 52: data bus, 53: memory unit, 54: control circuit unit, 55: arithmetic unit, 61
..X-register, 62... Y-register, 63.
Multiplying unit, 64 Data register, 65 Data shifter, 66 Shift setting register, 67
Shift execution signal generator, 68... Adder, 69.
Accumulator, 70: Limiter, 71: Output interface, 73: AND circuit, S0 to S5
···switch

Claims (4)

[Claims] 1. A memory unit in which a data signal input and output through an input interface is written and read, and a digital operation is performed on the data signal read from the memory unit, and an operation output data signal obtained by the digital operation And an arithmetic unit configured to be written into the memory unit or transmitted through an output interface, wherein the arithmetic unit is configured to execute a digital signal operation related to the digital operation with respect to a data signal held in a data register. A data shifter for performing a bit shift, a shift setting register for transmitting a shift setting data signal for setting an aspect of the bit shift in the data shifter, and a mode for causing the data shifter to selectively take a state for performing the bit shift. Shift execution signal for supplying shift execution signal Digital arithmetic processing circuit, characterized in that it is configured with a fresh portion. 2. A shift execution signal generation section provided in an operation section supplies a shift execution signal for causing a data shifter to perform a bit shift state before data overflow occurs in the operation section, The shift setting register provided in the operation unit supplies the data shifter with a shift setting data signal that causes a bit shift performed by the data shifter to suppress occurrence of data overflow in the operation unit. 2. The digital arithmetic processing circuit according to claim 1, wherein: 3. A data shifter provided in an operation section, according to a shift setting data signal from a shift setting register.
Based on the input data signal from the data register, the input data signal is transmitted to the lower bit side or the upper bit side.
3. The digital arithmetic processing circuit according to claim 2, wherein a state of performing a bit shift to obtain an output data signal corresponding to a result of the bit shift is performed. 4. A first state in which a shift execution signal obtained from a shift execution signal generator provided in an arithmetic unit causes a data shifter to perform a bit shift, and a state in which the data shifter does not perform a bit shift. The data shifter selectively takes the second state in accordance with the shift setting data signal from the shift setting register when the shift execution signal takes the first state. 4. The digital arithmetic processing circuit according to claim 3, wherein a bit shift is performed to obtain an output data signal corresponding to a one-bit shift generated to a bit side or an upper bit side.