JP2000021998A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device the manufacturing cost, of which can be reduced by suppressing an increase in number of photolithographic processes. SOLUTION: A semiconductor integrated circuit device is provided with an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed in the substrate 1, in such a way that the well 8-2 surrounds a p-type well forming are, and a p-type well 15-1 formed in the substrate 1. The circuit device is also provided with a p-type well 15-2 surrounded by the n-type well 8-2 in the substrate 1, an embedded n-type well 12-1 formed under the p-type well 15-1, and an n-type well 12-2 which is formed under the p-type well 15-2 and connected to the n-type well 8-2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a well pn-separated from a substrate of the same conductivity type as a substrate and a plurality of types of gate insulating films having different film thicknesses, and a method of manufacturing the same. The present invention relates to a technique for reducing the number of masks used for the manufacture.

[0002]

2. Description of the Related Art Generally, a CMOS type semiconductor integrated circuit device has an n-type well for forming a p-channel type MOSFET (hereinafter referred to as PMOS) and an n-channel type MOSFE.
And a p-type well for forming T (hereinafter, NMOS).

Some of such general CMOS type semiconductor integrated circuit devices have wells of the same conductivity type as the substrate, which are pn separated from the substrate. For example, an NMOS whose back gate potential is the same as the potential of the p-type substrate, and an NMOS whose back gate potential is different from the potential of the p-type substrate
Are integrated on a single p-type substrate. In the case of such a semiconductor integrated circuit device, a p-type well pn-separated from the p-type substrate is formed, and an NMOS for making the potential of the back gate different from that of the p-type substrate is formed therein.

FIG. 72 is a sectional view of a semiconductor integrated circuit device having a p-type well pn-separated from a p-type substrate. 73 is a profile diagram showing the distribution of impurities in the substrate, FIG. 73A is a profile along the line 73A-73A in FIG. 72, FIG. 73B is a profile along the line 73B-73B in FIG. C) is a profile along the line 73C-73C in FIG. 72, (D) is a profile along the line 73D-73D in FIG. 72, and (E) is a profile along the line 73E-73E in FIG. Each is shown.

However, in a semiconductor integrated circuit device having a p-type well separated by pn from a p-type substrate,
Compared to a general semiconductor integrated circuit device, p-type substrate
A separate photolithography process is required to form an n-separated p-type well. For this reason, the number of masks used in the photolithography process increases, and the manufacturing cost increases.

A method of manufacturing a semiconductor integrated circuit device shown in FIG. 72 will be described below as a technique corresponding to the prior art of the present invention.

FIGS. 74 (A)-(C) and FIGS. 75 (A)-
FIGS. 76 (C), 76 (A), and 76 (B) are views showing the semiconductor integrated circuit device shown in FIG. 72 for each main step.

[0008] First, as shown in FIG.
The element isolation region 102 is formed on the surface of the p-type silicon substrate 101 by using the OS method, and the element region 103 is partitioned on the surface of the substrate 101. Next, the surface of the substrate 101 (silicon) exposed to the element region 103 is thermally oxidized, for example, to form a buffer oxide film 104 on the surface of the element region 103.
77A to 77E show impurity profiles in the substrate 101 after the buffer oxide film 104 is formed. (A) is a profile along the line 77A-77A in FIG. 74 (A), (B) is a profile along the line 77B-77B in FIG. 74 (A), and (C) is FIG. 74 (A) 77C inside
Profile along the -77C line. (D) Fig. 74 (A)
The profile along the 77D-77D line in FIG. 7 (E) is FIG.
4 (A) is a profile along the line 77E-77E.
As shown in FIGS. 77A to 77E, the buffer oxide film 1
After the formation of the substrate 04, the only conductive impurities in the substrate 101 are the p-type impurities originally contained in the substrate 101.

Next, as shown in FIG.
01 is coated with a photoresist, and a photoresist film 10 is formed.
5 is formed. Then, using photolithography,
Openings 106a and 106b are formed in the photoresist film 105.
To form The opening 106a is provided corresponding to the region where the n-type well is formed, and the opening 106b is formed in the substrate 101.
Is provided in an annular shape so as to surround a region where ap @--type well is formed. Next, the photoresist film 105
Is used as a mask to ion-implant an n-type impurity 107 into the substrate 101. Thereby, the n-type well 108-1
And an n-type well 108-2 surrounding the region where the p − -type well separated from the substrate 101 is formed. The impurity profiles in the substrate 101 after the formation of the n-type wells 108-1 and 108-2 are shown in FIGS.
(J) shows each. (F) is a drawing of 77 in FIG. 74 (B).
Profile along F-77F line, (G) diagram is FIG. 74
FIG. 74B shows a profile along the line 77G-77H in FIG. 74B, and FIG. 74H shows a profile along the line 77H-77H in FIG.
(I) is a profile along the line 77I-77I in FIG. 74 (B), and (J) is a profile along the line 77J-77J in FIG. 74 (B). As shown in FIGS. 77 (F) to (J), the n-type impurity 107 is introduced so as to be higher than the concentration of the p-type impurity originally contained in the substrate 101, and the n-type well 108 is introduced into the substrate 101. -1 and 108-2.

[0010] Next, as shown in FIG.
After removing the photoresist film 105 from above, a photoresist is applied again to form a photoresist film 109. Next, an opening 110 is formed in the photoresist film 109 by using a photolithography method. Opening 11
0 is provided corresponding to a region where a p − -type well which is pn separated from the substrate 101 is formed. Next, n-type impurities 111 are ion-implanted into the substrate 101 using the photoresist film 109 as a mask. Thereby, the substrate 101
In the region surrounded by the n-type well 108-2 of FIG.
A buried n-type well 112 formed apart from the surface of the semiconductor device 01 is formed. The impurity profiles in the substrate 101 after the formation of the n-type well 112 are shown in FIGS.
(E) shows each. The figure (A) is the same as the figure 78 in FIG. 74 (C).
Profile along line A-78A, FIG.
FIG. 74 (C) is a profile along the line 78C-78C in FIG. 74 (C), and FIG. 74 (C) is a profile along the line 78C-78C in FIG.
(D) shows the profile along the line 78D-78D in FIG. 74 (C), and (E) shows the profile along the line 78E-78E in FIG. 74 (C). FIG. 78 (A)-
As shown in (E), the n-type impurity 111 is introduced so as to be higher than the concentration of the p-type impurity originally contained in the substrate 101, and the buried n-type well 1 is introduced into the substrate 101.
12 is formed. Next, as shown in FIG. 75A, after removing the photoresist film 109 from above the substrate 101,
A photoresist is applied again to form a photoresist film 113. Then, openings 114-1 and 114-2 are formed in the photoresist film 113 by using a photolithography method. The opening 114-1 is provided corresponding to a region where a p-type well connected to the substrate 101 is formed, and the opening 114-2 is formed with a p-type well which is pn separated from the substrate 101. Are provided in correspondence with the region of interest. Next, using the photoresist film 113 as a mask,
P-type impurities 115 are ion-implanted into the substrate 101. As a result, a p-type well 116-1 is formed in the substrate 101, and a p-type well 116-2 is formed in a region surrounded by the n-type well 108-2 of the substrate 101. p
The − well 116-1 is a well connected to the substrate 101, and the p − well 116-2 is a well pn-separated from the substrate 101. p-type wells 116-1, 116
78 (F) to 78 (J) show the impurity profiles in the substrate 101 after the formation of -2. (F) is a profile along the line 78F-78F in FIG.
(G) is a profile along the line 78G-78G in FIG. 75 (A), (H) is a profile along the line 78H-78H in FIG. 75 (A), and (I) is FIG. 75 (A). 78I-78 in
The profile along the line I. (J) is the profile in FIG.
The profile along the line 78J-78J is shown. As shown in FIGS. 78 (F) to (J), the p − -type wells 116-1 and 116-2 are formed by adding a p-type impurity to the p-type substrate 1 originally. P than
The concentration of the type impurity becomes higher.

Next, as shown in FIG.
The photoresist film 113 is removed from the top of the photo-resist film 01.

Next, as shown in FIG. 75 (C), the buffer oxide film 104 is removed. Thereby, the element region 10
3, the surface of the substrate 101 (in this embodiment, the surface of each of the n-type well 108-1, p-type wells 116-1 and 116-2) is exposed. Next, as shown in FIG. 76A, the surface of the substrate 101 exposed to the element region 103 is thermally oxidized to form a gate oxide film 117.

Next, as shown in FIG.
A conductive film serving as a gate electrode of a transistor, for example, a stacked film of polysilicon and a tungsten silicide film is formed over the structure illustrated in FIG. Next, the laminated film is patterned to form a gate electrode 118. Next, according to a known method, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 108-1 to form a p-type source region 119S and a p-type drain region 119D. Then, according to a well-known method, an n-type impurity for forming an n-type source / drain is ion-implanted into the p − -type wells 116-1 and 116-2, and n-type source regions 120S-1, 120S-2, 12
0D-1 and 120D-2 are formed.

Next, as shown in FIG.
An interlayer insulating film 121 made of, for example, a CVD oxide film is formed on the structure shown in FIG. Next, the p-type source / drain regions 119S, 11
9D, n-type source / drain regions 120S-1, 120
A contact hole 122 communicating with each of D-1, 120S-2, and 120D-2 is formed. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 123.

In such a manufacturing method, the n-type well 10
When forming 8-1 and 108-2 (FIG. 74 (B)),
A photolithography step is required for forming the n-type well 112 (FIG. 74 (C)) and for forming the p-type wells 116-1 and 116-2 (FIG. 75 (A)). Particularly, the n-type well 112 shown in FIG.
Is a process unique to the semiconductor integrated circuit device shown in FIG. Therefore, when manufacturing the semiconductor integrated circuit device shown in FIG. 72, the number of photolithography steps increases, and the number of masks used in the photolithography step increases. Therefore, the manufacturing cost increases as compared with a general semiconductor integrated circuit device.

In order to reduce the manufacturing cost of the semiconductor integrated circuit device shown in FIG. 72, there is another manufacturing method as described below.

FIG. 79 is a sectional view of a semiconductor integrated circuit device manufactured by another manufacturing method. FIG. 80 is a profile diagram showing the distribution of impurities in the substrate.
(A) is a profile along the line 80A-80A in FIG. 79, (B) is a profile along the line 80B-80B in FIG. 79, and (C) is a profile along the line 80C-80C in FIG. And (D) show profiles along the line 80D-80D in FIG. 79, respectively.

Hereinafter, another manufacturing method will be described.

FIGS. 81 (A) to 81 (C), FIG. 82 (A),
FIGS. 83 (B), 83 (A) and 83 (B) are views showing the semiconductor integrated circuit device shown in FIG. 79 for each main step.

First, as shown in FIG. 81A, the surface of a p-type silicon substrate 101 is, for example, thermally oxidized to
A buffer oxide film 104 is formed on the surface of the substrate. Next, a photoresist is applied on the buffer oxide film 104 to form a photoresist film 105. Next, the opening 10 is formed in the photoresist film 105 by photolithography.
6a and 106b are formed. The opening 106a is provided corresponding to the region where the n-type well is formed.
b is provided corresponding to the region where the p − -type well separated from the substrate 101 is formed. Then, using the photoresist film 105 as a mask, an n-type impurity 107 is
1 is ion-implanted. Thus, n-type impurity implanted regions 108-1 and 108-2 are obtained. n-type impurity 107
84A to 84D respectively show impurity profiles in the substrate 101 after the ion implantation. (A) The figure is a profile along the line 84A-84A in FIG.
(B) is a profile along the line 84B-84B in FIG. 81 (A), (C) is a profile along the line 84C-84C in FIG. 81 (A), and (D) is FIG. 81 (A). 84D-84 in
This is a profile along the line D. FIGS. 84 (A) to 84 (D)
As shown in FIG. 7, the n-type impurity 107 is implanted so as to have a higher concentration than the p-type impurity originally contained in the substrate 101.

Next, as shown in FIG. 81 (B), after removing the photoresist film 105, a photoresist is applied again to form a photoresist film 113. Then, openings 114-1 and 114-2 are formed in the photoresist film 113 by using a photolithography method. The opening 114-1 is provided corresponding to a region for forming a p-type well connected to the substrate 101, and the opening 114-2 is a region for forming a p-type well which is pn separated from the substrate 101. Is provided in correspondence with. Next, the photoresist film 1
13 as a mask, p-type impurities 115
And ion implantation into the implantation region 108-2. Thus, p-type impurity implanted regions 116-1 and 116-2 are obtained. Substrate 101 after ion implantation of p-type impurity 115
84 (E) to 84 (H) show the impurity profiles inside. (E) is a profile along the line 84E-84E in FIG. 81 (B), and (F) is a profile along 84F-84E in FIG. 81 (B).
A profile along the line 84F, (G) is a profile along the line 84G-84G in FIG. 81 (B), and (H) is a diagram in FIG.
(B) shows a profile along the line 84H-84H, respectively. As shown in FIGS. 84 (E) to 84 (H), the p-type impurity 115 is implanted at a higher concentration and shallower than the concentration of the n-type impurity 107 included in the implantation region 108-2.

Next, as shown in FIG. 81C, the photoresist film 113 is removed. Next, heat treatment is performed to diffuse / activate the n-type impurities in the implantation regions 108-1 and 108-2 and the p-type impurities in the implantation regions 116-1 and 116-2. As a result, the implantation regions 108-1 and 108-2 become n-type wells 108-1 and 108-2, respectively, and the implantation regions 116-1 and 116-2 respectively become p-type well 1
16-1 and 116-2. Substrate 10 after heat treatment
84 (I) to 84 (L) show the impurity profiles in 1 respectively. (I) is a profile along line 84I-84I in FIG. 81 (C), and (J) is a profile along 84J in FIG. 81 (C).
Profile along -84J line, (K) figure is Fig. 81 (C)
The profile along the 84K-84K line in FIG.
The profile along the line 84L-84L in FIG. 1 (C) is shown. As shown in FIGS. 84 (I) to (L), in particular, the p − -type well 116-2 is formed only in the n-type well 108-2 and is pn-separated from the substrate 101.

Next, as shown in FIG.
The element isolation region 10 is formed on the surface of the substrate 101 by using the OS method.
2 are formed to divide the element region 103.

Next, as shown in FIG. 82B, the buffer oxide film 104 is removed. Thereby, the element region 10
3, the surface of the substrate 101 (in this embodiment, the surface of each of the n-type well 108-1, p-type wells 116-1 and 116-2) is exposed. Next, as shown in FIG. 83A, the surface of the substrate 101 exposed to the element region 103 is thermally oxidized to form a gate oxide film 117.

Next, as shown in FIG.
A conductive film serving as a gate electrode of a transistor, for example, a stacked film of polysilicon and a tungsten silicide film is formed over the structure illustrated in FIG. Next, the laminated film is patterned to form a gate electrode 118. Next, according to a known method, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 108-1 to form a p-type source region 119S and a p-type drain region 119D. Then, according to a well-known method, an n-type impurity for forming an n-type source / drain is ion-implanted into the p − -type wells 116-1 and 116-2, and n-type source regions 120S-1, 120S-2, 12
0D-1 and 120D-2 are formed.

Next, as shown in FIG.
An interlayer insulating film 121 made of, for example, a CVD oxide film is formed on the structure shown in FIG. Next, the p-type source / drain regions 119S, 11
9D, n-type source / drain regions 120S-1, 120
A contact hole 122 communicating with each of D-1, 120S-2, and 120D-2 is formed. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 123.

In such another manufacturing method, FIG.
In the two photolithography steps shown in FIG. 81A and FIG. 81B, the n-type well 108-1, the p-type well 116-1 connected to the substrate 101, and the p-type
P-type wells 116-2 separated by n can be formed. Therefore, the number of photolithography steps can be reduced, and the number of masks used in the photolithography step can be reduced.

However, in order to form the p− type well 116-2 in the n type well 108-2, FIG.
The dose of the p-type impurity 115 to be implanted in the step shown in (B) must be set to be higher than the impurity concentration of the n-type well 108-2. That is, the amount of the p-type impurity 115 for forming the p-type wells 116-1 and 116-2 is determined by the impurity concentration of the n-type well 108-2. Therefore, the p − -type wells 116-1, 1-1
16-2, there is no freedom in setting the respective impurity concentrations.

Although the thickness of a gate insulating film in a general semiconductor integrated circuit device is usually one type, there is a semiconductor integrated circuit device having a plurality of types of gate insulating films having different thicknesses. This type of device is used, for example, in a semiconductor integrated circuit device having a plurality of potentials applied to the gate of a MOSFET.

In such a semiconductor integrated circuit device, a photolithography step is required to obtain a plurality of types of gate insulating films having different thicknesses. Therefore, the number of masks used in the photolithography process is increased, and the manufacturing cost is increased as described above.

[0031]

As described above, the n-type well, the p-type well connected to the substrate, and the pn
In a semiconductor integrated circuit device having p-type wells to be separated, the number of photolithography steps increases and the manufacturing cost increases.

There is also a method of manufacturing this kind of semiconductor integrated circuit device without increasing the number of photolithography steps. However, in this method, it is difficult to freely set the impurity concentration of the p-type well.

Further, even in a semiconductor integrated circuit device having a plurality of types of gate insulating films having different film thicknesses, the number of photolithography steps is increased, and the manufacturing cost is increased.

The present invention has been made in view of the above circumstances, and its main objects are to provide a well of a conductivity type different from that of a substrate, a well connected to the same conductivity type as the substrate, and a substrate. In a semiconductor integrated circuit device having wells of the same conductivity type as above and having pn separation from the substrate, an increase in the photolithography process is suppressed while maintaining the advantage that the impurity concentration of the well of the same conductivity type as the substrate can be freely set. Another object of the present invention is to provide a semiconductor integrated circuit device and a method for manufacturing the same, which can reduce the manufacturing cost.

Another object of the present invention is to provide a semiconductor integrated circuit device having a plurality of types of gate insulating films having different film thicknesses, capable of suppressing an increase in photolithography steps and reducing the manufacturing cost, and a method of manufacturing the same. It is to provide a method.

Still another object is to provide a well of a conductivity type different from the substrate, a well connected to the substrate with the same conductivity type as the substrate, a well of the same conductivity type as the substrate and pn-separated from the substrate, and In a semiconductor integrated circuit device having a plurality of types of gate insulating films having different thicknesses,
It is an object of the present invention to provide a semiconductor integrated circuit device capable of suppressing an increase in photolithography steps and reducing a manufacturing cost while maintaining an advantage that an impurity concentration of a well of the same conductivity type as a substrate can be freely set, and a method of manufacturing the same.

[0037]

According to the present invention, a first semiconductor region containing a second conductivity type impurity is formed on a first conductivity type semiconductor substrate. A ring-shaped second semiconductor region formed on the semiconductor substrate and containing a second conductivity type impurity; and a second conductivity type impurity formed in a region surrounded by the ring-shaped second semiconductor region. An embedded third semiconductor region including an embedded third semiconductor region, an embedded fourth semiconductor region including an impurity of a second conductivity type formed on the semiconductor substrate, and an embedded third semiconductor region formed above the third semiconductor region; A fifth semiconductor region containing a first conductivity type impurity, a sixth semiconductor region containing a first conductivity type impurity formed above the fourth semiconductor region, And a transistor formed in a sixth semiconductor region. It is characterized by a door.

In the semiconductor integrated circuit device having the above structure, the embedded fourth semiconductor region containing the second conductivity type impurity is provided below the sixth semiconductor region containing the first conductivity type impurity. . Therefore, a mask used for introducing impurities of the first conductivity type for forming the fifth and sixth semiconductor regions and a second conductivity type for forming the buried third and fourth semiconductor regions are provided. Can be used in common with the mask used for introducing the impurity. Therefore, a well (first semiconductor region) of a conductivity type different from that of the substrate, a well (sixth semiconductor region) connected to the substrate with the same conductivity type as the substrate, and pn separation from the substrate with the same conductivity type as the substrate In a semiconductor integrated circuit device having respective wells (fifth semiconductor regions) to be formed, an increase in the number of photolithography steps can be suppressed.

The fifth semiconductor region of the first conductivity type is
It is formed above the third semiconductor region of the second conductivity type corresponding to the region surrounded by the annular second semiconductor region of the second conductivity type. Therefore, the impurity concentration is substantially free from the influence of the semiconductor region of the second conductivity type and can be set freely. Therefore, the advantage that the impurity concentration of the wells (fifth and sixth semiconductor regions) of the same conductivity type as the substrate can be freely set can be maintained.

According to another aspect of the present invention, a first gate insulating film is formed on a semiconductor substrate, and the first gate insulating film is formed on the semiconductor substrate.
A first impurity for forming a first semiconductor region is introduced into the semiconductor substrate using the mask, and a second semiconductor region is formed on the semiconductor substrate using the second mask. A second impurity for removing the first gate insulating film by using the second mask;
Forming a second gate insulating film in a portion where the first gate insulating film is removed, and increasing a thickness of the first gate insulating film in a portion where the first gate insulating film is left; A transistor using a gate insulating film and a transistor using the second gate insulating film are formed.

According to the method of manufacturing a semiconductor integrated circuit device having the above configuration, the introduction of the second impurity for forming the second semiconductor region and the removal of the first gate insulating film are performed using the same mask (the second mask). Using a mask). Therefore, in a semiconductor integrated circuit device having a plurality of types of gate insulating films having different thicknesses, an increase in the number of photolithography steps can be suppressed.

According to another aspect of the present invention, a first conductive type semiconductor substrate formed on a first conductive type semiconductor substrate is provided.
A second gate insulating film formed on the semiconductor substrate;
A first semiconductor region containing an impurity of a conductivity type, an annular second semiconductor region containing an impurity of a second conductivity type formed on the semiconductor substrate, and a first semiconductor region formed on the semiconductor substrate;
A buried third semiconductor region containing the second conductivity type impurity and a buried type third semiconductor region containing the second conductivity type impurity formed in a region surrounded by the annular second semiconductor region. A fourth semiconductor region, an embedded fifth semiconductor region containing the second conductivity type impurity formed in the first semiconductor region, and a fifth semiconductor region formed above the third semiconductor region. A sixth semiconductor region containing one conductivity type impurity, a seventh semiconductor region containing the first conductivity type impurity formed above the fourth semiconductor region, and a fifth semiconductor region. An eighth semiconductor region formed above and containing the first conductivity type impurity, and a second thinner than the first gate insulating film formed in the sixth, seventh, and eighth semiconductor regions. A gate insulating film and a transistor using the first gate insulating film. And static, is characterized by comprising a transistor including a second gate insulating film.

In the semiconductor integrated circuit device having the above structure, the third, fourth and fifth semiconductor regions of the second conductivity type and buried are formed below the sixth, seventh and eighth semiconductor regions. Have. Moreover, a second gate insulating film thinner than the first gate insulating film is provided in the sixth, seventh, and eighth semiconductor regions.
Therefore, a mask used to introduce the first conductivity type impurity for forming the sixth, seventh, and eighth semiconductor regions, and the buried third, fourth, and fifth semiconductor regions are formed. Used to introduce the second conductivity type impurity and the mask used to remove the first gate insulating film can be made common. Therefore, a well (eighth semiconductor region) of a conductivity type different from that of the substrate, a well (sixth semiconductor region) connected to this substrate with the same conductivity type as the substrate, and a pn separation from this substrate with the same conductivity type as the substrate In a semiconductor integrated circuit device having a plurality of types of gate insulating films having different wells (seventh semiconductor regions) and different film thicknesses, an increase in the number of photolithography steps can be suppressed.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

[First Embodiment] FIGS. 1A and 1B show a semiconductor integrated circuit device according to a first embodiment. FIG. 1A is a plan view and FIG. Sectional view along line B,
(C) is a sectional view taken along line CC in (A), (D)
The figure is a cross-sectional view along the line DD in the figure (A). Also,
2A and 2B are profile diagrams showing the distribution of impurities in the substrate. FIG. 2A is a profile along the line 2A-2A in FIG. 1B, and FIG. 2B is a profile along 2B-2B in FIG. (C) is a profile along the line 2C-2C in FIG. 1 (B), (D) is a profile along the line 2D-2D in FIG. 1 (B), and (E) is a profile along the line. 2 shows profiles along the line 2E-2E in FIG.

Hereinafter, the semiconductor integrated circuit device according to the first embodiment will be described together with its manufacturing method.

FIGS. 3 to 10 are views showing the semiconductor integrated circuit device according to the first embodiment for each main step. 3A to 10, (A) is a plan view,
(B) is a sectional view taken along the line BB in (A), (C)
The figure is a cross-sectional view taken along the line CC in the figure (A), and the figure (D) is a cross-sectional view taken along the line DD in the figure (A).

First, as shown in FIGS. 3A to 3D,
forming an element isolation region 2 on the surface of a p-type silicon substrate 1;
An element region 3 is defined on the surface of the substrate 1. In this embodiment, the element isolation region 2 is formed by using the LOCOS method.
It is an OCOS film. Next, the surface of the substrate 1 (silicon) exposed to the element region 3 is thermally oxidized, for example, to form a buffer oxide film 4 on the surface of the element region 3. FIG. 11 (A)-
(E) shows an impurity profile in the substrate 1 after the buffer oxide film 4 is formed. (A) is a diagram corresponding to 11 in FIG. 3 (B).
Profile along line A-11A, (B) figure is FIG. 3 (B)
The profile along the 11B-11B line in FIG.
FIG. 3B shows a profile along the line 11C-11C, FIG. 3D shows a profile along the line 11D-11D in FIG.
FIG. 3E is a profile along the line 11E-11E in FIG. As shown in FIGS. 11A to 11E, after the buffer oxide film 4 is formed, the only conductive impurities in the substrate 1 are the p-type impurities originally contained in the substrate 1.

Next, as shown in FIGS. 4A to 4D,
A photoresist is applied on the substrate 1 and a photoresist film 5
To form Next, openings 6a and 6b are formed in the photoresist film 5 using a photolithography method. In this embodiment, the opening 6a is formed corresponding to the region where the n-type well is formed, and the opening 6b is formed so as to surround the region where the p @-well separated from the substrate 1 is formed. Is done. Next, n-type impurities 7 are ion-implanted into the substrate 1 using the photoresist film 5 as a mask.
Thus, the n-type well 8-1 and the n-type well 8-- surrounding the region where the p − -type well separated from the substrate 1 is formed are formed.
2 are formed simultaneously. FIGS. 11F to 11J show impurity profiles in the substrate 1 after forming the n-type wells 8-1 and 8-2. (F) is a view of FIG.
Profile along 11F line, (G) figure is in FIG. 4 (B)
Profile along 11G-11G line, (H) figure is FIG.
4B is a profile along the line 11H-11H, FIG. 4I is a profile along the line 11I-11I in FIG.
(J) is a profile along line 11J-11J in FIG. 4 (B). As shown in FIGS. 11F to 11J, the n-type impurity 7 is introduced so as to be higher than the concentration of the p-type impurity originally contained in the substrate 1, and the n-type well 8 is formed in the substrate 1. -1, 8-2 are formed. Further, in this embodiment, after forming the element isolation region 2 (LOCOS),
N-type impurities 7 for forming n-type wells 8-1 and 8-2 are ion-implanted. For this reason, as shown particularly well in FIG. 4B, the n-type wells 8-1 and 8-2 each have an element region 3 under the element isolation region 2 (LOCOS).
It is shallower than the lower part according to the cross-sectional shape of the element isolation region 2.

Next, as shown in FIGS. 5A to 5D,
After removing the photoresist film 5 from above the substrate 1, a photoresist is applied again to form a photoresist film 9. Next, openings 10a and 10b are formed in the photoresist film 9 using a photolithography method. In this embodiment, the opening 10a is formed corresponding to the region where the p-type well connected to the substrate 1 is formed.
Ob is formed corresponding to the region where the p − -type well separated from the substrate 1 is formed. Next, the photoresist film 9
Is used as a mask to ion-implant n-type impurity 11 into substrate 1. Thereby, a buried n-type well away from the surface of the substrate 1 is provided in each of the region where the p − -type well connected to the substrate 1 is formed and the region where the p − -type well separated from the substrate 1 is formed. 12-1 and 12-2 are simultaneously formed. Also, an embedded n-type well 1
2-2 is formed in contact with the n-type well 8-2. Thus, a p-type region 13 pn-separated from the substrate 1 by the n-type well 12-2 and the n-type well 8-2 is obtained in the substrate 1. FIGS. 12A to 12E show n-type well 1
7 shows an impurity profile in the substrate 1 after forming 2-1 and 12-2. (A) The figure is 12A-12A in FIG. 5 (B).
Profile along the line, (B) figure is 12B in FIG. 5 (B)
FIG. 5 (C) is a profile along the line 12C-12C in FIG. 5 (B), and FIG.
5B is a profile along the line 12D-12D, and FIG. 5E is a profile along the line 12E-12E in FIG. 5B. As shown in FIGS. 12A to 12E, the n-type impurity 1
1 is introduced so as to be higher than the concentration of the p-type impurity originally contained in the substrate 1 to form buried n-type wells 12-1 and 12-2 in the substrate 1. In this embodiment, after forming the element isolation region 2 (LOCOS), the buried n-type wells 12-1 and 12-2 are formed.
Is ion-implanted to form n-type impurity 11. For this reason, as shown particularly well in FIG. 5B, the n-type wells 8-1 and 8-2 are each provided in the element isolation region 2 (LOCO).
Under S), the depth is shallower than the portion under the element region 3 according to the cross-sectional shape of the element isolation region 2.

In order to form the buried n-type wells 12-1 and 12-2 remote from the surface of the substrate 1,
For example, the acceleration voltage at the time of ion implantation of the n-type impurity 11 is set higher than the acceleration voltage at the time of ion implantation of the n-type impurity 7 for forming the n-type wells 8-1 and 8-2. What is necessary is just to inject into a deeper part. The n-type impurity 11 may be the same as or different from the n-type impurity 7.

Next, as shown in FIGS. 6A to 6D,
Without removing the photoresist film 9, a p-type impurity 14 is ion-implanted into the substrate 1 using the photoresist film 9 as a mask. As a result, the p-
A mold well 15-1 and ap @-well 15-2 separated from the substrate 1 are simultaneously formed. FIG.
(F) to (J) show impurity profiles in the substrate 1 after the formation of the p @--type wells 15-1 and 15-2.
6 (F) is a profile along the line 12F-12F in FIG. 6 (B), FIG. 6 (G) is a profile along the line 12G-12G in FIG. 6 (B), and FIG. The profile along the 12H-12H line in FIG. 6 (I) is the 12I-12 in FIG. 6 (B).
The profile along the line I, (J) is the profile shown in FIG.
This is a profile along the line J-12J. FIG.
As shown in (J), the p-type impurity 14 is introduced so as to have a concentration lower than the concentration of the n-type impurity contained in the n-type wells 8-2, 12-1, and 12-2. To p
-Form the mold wells 15-1 and 15-2. In this embodiment, after forming the element isolation region 2 (LOCOS), p-type impurities 14 for forming the p − -type wells 15-1 and 15-2 are ion-implanted. For this reason, as shown particularly well in FIG.
-1, 15-2 are element isolation regions 2 (LOCO
Under S), the depth is shallower than the portion under the element region 3 according to the cross-sectional shape of the element isolation region 2.

The p-type region 13 pn separated from the substrate 1 (see FIG. 5B) has p-type regions 13 not connected to the substrate 1.
In order to form the mold well 15-2, for example, the acceleration voltage at the time of ion implantation of the p-type impurity 14 is changed to the n-type impurity 11 for forming the buried n-type wells 12-1 and 12-2. Lower than the acceleration voltage at the time of ion implantation,
The implantation may be performed for a shallower portion of the substrate 1.

Further, the p-type wells 15-1 and 15-2
Is formed by adding a p-type impurity to the p-type substrate 1 originally, so that the concentration of the p-type impurity is higher than that of the substrate 1.

After ion implantation of the p-type impurity 14 forming the p − -type wells 15-1 and 15-2, the photoresist film 9 is not removed, and the photoresist film 9 is used as a mask to form a transistor. P-type or n-type ions for adjusting the threshold voltage may be implanted into the substrate 1. The ion implantation for adjusting the threshold voltage is performed as necessary.

Next, as shown in FIGS. 7A to 7D,
The photoresist film 9 is removed from the substrate 1.

Next, as shown in FIGS. 8A to 8D,
The buffer oxide film 4 is removed from above the element region 3. As a result, the element region 3 is provided on the surface of the substrate 1 (in this embodiment, the n-type well 8-1, the p-type wells 15-1, 15-
2 each surface) is exposed.

Next, as shown in FIGS. 9A to 9D,
The surface of the substrate 1 (silicon) exposed in the element region 3 is thermally oxidized, for example, to form a gate oxide film 16 on the surface of the element region 3.

Next, as shown in FIGS. 10A to 10D, a conductive film serving as a gate electrode of a transistor, for example, polysilicon is formed on the structure shown in FIGS. 9A to 9D. A stacked film with a tungsten silicide film is formed. Next, the laminated film is patterned to form a gate electrode 17. Then, according to a well-known method, a p-type impurity for forming a p-type source / drain is doped with an n-type well 8.
-1 is implanted to form a p-type source region 18S and a p-type drain region 18D. Then, according to a well-known method, an n-type impurity for forming an n-type source / drain is ion-implanted into the p − -type wells 15-1 and 15-2, and the n-type source regions 19S-1, 19S-2, The n-type drain regions 19D-1 and 19D-2 are formed.

Then, as shown in FIGS. 1A to 1D, an interlayer insulating film 20 made of, for example, a CVD oxide film is formed on the structure shown in FIGS. 10A to 10D. Then, the p-type source / drain regions 18S and 18D and the n-type source / drain regions 19S-
1, 19D-1, 19S-2, and 19D-2 are formed respectively. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 22.
Note that FIG. 1A shows a state in which the interlayer insulating film 20 and the wiring 22 are omitted.

By the manufacturing method described above, the semiconductor integrated circuit device according to the first embodiment of the present invention is completed.

In the semiconductor integrated circuit device as described above, below the p − type well 15-1 connected to the substrate 1,
It has a buried n-type well 12-1. This buried n-type well 12-1 is a p-type well separated from the substrate 1.
-It can be formed using the same mask as the buried n-type well 12-2 formed below the mold well 15-2. Therefore, the buried n-type wells 12-1 and 12-1
The mask for forming 2-2 is a p @-well 15-.
1, 15-2 can be commonly used as a mask.
In the first embodiment, the photoresist film 9 is a common mask.

As described above, according to the first embodiment, an increase in the number of photolithography steps can be suppressed, and an increase in the number of masks can be suppressed. Therefore, a reduction in manufacturing cost can be achieved. In addition, since the number of photolithography steps can be suppressed from increasing, it is possible to reduce the manufacturing cost and also suppress the deterioration in yield. This also contributes to a reduction in manufacturing costs.

Further, in the first embodiment, the impurity concentration of the p − -type well 15-2 separated from the substrate 1 can be made equal to the impurity concentration of the p − -type well 15-1 connected to the substrate 1. Alternatively, it is possible to obtain an effect that the impurity concentration of the p − -type well 15-2 does not need to be restricted by the n-type well 8-2. That is, "the degree of freedom regarding the well concentration design" can be obtained without increasing the number of masks.

In the first embodiment, the n-type well 8
-1, 8-2, embedded n-type wells 12-1, 12
-2, the diffusion / activation of the conductive impurities forming the p @--type wells 15-1 and 15-2 are performed independently. May be performed by a single heat treatment.

After diffusion / activation of conductive impurities constituting n-type wells 8-1 and 8-2, buried n-type wells 12-1 and 12-2 and p-type well 15 are formed. −
Diffusion / activation of the conductive impurities constituting elements 1 and 15-2 may be performed simultaneously.

Further, as in the first embodiment, after forming the element isolation region 2, conductive impurities for forming the n-type well 12-2 and the p − -type wells 15-1 and 15-2 are added to the substrate. The manufacturing method introduced in No. 1 has an advantage that, for example, the accuracy of “alignment” between these wells and the element region 3 can be improved.

For example, the element isolation region 2 is formed on the surface of the substrate 1. Therefore, the element isolation region 2 formed on the surface of the substrate 1 can be used as an "alignment mark" of the mask. By using the element isolation region 2 as an "alignment mark", a mask for forming these wells (the photoresist films 5 and 9 in the first embodiment) is required as compared with a case where an "alignment mark" is separately formed. Therefore, "positioning" can be performed with extremely high accuracy on the element region 3. Therefore, the first
Is a semiconductor integrated circuit device that integrates very fine transistors on a large scale, for example, an EEPROM, a DR,
The present invention can be particularly preferably applied to a memory cell array of various semiconductor memories typified by AM and the like and a well structure of peripheral circuits.

[Second Embodiment] The second embodiment is an example of a semiconductor integrated circuit device having a structure similar to that of the first embodiment. The difference is that the n-type wells 8-1, 8-2, 12-1, 12-
2. To form the p @-wells 15-1 and 15-2.

FIG. 13 is a view showing a semiconductor integrated circuit device according to the second embodiment. FIG. 13 (A) is a plan view, FIG. 13 (B) is a cross-sectional view taken along line BB in FIG. (C) The figure is (A)
FIG. 3D is a cross-sectional view along the line CC in FIG. 3A, and FIG. 3D is a cross-sectional view along the line DD in FIG. FIG. 14 is a profile diagram showing the distribution of impurities in the substrate, and FIG. 14A is a profile along the line 14A-14A in FIG.
13B is a profile along the line 14B-14B in FIG. 13B, FIG. 13C is a profile along the line 14C-14C in FIG. 13B, and FIG. 14D-14 inside
The profile along the line D, FIG.
The profile along the line 14E-14E is shown.

Hereinafter, a semiconductor integrated circuit device according to the second embodiment will be described together with a method of manufacturing the same.

FIGS. 15 to 22 are views showing the semiconductor integrated circuit device according to the second embodiment for each of the main steps. 15A to FIG. 22, FIG.
(B) is a sectional view taken along the line BB in (A), (C)
The figure is a cross-sectional view taken along the line CC in the figure (A), and the figure (D) is a cross-sectional view taken along the line DD in the figure (A).

First, as shown in FIGS. 15A to 15D, the surface of the p-type silicon substrate 1 is thermally oxidized, for example, to form a buffer oxide film 4 on the surface of the substrate 1. Next, a photoresist is applied on the buffer oxide film 4 to form a photoresist film 5. Next, openings 6a and 6b are formed in the photoresist film 5 using a photolithography method. In this embodiment, the opening 6a is formed corresponding to the region where the n-type well is formed, and the opening 6b is formed so as to surround the region where the p @-well separated from the substrate 1 is formed. Is done. Next, the photoresist film 5
Is used as a mask to ion-implant an n-type impurity 7 into the substrate 1. Thereby, the n-type well 8-1 and the substrate 1
Surrounding the region where the p--type well isolated from
N-type impurity 7 for forming mold well 8-2
Introduced within. FIGS. 23A to 23E show n-type wells 8.
4 shows an impurity profile after n-type impurities 7 for forming −1 and 8-2 have been introduced into the substrate 1. (A) The figure is a profile along the 23A-23A line in FIG.
15B is a profile along the line 23B-23B in FIG. 15B, FIG. 15C is a profile along the line 23C-23C in FIG. 15B, and FIG. 23D-23D inside
The profile along the line, FIG.
This is a profile along the line E-23E. FIG.
As shown in (E), the n-type impurity 7 for forming the n-type wells 8-1 and 8-2 is set so that the concentration of the p-type impurity originally contained in the substrate 1 is higher than that of the substrate 1. 1 has been introduced.

Next, as shown in FIGS. 16A to 16D, after removing the photoresist film 5 from the substrate 1, a photoresist is applied again to form a photoresist film 9. Next, openings 10a and 10b are formed in the photoresist film 9 using a photolithography method. In this embodiment, the opening 10a is formed corresponding to a region where a p-type well connected to the substrate 1 is formed, and the opening 10b is formed with a p-type well separated from the substrate 1. Is formed corresponding to the region to be formed. Next, the n-type impurity 11 is ion-implanted into the substrate 1 using the photoresist film 9 as a mask. As a result, the p-
In order to form buried n-type wells 12-1 and 12-2 apart from the surface of the substrate 1, respectively, in the region where the p-type well is formed and in the region where the p-type well is separated from the substrate 1 Of n-type impurity 11 is introduced. FIG.
(F) to (J) show impurity profiles in the substrate 1 after the n-type impurity 11 for forming the n-type wells 12-1 and 12-2 has been introduced. (F) is a view in FIG.
Profile along 23F-23F line, (G) figure is FIG.
16B is a profile along the line 23G-23G, FIG. 16H is a profile along the line 23H-23H in FIG.
(I) is a profile along the line 23I-23I in FIG. 16 (B), and (J) is a profile along the line 23J-23J in FIG. 16 (B). As shown in FIGS. 23F to 23J, the n-type impurity 11 for forming the buried n-type wells 12-1 and 12-2 is a p-type impurity originally contained in the substrate 1. The concentration is introduced into the substrate 1 so as to be higher than the concentration. Further, in order to form the buried n-type wells 12-1 and 12-2 apart from the surface of the substrate 1, for example, acceleration at the time of ion implantation of the n-type impurity 11 is performed in the same manner as in the first embodiment. The voltage is applied to the n-type wells 8-1, 8
The n-type impurity 7 for forming -2 may be implanted into a deeper portion of the substrate 1 at a higher voltage than the acceleration voltage at the time of ion implantation. The n-type impurity 11
May be the same as or different from the n-type impurity 7.

Next, as shown in FIGS. 17A to 17D, the photoresist film 9 is not removed, and the p-type impurity 14 is subsequently removed using the photoresist film 9 as a mask.
Ion implantation. Thereby, the p − well 15-1 connected to the substrate 1 and the p − well 15-1 separated from the substrate 1 are removed.
A p-type impurity 14 for forming the mold well 15-2 is introduced into the substrate 1; FIG. 24 (A) to (E)
For forming p @-wells 15-1 and 15-2
4 shows an impurity profile after a mold impurity is introduced into the substrate 1. 17A is a profile along the line 24A-24A in FIG. 17B, and FIG. 17B is a profile along 24B-24 in FIG. 17B.
The profile along the line B, and FIG.
Profile along line 24C-24C, (D) Figure 17
17B is a profile along the line 24D-24D in FIG. 17B, and FIG. 17E is a profile along the line 24E-24E in FIG. As shown in FIGS. 24A to 24E, a p-type impurity 14 for forming p @-type wells 15-1 and 15-2 is formed.
Is different from the first embodiment, for example, the n-type well 8-
2, 15-1 and 15-2 are introduced into the substrate 1 so as to be higher in concentration than the n-type impurities contained therein. Of course, as in the first embodiment, the p-type impurity 14 is
N contained in the mold wells 8-2, 15-1, 15-2
The impurity may be introduced into the substrate 1 so as to be lower than the concentration of the type impurity.

Further, a p-type region 13 (see FIG. 17B) which is pn-isolated from the substrate 1 has p-type regions 13 not connected to the substrate 1.
In order to form the p-type well 15-2, for example, the acceleration voltage at the time of ion implantation of the p-type impurity 14 is changed to the n-type impurity 11 for forming the buried n-type wells 12-1 and 12-2. Should be lower than the acceleration voltage at the time of ion implantation, so as to be implanted into a shallower portion of the substrate 1.

The p-type impurity 14 for forming the p − -type wells 15-1 and 15-2 adds a p-type impurity to the p-type substrate 1. Therefore, in the region where the p-type impurity 14 is introduced, the concentration of the p-type impurity is higher than in the substrate 1.

After ion implantation of the p-type impurity 14 forming the p − -type wells 15-1 and 15-2, the photoresist film 9 is not removed, and the photoresist film 9 is continuously used as a mask to remove the transistor. P-type or n-type ions for adjusting the threshold voltage may be implanted into the substrate 1. The ion implantation for adjusting the threshold voltage is performed as necessary.

Next, as shown in FIGS. 18A to 18D, after removing the photoresist film 9, the substrate 1 is subjected to a heat treatment, and the n-type impurities 7, 11 and p introduced into the substrate 1 are removed. The impurity 14 is diffused / activated to form n-type wells 8-1, 8-2, 12-1, 12-2 and p-type wells 15-1, 15-2. The buried n-type well 12-1 is formed at a position distant from the surface of the substrate 1, and the buried n-type well 12-2 is separated from the surface of the substrate 1 and formed in the n-type well 8-2. It is formed in contact with. Thereby, the n-type well 12 is
-2 and the n-type well 8-2 provide a p-type region 13 which is pn-isolated from the substrate 1. FIGS. 24 (F) to (J)
2 shows impurity profiles in the substrate 1 after diffusing / activating the conductive impurities 7, 11, and 14 introduced into the substrate 1, respectively. (F) The figure shows 24F-24 in FIG. 18 (B).
The profile along the line F, (G) is a view in FIG.
Profile along the 24G-24G line, (H) Figure 18
FIG. 18 (B) shows a profile along the 24H-24H line, FIG. 18 (I) shows a profile along the 24I-24I line in FIG. 18 (B),
(J) is a profile along line 24J-24J in FIG. 18 (B). As particularly shown in FIGS. 24 (G), (H) and (J), the impurity concentration of the n-type wells 12-1 and 12-2 is different from that of the first embodiment, and
15-2 is lower than the impurity concentration. But,
The p- wells 15-1 and 15-2 are connected to the n-well 12-
1 and 12-2, the substrate 1
An n-type region appears in a deep part of the region. This n-type region constitutes buried n-type wells 12-1 and 12-2.

Further, as particularly shown in FIG.
The impurity concentration of the n-type well 15-2 is
24G-24G in FIG. 18B.
In the cross section along the line, p-type conductivity is shown near the surface of the substrate 1. However, as shown in FIG.
In the cross section along line 24F-24F in FIG. 8B, there is no p-type well 15-2, and the substrate 1 shows n-type conductivity. As described above, when the impurity concentration of the p − -type well 15-2 is higher than the impurity concentration of the n-type well 8-2,
By terminating the edge of -2 into n-type well 8-2, p-type well 15-2 can be separated from substrate 1 by a pn junction.

Therefore, the well structure according to the second embodiment has the same structure as the well structure according to the first embodiment.

Next, as shown in FIGS. 19A to 19D, an element isolation region 2 is formed on the surface of the p-type silicon substrate 1, and an element region 3 is partitioned on the surface of the substrate 1. In this embodiment, the element isolation region 2 is a LOCOS film formed using the LOCOS method.

Next, the buffer oxide film 4 is removed from above the element region 3 as shown in FIGS.
As a result, the element region 3 has the surface of the substrate 1 (in this embodiment, the n-type well 8-1, the p − -type well 15-1, 1).
5-2).

Next, as shown in FIGS. 21A to 21D, the surface of the substrate 1 (silicon) exposed in the element region 3 is thermally oxidized, for example, so that the gate oxide film 16 is formed on the surface of the element region 3.
To form

Next, as shown in FIGS. 22A to 22D, a conductive film serving as a gate electrode of a transistor, for example, polysilicon is formed on the structure shown in FIGS. 21A to 21D. A stacked film with a tungsten silicide film is formed. Next, the laminated film is patterned to form a gate electrode 17. Next, according to a known method, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 8-1 to form a p-type source region 18S and a p-type drain region 18D. Then, according to a well-known method, an n-type impurity for forming an n-type source / drain is ion-implanted into the p − -type wells 15-1 and 15-2, and the n-type source regions 19S-1, 19S-2, The n-type drain regions 19D-1 and 19D-2 are formed.

Next, as shown in FIGS. 13A to 13D, an interlayer insulating film 20 made of, for example, a CVD oxide film is formed on the structure shown in FIGS. 22A to 22D. Then, the p-type source / drain regions 18S and 18D and the n-type source / drain regions 19S-
1, 19D-1, 19S-2, and 19D-2 are formed respectively. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 22.
Note that FIG. 13A shows a state in which the interlayer insulating film 20 and the wiring 22 are omitted.

By the manufacturing method as described above, the semiconductor integrated circuit device according to the second embodiment of the present invention is completed.

The semiconductor integrated circuit device as described above has a buried n-type well 12-1 under the p − -type well 15-1, as in the first embodiment. The buried n-type well 12-1 is a p-type well 15-1.
Buried n-type well 12-2 formed underneath
It can be formed at the same time. Therefore, the mask for forming the buried n-type wells 12-1 and 12-2 is p-type.
This can be shared with a mask for forming the mold wells 15-1 and 15-2.

Therefore, also in the second embodiment,
As in the first embodiment, the effect that the number of masks can be reduced and the manufacturing cost can be reduced can be obtained.

In the second embodiment, the n-type well 8
-1, 8-2, embedded n-type wells 12-1, 12
-2, the diffusion / activation of the conductive impurities forming the p-type wells 15-1 and 15-2 is performed by a single heat treatment. May be performed independently as in the first embodiment.

After diffusion / activation of the conductive impurities constituting n-type wells 8-1 and 8-2, buried n-type wells 12-1 and 12-2 and p-type well 15 are formed. −
Diffusion / activation of the conductive impurities constituting elements 1 and 15-2 may be performed simultaneously.

[Third Embodiment] In the first and second embodiments, different wells, that is, buried n-type wells and p-type wells are respectively formed by using a common mask, thereby reducing the number of masks. Reduction and the number of processes.

The third embodiment is an example of a semiconductor integrated circuit device having gate oxide films having different thicknesses. In the third embodiment, the number of masks and the number of steps are reduced by using a common mask for each of the well forming step and the step for changing the thickness of the gate oxide film.

FIG. 25 is a sectional view of a semiconductor integrated circuit device according to the third embodiment.

FIGS. 26A to 26C and FIGS.
(D) is sectional drawing which showed the semiconductor integrated circuit device which concerns on 3rd Embodiment for every main manufacturing process, respectively.

Hereinafter, a semiconductor integrated circuit device according to the third embodiment will be described together with a method of manufacturing the same.

First, as shown in FIG. 26A, an element isolation region 2 is formed on the surface of a p-type silicon
The element region 3 is partitioned on the surface of the device. In this embodiment, the element isolation region 2 is a LOCOS formed using the LOCOS method.
This is an S film. Next, the surface of the substrate 1 (silicon) exposed to the element region 3 is thermally oxidized, for example, to form a first gate oxide film 31 on the surface of the element region 3.

Next, as shown in FIG.
Is coated on the substrate to form a photoresist film 32. Next, an opening 33 is formed in the photoresist film 32 by using a photolithography method. In this embodiment, the opening 33 is formed corresponding to the region where the n-type well is formed. Next, the photoresist film 32
Is used as a mask to ion-implant an n-type impurity 7 into the substrate 1. Thereby, an n-type well 8 is formed.

Next, as shown in FIG.
After the photoresist film 32 is removed from above, a photoresist is applied again to form a photoresist film 34. Next, an opening 35 is formed in the photoresist film 34 by using a photolithography method. In this embodiment, the opening 35 is formed corresponding to the region where the p-type well connected to the substrate 1 is formed. Next, using the photoresist film 34 as a mask, the p-type impurity 14 is
Ion implantation. Thus, a p-type well 15 connected to the substrate 1 is formed.

Since the p − -type well 15 is originally formed by adding a p-type impurity to the p-type substrate 1, the concentration of the p-type impurity is higher than that of the substrate 1.

Next, as shown in FIG.
The photoresist film 34 is not removed from above, but the first gate oxide film 31 exposed from the opening 35 is removed using the photoresist film 34 as a mask. As a result, the surface of the substrate 1 (p − well 15 in this embodiment) is exposed in the element region 3 exposed from the opening 35.

Next, as shown in FIG.
Is removed from above.

Next, as shown in FIG. 27C, the surface of the substrate 1 exposed to the element region 3, in this embodiment, the surface of the p − -type well 15 is subjected to, for example, thermal oxidation to form a surface of the element region 3. A second gate oxide film 36 is formed. At this time, additional thermal oxidation is performed on the first gate oxide film 31 to increase its thickness. As a result, a thick gate oxide film 31 is obtained on the n-type well 8 and a thin gate oxide film 36 is obtained on the p − -type well 15.

Next, as shown in FIG.
A conductive film serving as a gate electrode of a transistor, for example, a stacked film of polysilicon and a tungsten silicide film is formed over the structure illustrated in FIG. Next, the laminated film is patterned to form a gate electrode 17. Then
According to a known method, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 8,
A p-type source region 18S and a p-type drain region 18D are formed. Then, according to a known method, the n-type source /
An n-type impurity for forming a drain is doped into a p-type well 1
5, an n-type source region 19S and an n-type drain region 19D are formed.

Next, as shown in FIG. 25, FIG.
An interlayer insulating film 20 made of, for example, a CVD oxide film is formed on the structure shown in FIG. Next, the interlayer insulating film 20
Then, contact holes 21 communicating with the p-type source / drain regions 18S and 18D and the n-type source / drain regions 19S and 19D are formed. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 22.

By the manufacturing method described above, the semiconductor integrated circuit device according to the third embodiment of the present invention is completed.

In the semiconductor integrated circuit device as described above, the first gate oxide film 31 is removed by using the mask for forming the p − type well 15. That is, a mask for forming the p @-type well 15 and the thin gate oxide film 3 are formed.
6 can be used in common with a mask. In the third embodiment, the photoresist film 34 is a common mask.

Therefore, according to the third embodiment, in the semiconductor integrated circuit device having the gate oxide films having different thicknesses, the number of masks can be reduced and the manufacturing process can be reduced as in the first and second embodiments. The effect that cost can be reduced can be obtained.

[Fourth Embodiment] The fourth embodiment is an example of a semiconductor integrated circuit device having gate oxide films having different thicknesses, similarly to the third embodiment. The difference is that the thin gate oxide film is provided not only on the p-type well but also on both the n-type well and the p-type well.

FIG. 28 is a sectional view of a semiconductor integrated circuit device according to the fourth embodiment. 29 is a profile diagram showing the distribution of impurities in the substrate. FIG. 29A is a profile along the line 29A-29A in FIG. 28, and FIG. 29B is a profile along the line 29B-29B in FIG. 28 (C) show profiles along line 29C-29C in FIG.

Hereinafter, a semiconductor integrated circuit device according to the fourth embodiment will be described along with a method of manufacturing the same.

FIGS. 30A to 30C and FIGS.
(D) is sectional drawing which showed the semiconductor integrated circuit device which concerns on 4th Embodiment for every main manufacturing process.

First, as shown in FIG. 30A, an element isolation region 2 is formed on the surface of a p-type silicon
The element region 3 is partitioned on the surface of the device. In this embodiment, the element isolation region 2 is a LOCOS formed using the LOCOS method.
This is an S film. Next, the surface of the substrate 1 (silicon) exposed to the element region 3 is thermally oxidized, for example, to form a first gate oxide film 31 on the surface of the element region 3. FIG. 32 (A)-
(C) Substrate 1 after forming first gate oxide film 31
2 shows an impurity profile in the inside. (A) Figure 30
30A is a profile along the line 32A-32A, FIG. 30B is a profile along the line 32B-32B in FIG.
FIG. 30C is a profile along the line 32 C- 32 C in FIG. As shown in FIGS. 32A to 32C, after forming the first gate oxide film 31, the only conductive impurities in the substrate 1 are p-type impurities contained in the substrate 1.

Next, as shown in FIG.
Is coated on the substrate to form a photoresist film 32. Next, an opening 33 is formed in the photoresist film 32 by using a photolithography method. In this embodiment, the opening 33 is formed corresponding to the region where the n-type well is formed. Next, the photoresist film 32
Is used as a mask to ion-implant an n-type impurity 7 into the substrate 1. Thereby, an n-type well 8 is formed. FIG.
Substrate 1 after forming n-type well 8 in 2 (D) to (F)
2 shows an impurity profile in the inside. (D) Figure 30
30B is a profile along the line 32D-32D, FIG. 30E is a profile along the line 32E-32E in FIG.
FIG. 30C is a profile along the line 32F-32F in FIG. As shown in FIGS. 32 (D) to (F), n
The type impurity 7 is introduced so as to be higher than the concentration of the p-type impurity originally contained in the substrate 1 to form an n-type well 8 in the substrate 1. In this embodiment, after forming the element isolation region 2 (LOCOS), an n-type impurity 7 for forming an n-type well 8 is ion-implanted. For this reason, similarly to the first embodiment, as shown particularly well in FIG. 30B, the n-type well 8 is formed in the element isolation region 2 (LO
Under COS), it is shallower in accordance with the cross-sectional shape of the element isolation region 2 than the portion under the element region 3.

Next, as shown in FIG.
After the photoresist film 32 is removed from above, a photoresist is applied again to form a photoresist film 34. Next, an opening 35 'is formed in the photoresist film 34 by using a photolithography method. In this embodiment, the openings 35 'are formed corresponding to the region where the p-type well connected to the substrate 1 is formed and the region where the n-type well 8 is formed. Next, the p-type impurity 14 is ion-implanted into the substrate 1 using the photoresist film 34 as a mask. Thus, a p-type well 15 'connected to the substrate 1 is formed. 32 (G) to (I) show p
-Shows the impurity profile after forming the mold well 15 '. (G) is a profile along the line 32G-32G in FIG. 30 (C), and (H) is a profile along 32H-32H in FIG. 30 (C).
The profile along the line, (I) is the profile shown in FIG.
This is a profile along the line I-32I. FIG. 32 (G)-
As shown in (I), the p-type impurity 14 is
Is introduced so as to be lower than the concentration of the n-type impurity contained in the semiconductor. Thus, the p − -type well 15 ′ is formed from the inside of the substrate 1 to the inside of the n-type well 8. In this embodiment, the element isolation region 2 (LOCOS)
Is formed, ions of a p-type impurity 14 for forming a p @--type well 15 'are implanted. Therefore, FIG.
As is particularly well shown in (C), the p-type well 15 '
Under the element isolation region 2 (LOCOS), the depth is shallower in accordance with the cross-sectional shape of the element isolation region 2 than under the element region 3.

Since the p − -type well 15 ′ is formed by adding a p-type impurity to the p-type substrate 1 originally,
The concentration of the p-type impurity is higher than that of the substrate 1.

Further, the p-type well 15 'is the n-type well 8
However, as described above, the p-type impurity 14
The n-type well 8 is introduced so as to be lower in concentration than the n-type impurity contained in the n-type well 8. For this reason, even if the p − -type well 15 ′ is formed in the n-type well 8,
Indicates mold conductivity.

Next, as shown in FIG.
Without removing the photoresist film 34 from above, the first gate oxide film 31 exposed from the opening 35 'is removed using the photoresist film 34 as a mask. As a result, the element region 3 exposed from the opening 35 'is provided on the surface of the substrate 1 (in this embodiment, the n-type well 8 and the p-type
The mold well 15 ') is exposed.

Next, as shown in FIG.
Is removed from above.

Next, as shown in FIG. 31C, the surface of the substrate 1 exposed to the element region 3, that is, the surface of the n-type well 8 and the p − -type well 15 ′ in this embodiment is, for example, thermally oxidized. A second gate oxide film 36 is formed on the surface of the element region 3. At this time, additional thermal oxidation is performed on the first gate oxide film 31 to increase its thickness. As a result, a thick gate oxide film 31 is obtained on the substrate 1 and the n-type well 8 is formed.
And a thin gate oxide film 36 is obtained on each of the p-type wells 15 '.

Next, as shown in FIG.
A conductive film serving as a gate electrode of a transistor, for example, a stacked film of polysilicon and a tungsten silicide film is formed over the structure illustrated in FIG. Next, the laminated film is patterned to form a gate electrode 17. Then
According to a known method, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 8,
A p-type source region 18S and a p-type drain region 18D are formed. Then, according to a known method, the n-type source /
An n-type impurity for forming a drain is
-Ions are implanted into each of the type wells 15 'to form n-type source regions 19S-1, 19S-2 and n-type drain regions 19D.
-1, 19D-2 are formed.

Next, as shown in FIG. 28, FIG.
An interlayer insulating film 20 made of, for example, a CVD oxide film is formed on the structure shown in FIG. Next, the interlayer insulating film 20
In addition, p-type source / drain regions 18S, 18D, n-type source / drain regions 19S-1, 19S-2, 19D-
A contact hole 21 communicating with each of Nos. 1 and 19D-2 is formed. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 22.

By the manufacturing method as described above, the semiconductor integrated circuit device according to the fourth embodiment of the present invention is completed.

In the semiconductor integrated circuit device as described above, the first gate oxide film 31 is removed using a mask for forming the p − -type well 15 ′. That is, a mask for forming the p @-type well 15 'and a mask for obtaining the thin gate oxide film 36 can be used in common. In the fourth embodiment, the photoresist film 34 is a common mask.

The p − -type well 15 ′ has a p-type impurity that does not reverse the conductivity type of the n-type well 8.
Further, the p − -type well 15 ′ is formed from the region of the substrate 1 where the p − -type well 15 ′ is formed to the inside of the n-type well 8. Therefore, an opening 35 'formed in the photoresist film 34 for forming the p--type well 15' can be opened also on the n-type well 8. Therefore, the thin gate oxide film 36 can be formed not only on the p − well 15 ′ but also on both the n well 8 and the p − well 15 ′ without increasing the number of masks.

Therefore, according to the fourth embodiment, in a semiconductor integrated circuit device having gate oxide films having different thicknesses, the number of masks can be reduced as in the first to third embodiments. The effect that cost can be reduced can be obtained.

[Fifth Embodiment] The fifth embodiment is an example of a semiconductor integrated circuit device having gate oxide films having different thicknesses, as in the fourth embodiment. The difference is that p + has a higher impurity concentration than the p-type well.
And having a thin gate oxide film on each of the p +, n, and p- wells.

FIG. 33 is a sectional view of a semiconductor integrated circuit device according to the fifth embodiment. FIG. 34 is a profile diagram showing the distribution of impurities in the substrate. FIG. 34 (A) is a profile along the line 34A-34A in FIG. 33, and FIG. 34 (B) is a profile along the line 34B-34B in FIG. (C) is a profile along line 34C-34C in FIG. 33, (D)
The figure shows the profile along the line 34D-34D in FIG.

Hereinafter, a semiconductor integrated circuit device according to the fifth embodiment will be described together with a method of manufacturing the same.

FIGS. 35 (A), (B) -FIG. 38 (A),
(B) is sectional drawing which showed the semiconductor integrated circuit device which concerns on 5th Embodiment for every main manufacturing process, respectively.

First, as shown in FIG. 35A, an element isolation region 2 is formed on the surface of a p-type silicon
The element region 3 is partitioned on the surface of the device. In this embodiment, the element isolation region 2 is a LOCOS formed using the LOCOS method.
This is an S film. Next, the surface of the substrate 1 (silicon) exposed to the element region 3 is thermally oxidized, for example, to form a first gate oxide film 31 on the surface of the element region 3. FIG. 39 (A)-
(D) Substrate 1 after forming first gate oxide film 31
2 shows an impurity profile in the inside. (A) Figure 35
FIG. 35 (A) is a profile along the line 39A-39A, FIG. 35 (B) is a profile along the line 39B-39B in FIG. 35 (A),
(C) is a profile along the line 39C-39C in FIG. 35 (A), and (D) is a profile along the line 39D-39D in FIG. 35 (A). As shown in FIGS. 39A to 39D, after the first gate oxide film 31 is formed, the only conductive impurities in the substrate 1 are the p-type impurities contained in the substrate 1.

Next, as shown in FIG.
Is coated on the substrate to form a photoresist film 32. Next, an opening 33 is formed in the photoresist film 32 by using a photolithography method. In this embodiment, the opening 33 is formed corresponding to the region where the n-type well is formed. Next, the photoresist film 32
Is used as a mask to ion-implant an n-type impurity 7 into the substrate 1. Thereby, an n-type well 8 is formed. FIG.
Substrate 1 after forming n-type well 8 in 9 (E)-(H)
2 shows an impurity profile in the inside. (E) Figure 35
FIG. 35 (B) is a profile along the line 39E-39E, FIG. 35 (F) is a profile along the line 39F-39F in FIG. 35 (B),
(G) shows the profile along the line 39G-39G in FIG. 35 (B), and (H) shows the profile along the line 39H-39H in FIG. 35 (B). As shown in FIGS. 39E to 39H, the n-type impurity 7 is introduced so as to be higher than the concentration of the p-type impurity originally contained in the substrate 1, and the n-type well 8 is formed in the substrate 1. To form Further, in this embodiment, after forming the element isolation region 2 (LOCOS), n
An n-type impurity 7 for forming a mold well 8 is ion-implanted. Therefore, as in the first embodiment, FIG.
The n-type well 8 is shallower according to the cross-sectional shape of the element isolation region 2 below the element isolation region 2 (LOCOS) than the portion under the element region 3 as particularly well shown in FIG.

Next, as shown in FIG.
After the photoresist film 32 is removed from above, a photoresist is applied again to form a photoresist film 41. Next, an opening 42 is formed in the photoresist film 41 using a photolithography method. In this embodiment, the openings 42 are formed corresponding to the regions where the high-concentration p + wells connected to the substrate 1 are formed. Then
Using the photoresist film 41 as a mask, a p-type impurity 43 is formed.
Is implanted into the substrate 1. As a result, a low-concentration p-type well 44 is first formed. Thus, the high concentration p
As described later, the reason why the low-concentration p-type well 44 is first formed in the region where the + -type well is formed is that the high-concentration p + -type well is formed by two ion implantations in this embodiment. It is because it forms. FIG. 40 (A)-
(D) shows an impurity profile in the substrate 1 after the formation of the low-concentration p − -type well 44. (A) Figure 36
36A is a profile along the line 40A-40A, FIG. 36B is a profile along the line 40B-40B in FIG.
(C) is a profile along the line 40C-40C in FIG. 36 (A), and (D) is a profile along the line 40D-40D in FIG. 36 (A). As shown in FIGS. 40A to 40D, the p − -type well 44 is formed in the substrate 1 by introducing the p-type impurity 43 into the substrate 1. Also,
In this embodiment, the element isolation region 2 (LOCO
After the formation of S), a p-type impurity 43 for forming a p-type well 44 is ion-implanted. Therefore, FIG.
As shown particularly well in FIG. 3A, the p − -type well 44 is formed under the element isolation region 2 (LOCOS) and the element region 3.
It is shallower than the lower part according to the cross-sectional shape of the element isolation region 2. Further, since the p − -type well 44 is originally formed by adding a p-type impurity to the p-type substrate 1, the concentration of the p-type impurity is higher than that of the substrate 1.

Next, as shown in FIG.
After removing the photoresist film 41 from above, a photoresist is applied again to form a photoresist film 34. Next, an opening 35 '' is formed in the photoresist film 34 by using a photolithography method. In this embodiment, the opening 35 ″ is a low-concentration p-
The region where the type well is formed, the region where the n-type well 8 is formed, and the region where the p − type well 44 is formed are respectively formed. Next, the photoresist film 34
Is used as a mask to ion-implant p-type impurity 14 into substrate 1. As a result, a p-type well 15 '' connected to the substrate 1 is formed. FIGS. 40 (E) to 40 (H) show p-
7 shows an impurity profile in the substrate 1 after forming the mold well 15 ″. (E) The figure shows 40E-40 in FIG. 36 (B).
The profile along line E, (F) is a view in FIG.
Profile along 40F-40F line, (G) Figure 36
36B is a profile along the 40G-40G line, and FIG. 36H is a profile along the 40H-40H line in FIG. As shown in FIGS. 40E to 40H, the p-type impurity 14 is introduced so as to have a concentration lower than the concentration of the n-type impurity contained in the n-type well 8. Thereby, the p − -type well 15 ″ is formed from the inside of the substrate 1 to the inside of the n-type well 8. Further, the p-type well 15 "is formed in the p-type well 44. As a result, the impurity concentration of the p − -type well 44 increases. This is because the p-type impurity 14 is additionally introduced into the p − -type well 44. The portion where the density has increased is denoted by the reference symbol “p +”,
Call it p + well 44 '.

In this embodiment, after the element isolation region 2 (LOCOS) is formed, the p- type well 1 is formed.
P-type impurities 14 for forming 5 ″ are ion-implanted. Therefore, as particularly well shown in FIG.
The mold well 15 ″ is located below the element isolation region 2 (LOCOS) more than the portion below the element region 3.
Is shallower in accordance with the cross-sectional shape of.

Since the p − -type well 15 ″ is formed by adding a p-type impurity to the p-type substrate 1 originally, the concentration of the p-type impurity is higher than that of the substrate 1.

Further, the p − -type well 15 ″ is also formed in the n-type well 8, but as described above,
Is introduced so as to be lower than the concentration of the n-type impurity contained in the n-type well 8. For this reason, similarly to the fourth embodiment, even if the p − -type well 15 ″ is formed in the n-type well 8, the n-type well 8 exhibits n-type conductivity.

Next, as shown in FIG.
The photoresist film 34 is not removed from above, and the photoresist film 34 is subsequently used as a mask to form an opening 35 ''.
The first gate oxide film 31 exposed from is removed. Thereby, the element region 3 exposed from the opening 35 '' has
The surface of the substrate 1, in this embodiment, an n-type well 8, p +
The mold well 44 'and p-type well 15''are exposed.

Next, as shown in FIG.
Is removed from above.

Next, as shown in FIG. 38A, the surface of the substrate 1 exposed to the element region 3, that is, the n-type well 8, the p + -type well 44 'and the p--type well 1 in this embodiment.
The surface of 5 ″ is thermally oxidized, for example, to form a second gate oxide film 36 on the surface of the element region 3. At this time, additional thermal oxidation is performed on the first gate oxide film 31 to increase its thickness. As a result, a thick gate oxide film 31 is obtained on the substrate 1. In addition, n-type well 8 and p + -type well 4
A thin gate oxide 36 is obtained on each of the 4 'and p- wells 15''.

Next, as shown in FIG.
A conductive film serving as a gate electrode of a transistor, for example, a stacked film of polysilicon and a tungsten silicide film is formed over the structure illustrated in FIG. Next, the laminated film is patterned to form a gate electrode 17. Then
According to a known method, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 8,
A p-type source region 18S and a p-type drain region 18D are formed. Then, according to a known method, the n-type source /
An n-type impurity for forming a drain is ion-implanted into the substrate 1, the p + -type well 44 'and the p--type well 15''to form n-type source regions 19S-1 to 19S-3,
The n-type drain regions 19D-1 to 19D-3 are formed.

Next, as shown in FIG. 33, FIG.
An interlayer insulating film 20 made of, for example, a CVD oxide film is formed on the structure shown in FIG. Next, the interlayer insulating film 20
In addition, p-type source / drain regions 18S, 18D, n-type source / drain regions 19S-1 to 19S-3, 19D-
A contact hole 21 communicating with each of 1 to 19D-3 is formed. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 22.

By the manufacturing method as described above, the semiconductor integrated circuit device according to the fifth embodiment of the present invention is completed.

In the semiconductor integrated circuit device as described above, the first gate oxide film 31 is removed by using a mask for forming the p − -type well 15 ″. That is, a mask for forming the p @-type well 15 "and a mask for obtaining the thin gate oxide film 36 can be used in common. In the fifth embodiment, the photoresist film 34 is a common mask.

The p − -type well 15 ″ has a p-type impurity that does not reverse the conductivity type of the n-type well 8, as in the fourth embodiment. This p-type well 15 ''
Are formed from the region of the substrate 1 where the p-type well 15 '' is formed, to the inside of the n-type well 8, and further to the p-type well 44. In the p-type well 44, p-
Since the p-type impurity 14 forming the mold well 15 ″ is additionally introduced, the impurity concentration increases, and p +
It is converted to a mold well 44 '. As a result, p
A -type well 15 "and ap + -type well 44 'having a higher impurity concentration than the p- -type well 15" are formed.

The opening 3 formed in the photoresist film 34 for forming the p − -type well 15 ″ as described above.
5 '' can also be opened above the n-type well 8 and the p-type well 44. Therefore, without increasing the number of masks, the thin gate oxide film 36 is formed in the n-type well 8, the p + -type well 44 ′ having a high impurity concentration and the p − -type well 15 ″.
Can be formed on both.

Therefore, according to the fifth embodiment, in the semiconductor integrated circuit device having the gate oxide films having different thicknesses, the number of masks can be reduced, as in the first to fourth embodiments. The effect that cost can be reduced can be obtained.

In the fifth embodiment, p
-Photoresist film 3 for forming mold well 15 ''
4 was also opened on the n-type well 8,
The opening 35 '' may be formed only on the region for forming the p-type well 15 '' and only on the region for forming the high concentration p + well 44 '.

[Sixth Embodiment] The sixth embodiment is an example of a semiconductor integrated circuit device having the same gate oxide film and well structure as the fifth embodiment. The difference is that the element isolation region is formed by STI (Shallow Trench Isola
Option).

FIG. 41 is a diagram showing a semiconductor integrated circuit device according to the sixth embodiment. FIG. 41 (A) is a plan view, FIG. 41 (B) is a cross-sectional view taken along line BB in FIG. (C) The figure is (A)
It is sectional drawing which follows the CC line | wire in a figure. FIG. 42 is a profile diagram showing the distribution of impurities in the substrate.
(A) is a profile along the line 42A-42A in FIG. 41 (B), (B) is a profile along the line 42B-42B in FIG. 41 (B), and (C) is FIG. 41 (B). 42C-42 in
The profile along the line C. FIG.
The profile along the line 42D-42D is shown.

Hereinafter, a semiconductor integrated circuit device according to the sixth embodiment will be described along with a method of manufacturing the same.

FIGS. 43 to 53 are views showing the semiconductor integrated circuit device according to the sixth embodiment for each of the main manufacturing steps. 43 to 53, (A) is a plan view, (B) is a cross-sectional view taken along line BB in (A),
FIG. 3C is a cross-sectional view taken along line CC in FIG.

First, as shown in FIGS. 43A to 43C, the surface of the p-type silicon substrate 1 is thermally oxidized, for example, to form a first gate oxide film 31 on the surface of the substrate 1. Next, a photoresist is applied on the first gate oxide film 31 to form a photoresist film 32. Next, an opening 33 is formed in the photoresist film 32 by using a photolithography method. In this embodiment, the opening 3
3 is formed corresponding to the region where the n-type well is formed. Then, using the photoresist film 32 as a mask, n
Type impurities 7 are ion-implanted into the substrate 1. This allows
An n-type well 8 is formed. 54A to 54D show n.
4 shows an impurity profile after an n-type impurity 7 for forming a mold well 8 has been introduced into the substrate 1. (A) The figure is a profile along the line 54A-54A in FIG.
(B) is a profile along line 54B-54B in FIG. 43 (B), (C) is a profile along line 54C-54C in FIG. 43 (B), and (D) is FIG. 43 (B). 54D-54 in
This is a profile along the line D. FIG. 54 (A) to (D)
As shown in FIG. 5, the n-type impurity 7 for forming the n-type well 8 is introduced into the substrate 1 so as to have a higher concentration than the p-type impurity originally contained in the substrate 1.

Next, as shown in FIGS. 44A to 44C, after removing the photoresist film 32 from above the substrate 1,
A photoresist is applied again to form a photoresist film 41. Next, an opening 42 is formed in the photoresist film 41 using a photolithography method. In this embodiment, the openings 42 are formed corresponding to the regions where the high-concentration p + wells connected to the substrate 1 are formed.
Next, the p-type impurity 43 is ion-implanted into the substrate 1 using the photoresist film 41 as a mask. As a result, a low-concentration p-type well 44 is first formed. As described later, the reason why the low-concentration p− well 44 is first formed in the region where the high-concentration p + well is formed is that the high-concentration p + well is formed in this embodiment. 2
This is because it is formed by ion implantation twice. FIG.
(E) to (H) show the impurity profiles after the formation of the low-concentration p − -type well 44. (E) FIG.
44B is a profile along the line 54E-54E, FIG. 44F is a profile along the line 54F-54F in FIG.
(G) is a profile along the line 54G-54G in FIG. 44 (B), and (H) is a profile along the line 54H-54H in FIG. 44 (B). As shown in FIGS. 54 (E) to 54 (H), the p − -type well 44 is formed in the substrate 1 by introducing the p-type impurity 43 into the substrate 1. This p
Since the p-type well 44 is originally formed by adding a p-type impurity to the p-type substrate 1, the concentration of the p-type impurity is higher than that of the substrate 1.

Next, as shown in FIGS. 45 (A) to 45 (C), after removing the photoresist film 41 from above the substrate 1,
A photoresist is applied again to form a photoresist film 34. Next, an opening 35 '' is formed in the photoresist film 34 by using a photolithography method. In this embodiment, the opening 35 '' is formed with a region where a low-concentration p-type well connected to the substrate 1 is formed, a region where the n-type well 8 is formed, and a p-type well 44. Are formed corresponding to the respective regions. Next, using the photoresist film 34 as a mask, the p-type impurity 14 is
Ion implantation. As a result, a p-type well 15 '' connected to the substrate 1 is formed. FIG. 54 (I)-
(L) shows an impurity profile after the p − -type well 15 ″ is formed. (I) is a drawing of 54I- in FIG. 45 (B).
The profile along the 54I line, the (J) diagram is the profile along the 54J-54J line in FIG. 45 (B), and the (K) diagram is FIG.
45B is a profile along the line 54K-54K, and FIG. 45L is a profile along the line 54L-54L in FIG. As shown in FIGS. 54 (I) to (L), p-type impurity 14 is introduced so as to have a lower concentration than the n-type impurity contained in n-type well 8. Thereby, the p − -type well 15 ″ is formed from the inside of the substrate 1 to the inside of the n-type well 8. Further, the p-type well 15 "is formed in the p-type well 44. As a result, the impurity concentration of the p − -type well 44 increases. This is because the p-type impurity 14 is additionally introduced into the p − -type well 44. The portion where the density has increased is denoted by the reference symbol “p +”,
Call it p + well 44 '.

Since the p − -type well 15 ″ is formed by adding a p-type impurity to the p-type substrate 1 originally, the concentration of the p-type impurity is higher than that of the substrate 1.

Further, the p − -type well 15 ″ is formed in the n-type well 8.
Is introduced so as to be lower than the concentration of the n-type impurity contained in the n-type well 8. Therefore, similarly to the fourth and fifth embodiments, the p − -type well 1 is placed in the n-type well 8.
Even if 5 ″ is formed, n-type well 8 shows n-type conductivity.

Next, as shown in FIGS. 46 (A) to 46 (C), the photoresist film 34 is not removed from above the substrate 1 and the opening 35 ″ is continuously formed by using the photoresist film 34 as a mask. The first gate oxide film 31 exposed from is removed. As a result, the surface of the substrate 1 (in this embodiment, the n-type well 8 and the p + -type well 4
4 ', p-type well 15'') is exposed.

Next, as shown in FIGS. 47A to 47C, the photoresist film 34 is removed from above the substrate 1.

Next, as shown in FIGS. 48A to 48C, the surface of the substrate 1 is thermally oxidized, for example, to form a second gate oxide film 36. In this embodiment, the second gate oxide film 36 is formed on the surfaces of the n-type well 8, the p + -type well 44 'and the p--type well 15''. At this time, additional thermal oxidation is performed on the first gate oxide film 31 to increase its thickness. As a result, a thick gate oxide film 31 is obtained on the substrate 1. Also, an n-type well 8,
A thin gate oxide film 36 is obtained on each of the p + well 44 'and the p- well 15''.

Next, as shown in FIGS. 49 (A)-(C), conductive polysilicon and, for example, silicon nitride are sequentially deposited on the structure shown in FIGS. 48 (A)-(C). Then, a conductive polysilicon film 51 and a silicon nitride film 52 are formed.

Next, as shown in FIGS. 50A to 50C, for example, the silicon nitride film 52 is patterned in a form corresponding to the formation pattern of the element region 3. Next, using the patterned silicon nitride film 52 as a mask, the conductive polysilicon film 51 and the substrate 1 are sequentially etched to form grooves 5 corresponding to the formation pattern of the element isolation region.
Form 3 As a result, an island-shaped element region 3 protruding in the substrate 1 is obtained.

Next, as shown in FIGS. 51A to 51C, an insulating film to be an element isolation region, for example, silicon dioxide is deposited on the structure shown in FIGS. 50A to 50C. And
A silicon dioxide film is formed. Next, an etch back method using the silicon dioxide film as a stopper for etching with the silicon nitride film 52 or a CMP (Chemical Mechanical) method.
Then, the silicon dioxide film is buried in the trench 53 by the receding method using the cal polishing method. As a result, an STI type element isolation region 54 is formed.

In this embodiment, the side wall (51SIDE) of the conductive polysilicon film 51 is exposed. However, the side wall (51SIDE) may or may not be exposed.

Next, as shown in FIGS. 52 (A) to 52 (C), a conductive film serving as a gate electrode of a transistor, for example, a conductive film is formed on the structure shown in FIGS. 51 (A) to 51 (C). A polysilicon film 55 is formed. The conductive polysilicon film 55 is electrically connected to the conductive polysilicon film 51, and forms a laminated film with the conductive polysilicon film 51.

Next, as shown in FIGS. 53A to 53C, the gate electrode 17 is formed by patterning the laminated film composed of the conductive polysilicon films 51 and 55. Next, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 8 according to a well-known method to form a p-type source region 18S and a p-type drain region 18D. Then, according to a known method, an n-type impurity for forming an n-type source / drain is
+ -Type wells 44 'and p--type wells 15''are ion-implanted into n-type source regions 19S-1 to 19S-, respectively.
3. The n-type drain regions 19D-1 to 19D-3 are formed.

Next, as shown in FIGS. 41A to 41C, an interlayer insulating film 20 made of, for example, a CVD oxide film is formed on the structure shown in FIGS. 53A to 53C. . Next, the p-type source / drain regions 18S and 18D and the n-type source / drain regions 19S-1
To 19S-3 and 19D-1 to 19D-3 are formed. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 22.

With the above-described manufacturing method, a semiconductor integrated circuit device according to the sixth embodiment of the present invention is completed.

In the semiconductor integrated circuit device described above, as in the fifth embodiment, the first gate oxide film 3 is formed using a mask for forming the p − -type well 15 ″.
Remove one. That is, a mask for forming the p @-type well 15 "and a mask for obtaining the thin gate oxide film 36 can be used in common.

The p − -type well 15 ″ has a p-type impurity to the extent that the conductivity type of the n-type well 8 is not reversed, as in the fifth embodiment. This p-type well 15 ''
Are formed from the region of the substrate 1 where the p-type well 15 '' is formed, to the inside of the n-type well 8, and further to the p-type well 44. In the p-type well 44, p-
Since the p-type impurity 14 forming the mold well 15 ″ is additionally introduced, the impurity concentration increases, and p +
It is converted to a mold well 44 '. As a result, p
A -type well 15 "and ap + -type well 44 'having a higher impurity concentration than the p- -type well 15" are formed.

The opening 3 formed in the photoresist film 34 for forming the p − -type well 15 ″ in this manner.
5 '' can also be opened above the n-type well 8 and the p-type well 44. Therefore, without increasing the number of masks, the thin gate oxide film 36 is formed in the n-type well 8, the p + well 44 'having a high impurity concentration, and the p-
Can be formed on both.

Therefore, according to the sixth embodiment, in a semiconductor integrated circuit device having gate oxide films having different thicknesses, the number of masks can be reduced as in the first to fifth embodiments. The effect that cost can be reduced can be obtained.

In the fifth embodiment, p
-Photoresist film 3 for forming mold well 15 ''
4 was also opened on the n-type well 8,
The opening 35 '' may be formed only on the region for forming the p-type well 15 '' and only on the region for forming the high concentration p + well 44 '.

The STI type element isolation region 54 described in the sixth embodiment can be applied to the first to fourth embodiments.

[Seventh Embodiment] The seventh embodiment has a different gate oxide film as in the third to sixth embodiments, and has the same structure as the first and second embodiments. 1 is an example of a semiconductor integrated circuit device having a well separated by pn from 1; Note that STI (ShallowTrenc)
h Isolation).

FIG. 55 is a view showing a semiconductor integrated circuit device according to the seventh embodiment. FIG. 55 (A) is a plan view, FIG. 55 (B) is a sectional view taken along the line BB in FIG. (C) The figure is (A)
It is sectional drawing which follows the CC line | wire in a figure. FIG. 56 is a profile diagram showing the distribution of impurities in the substrate.
(A) is a profile along the line 56A-56A in FIG. 55 (B), (B) is a profile along the line 56B-56B in FIG. 55 (B), and (C) is FIG. 55 (B). 56C-56 in
FIG. 55 (B) shows a profile along the line C, and FIG.
Profile along the line 56D-56D, FIG.
(B) shows the profile along the line 56E-56E.

Hereinafter, a semiconductor integrated circuit device according to the seventh embodiment will be described along with a method of manufacturing the same.

FIGS. 57 to 68 are views showing the semiconductor integrated circuit device according to the seventh embodiment for each of the main manufacturing steps. 57A to FIG. 68, (A) is a plan view, (B) is a cross-sectional view taken along the line BB in FIG.
FIG. 3C is a cross-sectional view taken along line CC in FIG.

First, as shown in FIGS. 57A to 57C, the surface of p-type silicon substrate 1 is thermally oxidized, for example, to form first gate oxide film 31 on the surface of substrate 1. Next, a photoresist is applied on the first gate oxide film 31 to form a photoresist film 5. Next, the opening 6 is formed in the photoresist film 5 by photolithography.
a and 6b are formed. In this embodiment, the opening 6a is formed corresponding to the region where the n-type well is formed, and the opening 6b is formed so as to surround the region where the p @-well separated from the substrate 1 is formed. Is done. Then
Using the photoresist film 5 as a mask, an n-type impurity 7 is ion-implanted into the substrate 1. Thereby, the n-type well 8-
1 and an n-type impurity 7 for forming an n-type well 8-2 surrounding a region where a p-type well separated from the substrate 1 is formed are introduced into the substrate 1. FIG. 69 (A)-
(E) for forming n-type wells 8-1 and 8-2
4 shows an impurity profile after the mold impurity 7 has been introduced into the substrate 1. (A) is a profile along the line 69A-69A in FIG. 57 (B), and (B) is a profile along 69B in FIG. 57 (B).
Profile along -69B line, (C) figure is FIG. 57 (B)
The profile along the 69C-69C line in FIG. 5 (D) is FIG.
Profile along line 69D-69D in 7 (B), (E)
The figure is a profile along the line 69E-69E in FIG. As shown in FIGS. 69 (A) to (E), the n-type impurity 7 for forming the n-type wells 8-1 and 8-2 is higher than the concentration of the p-type impurity originally contained in the substrate 1. Is introduced into the substrate 1 so as to be higher.

Next, as shown in FIGS. 58A to 58C, after removing the photoresist film 5 from the substrate 1, a photoresist is applied again to form a photoresist film 41. Next, an opening 42 is formed in the photoresist film 41 using a photolithography method. In this embodiment, the opening 42 is formed of a high-concentration p connected to the substrate 1.
+ Formed corresponding to the region where the well is formed. Next, the p-type impurity 43 is ion-implanted into the substrate 1 using the photoresist film 41 as a mask. As a result, a low-concentration p-type well 44 is first formed. The region where the high concentration p @ + -type well is formed is
The reason for forming the -type well 44 first is that, in this embodiment, two p + -type wells having a high concentration
This is because it is formed by ion implantation twice. FIG.
(F) to (J) show the impurity profiles after the formation of the low-concentration p − -type well 44. (F) FIG.
58B is a profile along the line 69F-69F, FIG. 58G is a profile along the line 69G-69G in FIG.
(H) is a profile along the line 69H-69H in FIG. 58 (B), (I) is a profile along the line 69I-69I in FIG. 58 (B), and (J) is FIG. 58 (B). 69J-69 inside
This is a profile along the J line. FIGS. 69 (F) to (J)
As shown in (1), the p − -type well 44 is formed in the substrate 1 by introducing the p-type impurity 43 into the substrate 1.
Since the p − -type well 44 is originally formed by adding a p-type impurity to the p-type substrate 1, the concentration of the p-type impurity is higher than that of the substrate 1.

Next, as shown in FIGS. 59A to 59C, after removing the photoresist film 41 from above the substrate 1,
A photoresist is applied again to form a photoresist film 34. Next, the openings 35-1, 35-2, and 35-3 are formed in the photoresist film 34 by using a photolithography method.
To form In this embodiment, the opening 35-1
Is a hole 35- in the region where the n-type well 8-1 is formed.
Reference numeral 2 denotes an opening 35 in the region where the p--type well 44 is formed.
-3 are formed corresponding to the regions where the p @-wells which are pn separated from the substrate 1 are formed. Next, the n-type impurity 11 is ion-implanted into the substrate 1 using the photoresist film 34 as a mask. FIGS. 70A to 70E show impurity profiles after n-type impurity 11 is introduced into substrate 1. (A) is a profile along the line 70A-70A in FIG. 59 (B), and (B) is a profile along 70B-70A in FIG. 59 (B).
A profile along line 70B, FIG. 59 (C) is a profile along line 70C-70C in FIG. 59 (B), and FIG.
59B is a profile along the line 70D-70D, and FIG. 59E is a profile along the line 70E-70E in FIG. As shown in FIGS. 70A to 70E, the n-type impurity 11 is introduced so as to be higher than the concentration of the p-type impurity originally contained in the substrate 1, and the n-type impurity 11 is
Form a mold well 12-2. As a result, a region 13 is obtained in the substrate 1 from the substrate 1 which is pn separated from the substrate 1 by the n-type well 8-2 and the buried n-type well 12-2. In this embodiment, the n-type impurity 11 is p
-Is introduced at a concentration lower than the concentration of the p-type impurity contained in the mold well 44; For this reason, the buried well 12-3 formed in the p − -type well 44 exhibits p-type conductivity. Further, the n-type impurity 11 is formed in the n-type wells 8-1, 8-2.
In this case, an n-type impurity is added. Therefore, the buried well 12-1 formed in the n-type well 8-1 is a region having a higher n-type impurity concentration.

Next, as shown in FIGS. 60A to 60C, the p-type impurity 14 is ion-implanted into the substrate 1 using the photoresist film 34 as a mask without removing the photoresist film 34. I do. 70 (F) to 70 (J) show impurity profiles after p-type impurity 14 is introduced into substrate 1. (F) is a profile along the line 70F-70F in FIG. 60 (B), and (G) is a profile along the line 70G-70 in FIG. 60 (B).
The profile along the line 70G, (H) is a profile along the line 70H-70H in FIG. 60 (B), and (I) is a diagram in FIG.
The profile along the line 70I-70I in (B) and the profile along the line 70J-70J in FIG. 60 (B) are shown in FIG. As shown in FIGS. 70 (F) to (J), the p-type impurity 14 is introduced so as to have a lower concentration than the n-type impurity contained in the n-type wells 8-1 and 8-2. Thereby, the well 15-1 formed in the n-type well 8-1 is formed.
Represents n-type conductivity. The portion of the n-type well 8-1 where the well 15-1 is formed functions as a well 8'-1 in which the effective concentration of the n-type impurity is reduced. Also,
The well 15-3 formed in the p-type well 44 is
A p-type impurity is additionally introduced into the mold well 44. Therefore, the portion of the p- type well 44 where the well 15-3 is formed becomes the high concentration p + type well 44 '. The well 15-2 formed in the p-type substrate 1 additionally introduces p-type impurities into the substrate 1. Therefore, a p-type well 15-2 is formed in the region 13.

Next, as shown in FIGS. 61 (A) to 61 (C), the photoresist film 34 is not removed from above the substrate 1 and the opening 35-1 is continuously formed using the photoresist film 34 as a mask. The first gate oxide film 31 exposed from .about.35-3 is removed. Thereby, the opening portions 35-1 to 35-35
3, the surface of the substrate 1, in this embodiment, the well 1
5-1 (n-type well 8'-1), p-type well 15-
2. The wells 15-3 (p + wells 44 ') are exposed.

Next, as shown in FIGS. 62A to 62C, the photoresist film 34 is removed from the substrate 1.

Next, as shown in FIGS. 63A to 63C, the surface of the substrate 1 is thermally oxidized, for example, to form a second gate oxide film 36. In this embodiment, the second gate oxide film 36 includes a well 15-1 (n-type well 8'-1),
They are formed on the surfaces of the p- well 15-2 and the well 15-3 (p + well 44 '). At this time, additional thermal oxidation is performed on the first gate oxide film 31 to increase its thickness. As a result, a thick gate oxide film 31 is obtained on the substrate 1. In addition, well 15-1
A thin gate oxide film 36 is obtained on the (n-type well 8'-1), the p- well 15-2 and the well 15-3 (p + well 44 ').

Next, as shown in FIGS. 64 (A) to 64 (C), conductive polysilicon and, for example, silicon nitride are sequentially deposited on the structure shown in FIGS. 63 (A) to 63 (C). Then, a conductive polysilicon film 51 and a silicon nitride film 52 are formed.

Next, as shown in FIGS. 65 (A) to 65 (C), for example, the silicon nitride film 52 is patterned in a shape corresponding to the formation pattern of the element region 3. Next, using the patterned silicon nitride film 52 as a mask, the conductive polysilicon film 51 and the substrate 1 are sequentially etched to form grooves 5 corresponding to the formation pattern of the element isolation region.
Form 3 As a result, an island-shaped element region 3 protruding in the substrate 1 is obtained.

Next, as shown in FIGS. 66A to 66C, an insulating film to be an element isolation region, for example, silicon dioxide is deposited on the structure shown in FIGS. 65A to 65C. And
A silicon dioxide film is formed. Next, an etch back method using the silicon dioxide film as a stopper for etching with the silicon nitride film 52 or a CMP (Chemical Mechanical) method.
Then, the silicon dioxide film is buried in the trench 53 by the receding method using the cal polishing method. As a result, an STI type element isolation region 54 is formed.

In this embodiment, the side wall (51SIDE) of the conductive polysilicon film 51 is exposed, but this may or may not be exposed.

Next, as shown in FIGS. 67A to 67C, a conductive film serving as a gate electrode of a transistor, for example, a conductive film is formed on the structure shown in FIGS. 66A to 66C. A polysilicon film 55 is formed. The conductive polysilicon film 55 is electrically connected to the conductive polysilicon film 51, and forms a laminated film with the conductive polysilicon film 51.

Next, as shown in FIGS. 68 (A) to (C), the laminated film composed of the conductive polysilicon films 51 and 55 is patterned to form the gate electrode 17. Next, a p-type impurity for forming a p-type source / drain is ion-implanted into the n-type well 8 according to a well-known method to form a p-type source region 18S and a p-type drain region 18D. Then, according to a known method, an n-type impurity for forming an n-type source / drain is
+ -Type wells 44 'and p--type wells 15''are ion-implanted into n-type source regions 19S-1 to 19S-, respectively.
3. The n-type drain regions 19D-1 to 19D-3 are formed.

Next, as shown in FIGS. 55 (A)-(C), an interlayer insulating film 20 made of, for example, a CVD oxide film is formed on the structure shown in FIGS. 68 (A)-(C). . Next, the p-type source / drain regions 18S and 18D and the n-type source / drain regions 19S-1
To 19S-3 and 19D-1 to 19D-3 are formed. Next, a conductive film to be a wiring, for example, an aluminum film is formed, and the formed aluminum film is patterned to form a wiring 22.

By the manufacturing method described above, the semiconductor integrated circuit device according to the seventh embodiment of the present invention is completed.

The semiconductor integrated circuit device as described above has buried wells 12-1 to 12-3 below the wells 15-1 to 15-3. The buried wells 12-1 to 12-3 correspond to wells 15-1 to 1
It can be formed using the same mask as in 5-3. Further, the first gate oxide film 31 is removed using a mask for forming the wells 15-1 to 15-3.

As described above, according to the seventh embodiment, a mask for forming buried type wells 12-1 to 12-3, a mask for forming wells 15-1 to 15-3, and A mask for obtaining a thin gate oxide film 36 can be shared.

Therefore, according to the seventh embodiment, the number of masks can be reduced in a semiconductor integrated circuit device having a different gate oxide film and having ap − type well 15-3 pn-separated from the substrate 1. Thus, the effect that the manufacturing cost can be reduced can be obtained.

In the seventh embodiment, the opening 35-1 of the photoresist film 34 is formed in the n-type well 8-1.
The opening 35-1 is opened only on the region where the p − -type well 15-3 is formed and on the region where the high-concentration p + -type well 44 ′ is formed. You may do it.

The p − well 44 need not be formed if it is not necessary.

Further, the STI type element isolation region 54 described in the seventh embodiment may be replaced with the LOCOS type element isolation region 2 as in the first to fifth embodiments.

[Eighth Embodiment] The eighth embodiment is an example of a transistor formed in a p-type well 15-2 which is pn separated from the substrate 1.

FIG. 71 is a sectional view of a semiconductor integrated circuit device according to the eighth embodiment of the present invention.

As shown in FIG. 71, the p-type well 15-
2 is a nonvolatile memory cell transistor MT used for an EEPROM or the like. This nonvolatile memory cell transistor MT has a floating gate FG for storing electrons. The threshold voltage of the nonvolatile memory cell transistor MT changes depending on the amount of electrons stored in the floating gate FG. The nonvolatile memory cell transistor MT has a control gate C
When a predetermined read voltage is applied to G, binary or more data can be stored depending on whether it is turned on or off.

When erasing data, control gate CG
And a back gate thereof, that is, the p − -type well 15-2, so that the p − -type well 15-2 side has a positive potential, thereby giving a large potential difference. As a result, electrons are extracted from the floating gate FG to the p − -type well 15-2.
At this time, since a very high potential is applied to the p − -type well 15-2, it is better that the p − -type well 15-2 is separated from the substrate 1. This is because the potential of the p − -type well 15-2 can be selectively made higher than that of the substrate 1.

As described above, p which is pn separated from the substrate 1
-As a transistor formed in the mold well 15-2,
For example, it is preferable that the back gate be operated at a potential different from the potential of the substrate 1 (generally, the circuit ground potential VSS), such as a nonvolatile memory cell transistor MT.

FIG. 71 shows a unit (NAND cell) in which a nonvolatile memory cell transistor MT connected in series is sandwiched between select gate transistors ST1 and ST2.
N connected in series between the source line SL and the bit line BL
Although an AND type EEPROM is illustrated, it is needless to say that the present invention can be applied to EEPROMs other than the NAND type.

In the p − -type well 15-2, in addition to a nonvolatile memory cell transistor, a transistor that operates with a potential of the back gate different from the potential of the substrate 1 may be formed.

The present invention has been described with reference to the first to eighth embodiments. However, the present invention is not limited to these embodiments, and it is needless to say that various modifications can be made without departing from the gist of the present invention. .

Further, the first to eighth embodiments respectively
It can also be implemented in combination.

[0209]

As described above, according to the present invention, a well having a conductivity type different from that of a substrate, a well connected to the substrate having the same conductivity type as that of the substrate, and a well having the same conductivity type as that of the substrate. In a semiconductor integrated circuit device having wells to be pn-separated, a semiconductor capable of suppressing an increase in a photolithography step and reducing a manufacturing cost while maintaining an advantage that an impurity concentration of a well of the same conductivity type as a substrate can be freely set. An integrated circuit device and a method for manufacturing the same can be provided.

Further, in a semiconductor integrated circuit device having a plurality of types of gate insulating films having different film thicknesses, a semiconductor integrated circuit device capable of suppressing an increase in photolithography steps and reducing a manufacturing cost and a manufacturing method thereof can be provided.

Further, a well of a conductivity type different from that of the substrate,
In a semiconductor integrated circuit device having a well connected to the substrate with the same conductivity type as the substrate, a well having the same conductivity type as the substrate and pn-separated from the substrate, and a plurality of types of gate insulating films having different film thicknesses, It is possible to provide a semiconductor integrated circuit device capable of suppressing an increase in photolithography steps and reducing a manufacturing cost while maintaining an advantage that an impurity concentration of a well of the same conductivity type as a substrate can be freely set, and a manufacturing method thereof.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIGS.
(D) is a sectional view.

FIG. 2A to FIG. 2E are profile diagrams each showing the distribution of impurities.

FIG. 3A is a plan view showing one manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 3B to 3D are cross-sectional views.

FIG. 4A is a plan view showing one manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 4B to 4D are cross-sectional views.

FIG. 5A is a plan view showing a manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views.

FIG. 6A is a plan view showing one manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views.

FIG. 7A is a plan view showing one manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views.

FIG. 8A is a plan view showing one manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views.

FIG. 9A is a plan view showing one manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views.

FIG. 10A is a plan view showing one manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views.

FIGS. 11A to 11J are profile diagrams each showing the distribution of impurities.

FIGS. 12A to 12J are profile diagrams showing the distribution of impurities, respectively.

FIG. 13A is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views.

FIGS. 14A to 14E are profile diagrams showing the distribution of impurities, respectively.

FIG. 15A is a plan view showing one manufacturing step of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views.

FIG. 16A is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention in one manufacturing step, and FIGS. 16B to 16D are cross-sectional views.

FIG. 17A is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention in one manufacturing step, and FIGS. 17B to 17D are cross-sectional views.

FIG. 18A is a plan view in a manufacturing step of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views, respectively.

FIG. 19A is a plan view showing one manufacturing step of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views.

FIG. 20A is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention in one manufacturing step, and FIGS. 20B to 20D are cross-sectional views, respectively.

FIG. 21A is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention in one manufacturing step, and FIGS. 21B to 21D are cross-sectional views.

FIG. 22A is a plan view showing a manufacturing step of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views.

FIGS. 23A to 23J are profile diagrams each showing the distribution of impurities.

FIG. 24A to FIG. 24J are profile diagrams each showing the distribution of impurities.

FIG. 25 is a sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIGS. 26A to 26C are cross-sectional views illustrating a manufacturing process of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIGS. 27A to 27D are cross-sectional views in a manufacturing process of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 28 is a sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

29 (A) to 29 (C) are profile diagrams each showing the distribution of impurities.

FIGS. 30A to 30C are cross-sectional views illustrating a manufacturing process of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIGS. 31A to 31D are cross-sectional views illustrating a manufacturing process of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

32 (A) to 32 (I) are profile diagrams each showing a distribution of impurities.

FIG. 33 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

34 (A) to 34 (D) are profile diagrams each showing the distribution of impurities.

FIGS. 35A and 35B are cross-sectional views of a semiconductor integrated circuit device according to a fifth embodiment of the present invention in one manufacturing step.

FIGS. 36A and 36B are cross-sectional views of a semiconductor integrated circuit device according to a fifth embodiment of the present invention in one manufacturing step.

FIGS. 37A and 37B are cross-sectional views of a semiconductor integrated circuit device according to a fifth embodiment of the present invention in one manufacturing step.

38 (A) and 38 (B) are cross-sectional views of a semiconductor integrated circuit device according to a fifth embodiment of the present invention in one manufacturing step.

FIGS. 39A to 39H are profile diagrams each showing the distribution of impurities.

FIGS. 40A to 40H are profile diagrams each showing the distribution of impurities.

FIG. 41 (A) is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention, and FIGS. 41 (B) and 41 (C) are cross-sectional views.

FIGS. 42A to 42D are profile diagrams each showing the distribution of impurities.

FIG. 43 (A) is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention in one manufacturing step, and FIGS. 43 (B) and 43 (C) are cross-sectional views.

FIG. 44A is a plan view of one manufacturing step of a semiconductor integrated circuit device according to a sixth embodiment of the present invention, and FIGS. 44B and 44C are cross-sectional views, respectively.

FIG. 45A is a plan view of one manufacturing step of a semiconductor integrated circuit device according to a sixth embodiment of the present invention, and FIGS. 45B and 45C are cross-sectional views, respectively.

FIG. 46A is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention in one manufacturing step, and FIGS. 46B and 46C are cross-sectional views, respectively.

FIG. 47 (A) is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention in one manufacturing step, and FIGS. 47 (B) and 47 (C) are cross-sectional views.

FIG. 48A is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention in one manufacturing step, and FIGS. 48B and 48C are cross-sectional views, respectively.

FIG. 49 (A) is a plan view showing a manufacturing step of a semiconductor integrated circuit device according to a sixth embodiment of the present invention, and FIGS. 49 (B) and 49 (C) are cross-sectional views.

FIG. 50 (A) is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention in one manufacturing step, and FIGS. 50 (B) and 50 (C) are cross-sectional views.

FIG. 51A is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention in one manufacturing step, and FIGS. 51B and 51C are cross-sectional views, respectively.

FIG. 52A is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention in one manufacturing step, and FIGS. 52B and 52C are cross-sectional views, respectively.

FIG. 53A is a plan view showing one manufacturing step of a semiconductor integrated circuit device according to a sixth embodiment of the present invention, and FIGS. 53B and 53C are cross-sectional views, respectively.

FIGS. 54 (A) to (L) are profile diagrams each showing the distribution of impurities.

FIG. 55A is a plan view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 55B and 55C are cross-sectional views, respectively.

FIGS. 56A to 56E are profile diagrams each showing the distribution of impurities.

FIG. 57 (A) is a plan view of one manufacturing step of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 57 (B) and 57 (C) are cross-sectional views.

FIG. 58 (A) is a plan view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention in one manufacturing step, and FIGS. 58 (B) and 58 (C) are cross-sectional views.

FIG. 59 (A) is a plan view showing a manufacturing step of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 59 (B) and 59 (C) are cross-sectional views.

FIG. 60A is a plan view showing one manufacturing step of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 60B and 60C are cross-sectional views, respectively.

FIG. 61 (A) is a plan view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention in one manufacturing step, and FIGS. 61 (B) and 61 (C) are cross-sectional views.

FIG. 62A is a plan view of one manufacturing step of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 62B and 62C are cross-sectional views, respectively.

63 (A) is a plan view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention in one manufacturing step, and FIGS. 63 (B) and 62 (C) are cross-sectional views.

FIG. 64A is a plan view of one manufacturing step of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 64B and 64C are cross-sectional views, respectively.

FIG. 65A is a plan view of one manufacturing step of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 65B and 65C are cross-sectional views, respectively.

FIG. 66 (A) is a plan view of one manufacturing step of the semiconductor integrated circuit device according to the seventh embodiment of the present invention, and FIGS. 66 (B) and 66 (C) are cross-sectional views.

FIG. 67 (A) is a plan view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention in one manufacturing step, and FIGS. 67 (B) and 67 (C) are cross-sectional views.

FIG. 68A is a plan view of one manufacturing step of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIGS. 68B and 68C are cross-sectional views, respectively.

FIGS. 69A to 69J are profile diagrams each showing the distribution of impurities.

FIGS. 70A to 70J are profile diagrams each showing the distribution of impurities.

FIG. 71 is a sectional view of a semiconductor integrated circuit device according to an eighth embodiment of the present invention;

FIG. 72 is a sectional view of a conventional semiconductor integrated circuit device.

73 (A) to 73 (E) are profile diagrams each showing the distribution of impurities.

FIGS. 74 (A) to 74 (C) are cross-sectional views showing main manufacturing steps of a conventional semiconductor integrated circuit device, respectively.

75 (A) to 75 (C) are cross-sectional views showing main manufacturing steps of a conventional semiconductor integrated circuit device, respectively.

76 (A) and 76 (B) are cross-sectional views showing main manufacturing steps of a conventional semiconductor integrated circuit device, respectively.

FIGS. 77 (A) to 77 (J) are profile diagrams each showing the distribution of impurities.

FIGS. 78A to 78J are profile diagrams each showing the distribution of impurities.

FIG. 79 is a sectional view of another conventional semiconductor integrated circuit device.

FIGS. 80A to 80D are profile diagrams each showing the distribution of impurities.

FIGS. 81 (A) to 81 (C) are cross-sectional views showing main manufacturing steps of another conventional semiconductor integrated circuit device.

82 (A) and 82 (B) are cross-sectional views showing main manufacturing steps of another conventional semiconductor integrated circuit device, respectively.

83 (A) and 83 (B) are cross-sectional views showing main manufacturing steps of another conventional semiconductor integrated circuit device, respectively.

84 (A) to 84 (L) are profile diagrams each showing the distribution of impurities.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate, 2 ... element isolation area (LOCOS), 3 ... element area, 4 ... buffer oxide film, 5 ... photoresist film, 6a, 6b ... opening part, 7 ... n-type impurity, 8, 8- 1, 8-2: n-type well, 8 ', 8-1: n-type well with low effective impurity concentration, 9: photoresist film, 10a, 10b: opening, 11 ... n-type impurity, 12-1 ... 12-3: Well containing embedded n-type impurity; 13 ... P-type region pn separated from substrate; 14 ... P-type impurity; 15, 15 ', 15 ", 15-1 to 15-3 ... well containing p-type impurities, 16 gate oxide film, 17 gate electrode, 18S p-type source region, 18D p-type drain region, 19S, 19S-1, 19S-2, 19S-3 ... n-type source region , 19D, 19D-1, 19D-2, 19D-3 ... n-type drain region, 20 ... interlayer insulating film, 21 ... contact hole, 22 ... wiring, 31 ... first gate oxide film (thick gate oxide film), 32 ... photoresist film, 33 ... opening, 34 ... photoresist Film, 35, 35 ', 35'', 35-1 to 35-3 ... opening, 36 ... second gate oxide film (thin gate oxide film), 41 ... photoresist film, 42 ... opening, 43 ... p-type impurity, 44 ... p- type well, 44 '... p + type well, 51 ... conductive polysilicon film, 52 ... silicon nitride film, 53 ... groove, 54 ... element isolation region (STI), 55 ... Conductive polysilicon film.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Seiichi Aridome 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama Office 5F040 DB03 DC01 EC07 EC13 ED06 EE05 EF11 EK01 FA05 FC11 FC21 5F048 AA09 AB01 AC03 BA01 BB05 BB08 BB16 BD04 BE02 BE03 BE05 BE10 BG12 BH02

Claims (7)

[Claims] A first conductive type semiconductor substrate formed on the first conductive type semiconductor substrate;
A first semiconductor region containing an impurity of the second conductivity type, a second annular semiconductor region containing an impurity of the second conductivity type formed on the semiconductor substrate, and an annular second semiconductor region. A buried third semiconductor region containing impurities of the second conductivity type formed in the recessed region; and a fourth semiconductor region of buried type containing impurities of the second conductivity type formed on the semiconductor substrate. A fifth semiconductor region formed above the third semiconductor region and containing a first conductivity type impurity, and a first conductivity type impurity formed above the fourth semiconductor region. A semiconductor integrated circuit device, comprising: a sixth semiconductor region including: a transistor formed in the first, fifth, and sixth semiconductor regions. 2. Using a first mask, a first semiconductor region of a second conductivity type and an annular second semiconductor region of a second conductivity type are formed on a semiconductor substrate of the first conductivity type. Second for
A step of introducing an impurity of a conductivity type; and a third and third buried type of the second conductivity type in a region surrounded by the semiconductor substrate and the annular second semiconductor region using a second mask. Introducing a second conductivity type impurity for forming the fourth semiconductor region; and using the second mask to cover the third and fourth semiconductor regions with the fifth of the first conductivity type. Introducing a first conductivity type impurity for forming a sixth semiconductor region; and forming a transistor in the first, fifth, and sixth semiconductor regions. Of manufacturing a semiconductor integrated circuit device. 3. A step of forming a first gate insulating film on a semiconductor substrate, and introducing a first impurity for forming a first semiconductor region into the semiconductor substrate by using a first mask. A step of introducing a second impurity for forming a second semiconductor region into the semiconductor substrate using a second mask; and a step of using the second mask to form the first gate. Removing an insulating film; forming a second gate insulating film in a portion where the first gate insulating film has been removed; and forming a first gate in a portion where the first gate insulating film remains. A semiconductor integrated circuit device, comprising: a step of increasing a thickness of an insulating film; and a step of forming a transistor using the first gate insulating film and a transistor using the second gate insulating film. Manufacturing method. 4. A step of forming a first gate insulating film on a semiconductor substrate, and using a first mask to introduce a first impurity for forming a first semiconductor region into the semiconductor substrate. Using a second mask to introduce a second impurity for forming a second semiconductor region into the semiconductor substrate and the region into which the first impurity has been introduced; Removing the first gate insulating film using a second mask; forming a second gate insulating film in a portion where the first gate insulating film has been removed; Increasing the thickness of the first gate insulating film in a portion where the film remains, and forming a transistor using the first gate insulating film and a transistor using the second gate insulating film. Characterized by having Method for producing a body integrated circuit device. 5. A step of forming a first gate insulating film on a semiconductor substrate, and using a first mask to introduce a first impurity for forming a first semiconductor region into the semiconductor substrate. A step of introducing a second impurity for forming a second semiconductor region into the semiconductor substrate using a second mask; and a step of introducing a second impurity to the semiconductor substrate using a third mask. Introducing a third impurity for forming a third semiconductor region into the region into which the first impurity is introduced and into the region into which the second impurity is introduced; and using the third mask Removing the first gate insulating film; forming a second gate insulating film in a portion where the first gate insulating film has been removed, and a portion where the first gate insulating film remains A step of increasing the thickness of the first gate insulating film; Forming a transistor using the first gate insulating film and a transistor using the second gate insulating film. 6. A step of forming a first gate insulating film on a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type on the semiconductor substrate using a first mask; A step of introducing a second impurity of a second conductivity type for forming a second semiconductor region of a second conductivity type, and a step of introducing a second impurity using a second mask. A second conductivity type for forming third, fourth, and fifth semiconductor regions of a second conductivity type and buried in a region surrounded by the semiconductor region and a region into which the first impurity is introduced. Introducing a second impurity, and using the second mask to cover the third, fourth, and fifth semiconductor regions above the sixth, seventh, and eighth first conductivity types. A step of introducing a third impurity of a first conductivity type for forming a semiconductor region, and using the second mask Removing the first gate insulating film; forming a second gate insulating film in a portion where the first gate insulating film has been removed; and forming a second gate insulating film in a portion where the first gate insulating film remains. Increasing the thickness of the first gate insulating film; and forming a transistor using the first gate insulating film and a transistor using the second gate insulating film. Of manufacturing a semiconductor integrated circuit device. 7. A first gate insulating film formed on a semiconductor substrate of a first conductivity type, a first semiconductor region containing impurities of a second conductivity type formed on the semiconductor substrate, and the semiconductor substrate An annular second semiconductor region including the second conductivity type impurity formed in the semiconductor substrate; and a buried third semiconductor region including the second conductivity type impurity formed in the semiconductor substrate. A buried type fourth semiconductor region containing the second conductivity type impurity formed in a region surrounded by the annular second semiconductor region; and a buried type fourth semiconductor region formed in the first semiconductor region. A buried-type fifth semiconductor region containing two-conductivity-type impurities; a sixth semiconductor region containing first-conductivity-type impurities formed above the third semiconductor region; and the fourth semiconductor The first conductivity type formed above a region; A seventh semiconductor region containing an impurity, an eighth semiconductor region formed above the fifth semiconductor region and containing the impurity of the first conductivity type, and the sixth, seventh, and eighth semiconductors. A second gate insulating film thinner than the first gate insulating film formed in the region; a transistor using the first gate insulating film; and a transistor using the second gate insulating film A semiconductor integrated circuit device.