JP2000021187A - Semiconductor memory apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save a power without lowering a speed at the time of switching memories by extending an operation clock for a predetermined period when a non-operation state is selected while a steady-state current shutoff means for shutting off a steady-state current is operating. SOLUTION: A wait control circuit 3 generates a wait clock WC to substantially delay a clock CK for a predetermined time in response to a change of a most significant address CS, that is, to keep the clock CK wait in a wait state for a period corresponding to an operation preparation to a selected memory block, and supplies the wait clock to a CPU 4. The wait control clock signal WC extends the clock by an amount of four clocks intentionally only during a precharge period of a data line. Seen from the CPU 4, therefore, the operation does not stop and no influence is given to a next operation at all. For instance, even if a memory block 2A changes from a non-selection state to a selection state, data of the memory block 2A can be read immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device mounted on a microcomputer and comprising a plurality of memory blocks.

[0002]

2. Description of the Related Art In recent years, the capacity of memories mounted on microcomputers has been increasing year by year. However, in a high-speed microcomputer, if the capacity of the memory to be mounted is increased, the additional capacity of the word line and the data line is increased and the data read speed is reduced. Therefore, the memory is divided into a plurality of memory blocks and the read speed is reduced. I have taken the method of securing.

However, the number of sense amplifiers and reference voltage generating circuits is proportional to the number of divided memories, that is, the number of memory blocks. In addition, as the number of memory blocks increases, the number of non-operating memory blocks increases. On the other hand, in the memory block, the sense amplifier and the reference voltage generation circuit of the memory block consume current regardless of operation / non-operation. Therefore, if there is a non-operational memory block, the consumption of the sense amplifier and the reference voltage generation circuit of these memories is caused. The current cannot be ignored. For example, when the number of memory blocks is eight, that is, when eight sense amplifiers are mounted, about 400 μA of current is wasted.

For example, referring to FIG. 8 which shows a block diagram of a general semiconductor memory device of this type described in Japanese Patent Application Laid-Open No. 6-052680, this conventional semiconductor memory device has an address AD transmitting address AD. Bus AB,
Two memory blocks 1 and 2 for outputting read data SO1 and SO2 in response to access from address bus AB, and the most significant bit of the address (most significant address)
An inverter I1 that inverts CS and outputs an inverted highest address CSB, and buffers read data SO1 and SO2 in response to the supply of the highest address CS and the inverted highest address CSB of the address, respectively. It has buffers BF1 and BF2 for outputting to the DB and a data bus DB.

The memory blocks 1 and 2 have the same configuration.
Referring to FIG. 9 which shows the configuration of the memory block 1 as a block as a representative, the memory block 1 has an address A
A decoder 11 for decoding D and outputting word selection data W to a word line; a memory cell 12 for reading data in a memory cell in response to supply of word selection data W and outputting bit data B to a data line; A sense amplifier group 13 including sense amplifiers SA1 to SA7 receiving supply of reference voltage RF, precharge signal FC and read signal RD, and outputting read data SO of each memory cell in response to supply of bit data B; A reference voltage generating circuit for outputting a reference voltage in response to activation of RD.

The read signal RD is a signal that is always activated when the semiconductor memory device is in a read state, and is deactivated when the semiconductor memory device is not in a read state.

Next, the operation of the conventional semiconductor memory device will be described with reference to FIGS. 7 and 8. This conventional semiconductor memory device has a plurality of memory blocks, here,
For convenience of explanation, two memory blocks, memory blocks 1 and 2, are provided, and the output of one of these two memory blocks 1, 2 is selected by the most significant bit of the address designated by the CPU.

First, an address AD is transmitted via an address bus AB. For example, if this address AD selects the memory block 1, the highest address CS
Is '0', and in response to '0' of the highest address CS, the buffer BF2 is turned off and does not output the read data SO2 of the memory block 2. On the other hand, since the inverted uppermost address CSB becomes "1", the buffer BF1 becomes conductive in response to the inverted uppermost address CSB being "1", and outputs the read data SO1 of the memory block 1 to the data bus DB.

As described above, the selection of the memory blocks 1 and 2 only depends on the value of the highest address CS of the address AD, and the reference voltage generation circuit and the sense amplifier in these memory blocks 1 and 2 It operates irrespective of / selection and consumes current.

The reference voltage generating circuit 14 of the selected memory block 1 is activated in response to activation of the read signal RD corresponding to the read state, and outputs the reference voltage RF. The decoder 11 decodes the address AD, outputs predetermined word selection data W, and
Feed to 2. The memory cell 12 selects a memory cell corresponding to the word selection data W, outputs bit data B to a corresponding read data line, and supplies the bit data B to a corresponding sense amplifier (for convenience of description, SA1) of the sense amplifier group 13. . Here, assuming that the sense amplifier is a sense amplifier SA1 for convenience of explanation, this sense amplifier SA1
Becomes active in response to the activation of the read signal RD,
The operation is performed in response to the supply of the reference voltage RF and the precharge signal FC, and a change in the current of the data line due to the bit data B is detected to generate the read data SO1.

As described above, the reference voltage generating circuit 14 and the sense amplifier group 13 are activated in response to the activation of the read signal RD. Therefore, the conditions for stopping the reference voltage generating circuit 14 and the sense amplifier group 13 are set. Is the read signal R
This means that D is inactivated. However, if the read signal RD is deactivated and the memory blocks 1 and 2 are switched in order to reduce the operating current of the reference voltage generation circuit 14 and the sense amplifier group 13, it takes time to generate the reference voltage.
Extremely lower speed when switching memory blocks.

[0012]

In the above-mentioned conventional semiconductor memory device, in order to stop the reference voltage generating circuit and the sense amplifier group for the purpose of saving the operating current, when the read signal is inactivated and the memory block is switched, There is a disadvantage that it takes time to generate the reference voltage, and the speed is extremely reduced when switching between memory blocks.

An object of the present invention is to provide a semiconductor memory device capable of saving power without causing a reduction in speed at the time of memory switching.

[0014]

A semiconductor memory device according to the present invention has a current sense type sense amplifier which reads out stored data at a high speed by allowing a steady current to flow.
In a semiconductor memory device including (n is an integer of 2 or more) memory blocks, each of the n memory blocks sets one of the n memory blocks to an operation state and the other to a non-operation state. And a wait control means for extending the operation clock for a predetermined period during an operation period of the steady-state current interrupting means, comprising: a steady-state current interrupting means for interrupting the steady-state current when the non-operating state is selected by a selection signal to be selected. It is provided with.

[0015]

FIG. 8 shows an embodiment of the present invention.
Referring to FIG. 1 in which like components are denoted by common reference characters / numerals and similarly shown in blocks, the semiconductor memory device of this embodiment shown in FIG. , Address bus AB, inverter I1,
In addition to buffers BF1 and BF2, address bus AB
Memory blocks 1A and 2A instead of the two memory blocks 1 and 2 which output read data SO1 and SO2 in response to an access from the memory, and a clock CK in response to a change in the highest address CS. A wait control circuit 3 generates a wait clock WC by applying a wait delayed by a number of times and supplies the wait clock WC to the CPU 4, and a CPU 4 that operates in response to the supply of the wait clock WC.

The memory blocks 1A and 2A have the same configuration. As a representative, refer to FIG. 2 which similarly shows the configuration of the memory block 1A by adding common reference characters / numerals to components common to FIG. Then, this memory block 1
A is a decoder 11 that decodes an address AD common to the related art and outputs word selection data W to a word line, and reads data in a memory cell in response to the supply of the word selection data W, and outputs bit data B to a data line. And the sense amplifiers SA1 to SA7 receiving the supply of the reference voltage RF, the precharge signal FC and the read enable signal RDB, and outputting the read data SO of each of the memory cells in response to the supply of the bit data B. And a reference voltage generating circuit 14 for outputting a reference voltage RF in response to activation of read enable signal RDB
In addition to the above, a NAND circuit 15 which takes the NAND of the read signal RD and the most significant address CS and outputs the read enable signal RDB.

The sense amplifier SA1 of the sense amplifier group 13
To SA7 have the same configuration.
Referring to FIG. 3 which is a circuit diagram showing the details of the circuit No. 1, this sense amplifier SA1 performs a NOR operation on a precharge signal FC and a read enable signal RDB to output a signal RFC, and connects the source to a power supply VD. A P-channel transistor P23 connected to the power supply VD and receiving a signal RFC at its gate, a P-channel transistor P21 connected at its source to the power supply VD and supplied with a read enable signal RDB at its gate, and a gate connected to the drain of the transistor P21. A P-channel transistor P22 receiving a supply of an input signal S from a data line, an N-channel transistor N21 having a drain connected to the drain of the transistor P22 and a source connected to the ground, and receiving a supply of a read enable signal RDB to a gate; Of the transistor P22 An N-channel transistor N22 having a source connected to the ground and a gate receiving the input signal S at the gate; a P-channel transistor P24 having the source connected to the power supply VD and having a commonly connected gate and drain connected to the drain of the transistor P23; , With the drain connected to the drain of the transistor P22, the gate connected to the drain common connection point of the transistors P22, N21 and N22, and the source connected to the gate of the transistor N22, respectively.
A channel transistor N23, a P-channel transistor P25 having a source connected to the power supply VD and a gate connected to the gate of the transistor P24, an N-channel transistor N24 having a drain connected to the drain of the transistor P25 and receiving the reference voltage RF at the gate, Transistor N25 having a drain connected to the source of transistor N24, a gate connected to power supply VD, and a source connected to ground
An inverter I21 having an input terminal connected to a common drain connection point of the transistors P25 and N24, and an inverter I22 having an input terminal connected to the output terminal of the inverter I11 and outputting read data SO as an output signal from the output terminal. .

Referring to FIG. 3 which is a circuit diagram showing details of reference voltage generating circuit 14, reference voltage generating circuit 14 includes an inverter I41 for inverting read enable signal RDB and outputting an inverted read enable signal RBB, and a source I41. Is connected to a power supply VD and receives a signal RBB at a gate. A P-channel transistor P41 receives a read enable signal RDB at a gate whose source is connected to the power supply VD. A source is a drain of the transistor P41. A connected P-channel transistor P42, an N-channel transistor N41 having a drain connected to the drain of the transistor P42 and a source connected to the ground and receiving a supply of the read enable signal RDB to the gate, and a drain connected to the drain of the transistor P42 and the source grounded N-channel transistor N42 which are connected respectively to gate the gate of the transistor P41
A P-channel transistor P44 having a source connected to the power supply VD and having a commonly connected gate and drain connected to the drain of the transistor P43; a drain having a drain connected to the drain of the transistor P42;
An N-channel transistor N43 having a source connected to the gate of the transistor N42 at the common connection point of the drains N1 and N42, and a P-channel transistor having the source connected to the power supply VD and the gate connected to the gate of the transistor P44, and outputting the reference voltage RF from the drain. A transistor P45;
An N-channel transistor N44 having a drain connected to the drain of the transistor P45 and a gate supplied with the reference voltage RF; a transistor N45 having a drain connected to the source of the transistor N44, a gate connected to the power supply VD, and a source connected to the ground; A drain is connected to VDD, and a P-channel transistor P46 receiving a supply of the inverted read enable signal RBB is provided at a gate at a common connection point of the transistors P45 and N44.

FIG. 5 is a block diagram showing details of the weight control circuit 3. Referring to FIG.
The uppermost address sensing circuit 31 outputs a sensing signal CSS in response to the rising edge of the uppermost address CS, and starts a shift operation in response to the supply of the sensing signal CSS to output a fourth bit output signal OV3. 5 bit shift register 32, reset signal RES and shift register 3
A which takes a logical product with the inverted value of the output signal OV4 of the 5th bit of 2 and outputs the reset signal R of the shift register 32
An ND circuit A31, a selector 33 that selects one of the sensing signal CSS and the output signal OV3 of the shift register 32 in response to the supply of the clock CK, and outputs a selector signal CKS, and a selector 33 that responds to the rise of the selector signal CKS. A flip-flop F31 for taking in the value of the sensing signal CSS and outputting the signal EO, a flip-flop F32 for taking in the signal EO in response to the rising edge of the selector signal CKS and outputting the signal FO, and an inverting signal FOB by inverting the signal FO. Inverter I31 to output and clock CK
And an AND circuit A32 which takes the logical product of the signal FOB and outputs a wait clock WC.

The most significant address sensing circuit 31 senses the rising edge of the most significant address CS in response to the supply of the clock CK and outputs a signal C1 as a flip-flop F311.
And the highest address CS in response to the supply of the clock CK.
And a flip-flop F312 that senses the rising edge of the signal and outputs a signal C2, and an inverter I3 that inverts each of the signals C1 and CS and outputs each of the signals C1B and CSB.
11, I312 and a selector 311 for selecting one of the signal C1B and the signal C2 and outputting the sensing signal CSS.
And

Next, the operation of this embodiment will be described with reference to FIGS. 1, 2, 3, 4 and 5, as in the prior art. CPU having two memory blocks 1A and 2A
The output of one of these memory blocks 1A and 2A is selected by the most significant bit of the address specified by the address 4. Furthermore, the weight control circuit 3 characterizing the present embodiment
Generates a wait clock WC obtained by weighting the clock CK by a predetermined number of clocks in response to a change in the value of the most significant address CS, and supplies the wait clock WC to the CPU 4, which uses the wait clock WC as an operation clock.

The read enable signal RDB is generated by the NAND of the read signal RD common to the prior art and the highest address CS, and is "1" when inactive and "0" when activated.
Of each level. This read enable signal R
In response to the activation of DB, the sense amplifier SA and the reference voltage generation circuit 14 are activated.

The sense amplifier SA1 is a current sense type sense amplifier, and the level of the precharge signal FC is'
When it is “1”, it is a precharge period for charging the data line, and when it is “0”, it is a sampling period in which the sense amplifier detects the data line potential. The reference voltage RF is a reference voltage for sensing data line potential. Sense amplifier SA1
Indicates that the read enable signal RDB is inactivated ('1')
Deactivates in response to activation, and activates in response to activation ('0'). During activation, during the sampling period,
Detects a slight change in current of input signal S and outputs read data SO.

The reference voltage generation circuit 14 is deactivated in response to the deactivation ('1') of the read enable signal RDB, and outputs '1' as the reference voltage signal RF. In response to the activation ('0') of signal RDB, it is activated in response to the activation, and the transistor P45 is used as reference voltage signal RF.
N4 connected in series with the threshold voltage VtP of
4, a voltage determined by the ratio of the threshold voltage 2VtN of N45.

The selection of the memory blocks 1A and 2A
This is performed by the highest address signal CS supplied from U4. As described above, the wait control circuit 3 waits for the clock CK in response to the change of the most significant address CS so as to substantially delay the operation for a predetermined time, that is, wait for a period corresponding to the operation preparation of the selected memory block. A wait clock WC for applying a wait for setting a state is generated and supplied to the CPU 4. The most significant address signal CS changes from '0' to '
When the value changes from 1 to 1 or from 0 to 0, the wait control circuit 3 senses the change of the highest-order address signal CS, and, for the predetermined time, in this embodiment, four clocks of the clock CK. And a wait clock WC is generated and supplied to the CPU 4. The CPU 4 uses the wait clock WC as an operation clock, and maintains this state until the operation of the newly selected memory block is completed.

Next, the operation of the present embodiment will be described in detail with reference to FIG. 6 which shows a waveform of each part of the wait control circuit 3 in a time chart. First, when the memory block is in the read state, The read signal RD is activated, and in the non-read state, the read signal RD is inactivated.

Here, when the memory block 2A is in the read state, the decoder 11
Decodes address AD, outputs word selection data W, and activates a word line to select a corresponding memory cell MC. At this time, the highest-order address signal CS is “0”.
In this case, the NAND circuit 15 sets the read enable signal RDB to an inactive state, that is, '1', regardless of the value of the read signal RD, and sets the reference voltage generating circuit 14 to an inactive state. The reference voltage generation circuit 14 sets the reference voltage RF to '1' in response to the inactive state.
Further, the sense amplifier SA also has a read enable signal RD
B becomes inactive in response to "1", and the level of the read data SO as an output is always set to "1".

Next, when the highest address CS of the memory block 2A changes from "0" to "1", the read signal R
When D is “1”, the NAND circuit 15 sets the read enable signal RDB to “0”, sets the reference voltage generation circuit 14 to an activated state, and supplies the reference voltage RF. The sense amplifier SA is activated in response to the read enable signal RDB “0”. In this state, when the precharge signal FC becomes “1”, the precharge state is established, and the data line is charged to the precharge potential set by the balance between the transistors N22 and P22 of the sense amplifier SA. In the semiconductor memory device that operates at high speed as in this embodiment, the precharge potential is set to a potential lower than the potential of the power supply VD in order to increase the speed of discharging the charge.

Next, when the precharge signal FC changes to "0" and the sampling period begins, the data line corresponding to the memory cell MC selected by the address AD is pulled down to the L level. At this time, a slight change in the potential of the data line is detected by the sense amplifier SA, which is a current sense type sense amplifier, and the read data SO is output.

Next, the wait control circuit 3 performs the following operation when the highest address changes from "0" to "1".

First, when access to one memory block shifts to the other memory block, for example, shifts from the memory block 2A to the memory block 1A, the highest address sensing circuit 31 determines the highest address C.
The rising edge of S is detected, and a sensing signal CSS is generated.
The shift register 32 starts the shift operation in response to the supply of the sensing signal CSS. In this embodiment mode, a 5-bit shift register is used as described above. The AND circuit A31 includes a normal reset signal RES for clearing the initial state of the shift register 32, and a fifth bit output signal OV of the shift register indicating completion of the shift operation.
The logical product of the shift register 32 and the inverted value of 4 is obtained, and a reset signal R is output and supplied to the reset end of the shift register 32.

The selector 33 comprises two two-input AND gates and a two-input OR gate (2AND2OR). When the clock CK is “1”, either the sense signal CSS or the third bit output OV3 of the shift register 32 is output. But'
In the case of "1", "1" is output as the selector signal CKS.

While the shift register 32 performs the shift operation, the flip-flop F31 takes in the value of the address sensing signal CSS at the rise of the selector signal CKS, and outputs the signal E.
O is output. Next, the flip-flop F32 captures the signal EO at the falling edge of the selector signal CKS and outputs the signal FO. Finally, the AND circuit A32 outputs the inverted signal FO of the clock CK and the signal FO at the inverter I31.
A logical AND with B is generated to generate a wait control clock WC.

The wait control clock signal WC is a clock for performing the same operation as the clock CK, and the clock is intentionally extended by four clocks only during the precharge period of the data line. Therefore, from the viewpoint of the CPU 4, the operation is not stopped, so that the next operation is not affected at all. For example, even if the memory block 2A changes from the non-selected state to the selected state, this memory block 2A
Data can be read immediately.

At this time, in the memory block 1A, the word line corresponding to the word line selection signal decoded by the address AD is activated to select the corresponding memory cell.

In response to the deactivation ('1') of the read enable signal RDB, the reference voltage generation circuit 14 enters a non-operating state, and changes the reference voltage RF for operating the sense amplifier SA to the level of the power supply VD. I do. In addition, the sense amplifier SA also becomes inactive in response to the signal RDB of “1”, and always outputs “1” as the read data SO.

Next, when the most significant address signal CS changes from "1" to "0" and the read state, that is, the read signal RD is "1", the memory block 2A
Since the highest address CS becomes “0”, the AND circuit 1
5, the read enable signal RDB output becomes "1", the sense amplifier SA is made inactive, and the data line is discharged. On the other hand, in the memory block 1A, the highest-order address CS is “1”, so that the sense amplifier SA is in the operating state.

Thereafter, the operation of the memory block 2A and the operation of the memory block 1A are performed in the reverse order.

As described above, the semiconductor memory device of the present embodiment selects one of the memory blocks to the operating state by the memory block selection signal generated from the highest address, and sets the wait time corresponding to the precharge time. Setting can completely disable the sense amplifiers and reference voltage generation circuits of other unused memory blocks, thereby reducing the current consumption of the sense amplifiers and reference voltage generation circuits of these unused memory blocks. it can. The above wait time is simply calculated by the CPU operation CK.
Is added by the weight time, so that C
The operation is not stopped from the point of view of PU, so
It has no effect on the next operation.

Considering the setting of the wait time,
When a 64-bit memory is mounted in the bit line direction in a normal RAM, the capacity in the bit line direction is about 1 pF or less, and even a high-speed RAM can be precharged in about 5 ns. . Further, in the case of a current flash ROM, when a 1024-bit horizontal ROM cell is mounted in the bit line direction, the capacity of the bit line is about 4 pF, and the precharge time is about 5 ns. It is possible to charge.

Therefore, depending on the target memory device, the precharge time can be calculated if the bit line capacity of the memory device is clear in advance. By incorporating an analog delay at the time of design in place of the required number of bits and the shift register, the wait time can be set.

Further, even when the memory capacities of a plurality of memory cells are different due to a difference in the number of bit lines or the like, it is possible to set the wait time in accordance with a memory requiring a long precharge time.

Next, referring to FIG. 2, which shows a second embodiment of the present invention in the same manner as FIG. This embodiment is different from the above-described first embodiment in that n memory blocks 1A, 2A, 103A to 10n (n is an integer of 3 or more) A and the highest address CS of the address. The memory block selection signals CS1 to CSn are generated by decoding the upper m bits up to the m-th address (m is the number of bits obtained by expressing n-1 in a binary number) (m is the m-th address). A decoder 5 and a weight control circuit 3A configured to apply a weight to the clock CK in response to the rise and fall of each of the highest address CS to the m-th address CM instead of the weight control circuit 3 are provided. It is when.

For example, assuming that the number n of the memory blocks is 4, this 4-1 = 3 is 11 when expressed in a binary number, and therefore m is 2, so that the m-th address CM is the next highest-order address CM. The address is the second address, that is, the second bit from the most significant bit of the address.

The operation of the present embodiment will be described with reference to FIG. 9 where n is 4, and the decoder 5 determines the memory block 1 based on the highest address CS and the second address CM.
Memory block selection signals CS1 to CS4 for selecting one of A to 4A into an operation state are generated. In this figure,
Top 2 consisting of top address CS and second address CM
The memory block selection signals generated corresponding to the digit values 00, 01, 10, 11 are respectively denoted by CS1, CS
2, CS3 and CS4.

Other operations are the same as those in the first embodiment.

[0047]

As described above, the semiconductor memory device of the present invention includes the steady-state current cutoff means for cutting off the steady-state current when each of the n memory blocks is selected to be in the non-operation state by the selection signal. By providing wait control means for extending the operation clock for a predetermined period during the operation of the steady-state current cutoff means, one of the memory blocks can be selected for operation by the memory block selection signal generated from the upper address, and By setting the wait time corresponding to the charge time, the sense amplifier and the reference voltage generation circuit of the unused memory block can be completely made inactive, so that the sense amplifier and the reference voltage generation circuit of these unused memory blocks can be completely turned off. The current consumption can be reduced, and the wait time is simply set when the CPU operation CK is waited. Since carried out by partial addition, the operation when viewed from the CPU is not stopped, therefore, there is an effect that does not give at all affect the next operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a memory block in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a sense amplifier of FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of a reference voltage generation circuit of FIG. 2;

FIG. 5 is a block diagram illustrating a configuration of a weight control circuit of FIG. 1;

FIG. 6 is a time chart illustrating an example of an operation in the semiconductor memory device according to the present embodiment;

FIG. 7 is a block diagram showing a second embodiment of the semiconductor memory device of the present invention.

FIG. 8 is a block diagram illustrating an example of a conventional semiconductor memory device.

FIG. 9 is a block diagram illustrating a configuration of a memory block in FIG. 8;

[Explanation of symbols]

1,2,1A, 2A, 103A, 10nA memory block 3,3A weight control circuit 4 CPU 5,11 decoder 12 memory cell 13 sense amplifier group 14 reference voltage generation circuit 15 NAND circuit 31 top address sensing circuit 32 shift register 33 , 311 selectors A31, A32 AND circuits F31, F32, F311, F312 flip-flops I1, I41, I311, I312 inverters P41, P42, P43, P44, P45, P46, N
41, N42, N43, N44, N45, P21, P2
2, P23, P24, P25, N21, N22, N2
3, N24, N25 transistor

Claims (6)

[Claims] 1. A semiconductor memory device comprising n (n is an integer of 2 or more) memory blocks each having a current sense type sense amplifier for reading stored data at a high speed by passing a steady current. Of the n memory blocks are selected to be in the non-operation state by a selection signal for selecting one of the n memory blocks as the operation state and the other as the non-operation state. A semiconductor memory device comprising: a current cutoff unit; and a wait control unit for extending an operation clock for a predetermined period during an operation period of the steady current cutoff unit. 2. The stationary current cutoff means performs a logical operation on a read signal, which is a signal activated when the storage data is in a read state and deactivated in a non-read state, and the selection signal, and performs a logical operation on the stationary current. 2. The semiconductor memory device according to claim 1, further comprising a logic circuit that outputs a steady-state current control signal for controlling generation / interruption. 3. The method according to claim 1, wherein n is 2, the first and second memory blocks are provided, and a most significant bit which is a most significant bit of an address signal is used as the selection signal, and a value of the most significant address is one. When the first memory block is set to the operating state and the second memory block is set to the non-operating state, the steady-state current cutoff means of the second memory block is set to the operating state, and When the value is 0, the first memory block is selected to be in an inactive state, the second memory block is selected to be in an active state, and the steady-state current interrupting means of the first memory block is set to an active state. 2. The semiconductor memory device according to claim 1, wherein: 4. The high-order m bits from the most significant bit of the address signal to the m-th (m is the number of bits obtained by expressing n−1 in binary) bit as the selection signal, wherein n is 3 or more. 2. The semiconductor memory device according to claim 1, further comprising: memory block selection decoding means for generating the first to n-th memory block selection signals for selecting the memory block in the operating state by decoding the memory block. 5. A semiconductor memory device comprising n (n is an integer of 2 or more) memory blocks each having a current sense type sense amplifier for reading stored data at a high speed by flowing a steady current. In response to a change in a selection signal for selecting one of the memory blocks as an operating state and the other as a non-operating state, a wait clock is generated by applying a wait for extending an operating clock by a predetermined number of clocks. A weight control circuit, wherein each of the n memory blocks performs a logical operation on a read signal, which is a signal that is activated when the storage data is in a read state and is inactivated when the memory data is not read, and the selection signal, and stores the read signal. A logic circuit that outputs a read enable signal that controls data read, and an address signal that is decoded and A decoder for outputting word selection data; a memory cell for reading data in a memory cell in response to the supply of the word selection data and outputting bit data to a data line; a reference voltage, a precharge signal, and a read enable signal; A sense amplifier group including a plurality of sense amplifiers receiving the supply and outputting read data of each of the memory cells in response to the supply of the bit data; and a reference voltage outputting a reference voltage in response to activation of the read enable signal. A semiconductor memory device comprising: a generation circuit. 6. A selection sensing circuit for outputting a sensing signal in response to the supply of the selection signal, the weight control circuit starting a shift operation in response to the supply of the sensing signal, and setting the operation clock in advance. 6. The semiconductor memory device according to claim 5, further comprising: a shift register that outputs a delay signal delayed by the number of bits, wherein said wait clock is generated from said delay signal.