JP2000021174A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate necessity of setting a margin between data determination and a timing for starting a control signal by passing an input data for a plurality of latch circuit sections without any modification when a data latch control signal is input, while holding the data when the control signal is not input. SOLUTION: A first NAND gate 11 supplies as an input to a first flip-flop a signal in which a level of an input data signal irdOx is inverted when a control signal piOz is supplied, while supplying an H-level signal, irrespective of the data signal status, to the first flip-flop as its input when this control signal is not supplied. On the other hand, a second NAND gate 12 supplies as an input to a second flip-flop a signal in which a level of another input data signal irdOz is inverted when the control signal piOz is in an H-level, while supplying an H-level signal, irrespective of the data signal status, to the second flip-flop as its input when this control signal is in an L-level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a data latch function for temporarily holding data by a pipeline control method when data is read from a memory cell or the like in synchronization with a clock. About.
2. Description of the Related Art Recent semiconductor memory devices such as a synchronous dynamic random access memory (hereinafter abbreviated as SDRAM) are required to operate in synchronization with a high-frequency clock of, for example, 100 MHz or more. In order to meet such a demand, it is necessary to accurately read data in a memory cell of a semiconductor memory device in synchronization with a high-frequency clock. More specifically, a plurality of latch circuits are provided in parallel on a data read path, and the latch circuits temporarily hold the data for each bit of the data, whereby the data read from the memory cell is read. It is necessary to perform pipeline control.

[0002]

2. Description of the Related Art As a typical example of pipeline control of data read from a memory cell of a semiconductor memory device such as an SDRAM, a wave pipeline control method is used. In such a wave pipeline control method, generally, a FIFO is provided in a data read path.
A plurality of latch circuits called “First-in First-out” are provided in parallel, and the latency at the time of data reading (Latency) in these latch circuits is provided.
: Means waiting time). conventionally,
After the data read from the memory cell is determined, F
Wave pipeline control of the data is performed by operating a plurality of latch circuits in the IFO.

Here, an example of a conventional semiconductor memory device having a data latch function based on a wave pipeline control method will be described with reference to FIGS. FIG. 4 is a block diagram showing a configuration of a semiconductor memory device having a general data latch function, FIG. 5 is a circuit diagram showing a configuration of a latch circuit according to a conventional semiconductor memory device, and FIG. 3 is a timing chart for explaining the operation of FIG. In this case, however, F is composed of three latch circuits provided in parallel with the data read path.
The configuration and operation of the semiconductor memory device in the case of performing the wave pipeline control using the IFO will be exemplified.

In the semiconductor memory device shown in FIG. 4, complementary data DATA read from a plurality of memory cells (not shown) arranged in a matrix is provided.
First to third latch circuits 10 for temporarily holding
-1 to 10-3 are provided in parallel with the complementary data read path. These three latch circuits 10-1 to 10-3 have a function of sequentially holding data DATA bit by bit in synchronization with a clock.
In addition, the selector 7 has a function of sequentially sending data DATA held earlier by the selector 7 to the data output buffer 8, and the latch circuits 10-1 to 10-3 and the selector 7 are generally called a FIFO. .

More specifically, the three latch circuits 10-1 to 10-3 are provided with corresponding control signals pi0z, pi1z and p1 for data latch control, respectively.
Input data signals irdx, irdz (input data signals ird0x, ird0 held in the first to third latch circuits) representing complementary data DATA based on i2z.
z, ird1x, ird1z, ird2x and ird
2z) is sequentially stored for each bit. Further, in order to reliably hold the next input data signal, the reset signals drst corresponding to the respective reset signals drst are sent to the data output buffer 8 in order.
The input data signal is cleared by 0x, drst1x and drst2x.

Further, in FIG. 4, a latch circuit 10-
Complementary format data (dlx and dlz) passed through 1 to 10-3 are output data signals dl0x, dl0z, d
These are sent to the selector 7 as l1x, dl1z, dl2x and dl2z. The six output data signals dl0x, dl0z, and d sequentially selected by the selector 7
l1x, dl1z, dl2x and dl2z are output to the outside of the semiconductor memory device via the data output buffer 8 (output data DQ). That is, in the semiconductor memory device of FIG. 4, the data read from the memory cell
To the third latch circuits 10-1 to 10-3 and output from the data output buffer 8 after a certain latency has elapsed.

The specific configuration of each of these latch circuits 10-1 to 10-3 is as shown in FIG. In the latch circuit of FIG. 5 (for example, the first latch circuit 10-1), a first data latch unit including two inverters 150 and 155 holding one input data signal ird0x in a complementary format is provided. . On the other hand, two inverters 1 holding the other input data signal ird0z
A second data latch unit 60 and 165 is provided. These first and second data latch units are:
Respectively, the high voltage level (“H (High)” level) or the low voltage level (“L”
(Low) “level”.

The input data signals ird0x and ird0
rd0z is the N-channel transistors 110 and 120
Are input to the corresponding first data latch unit and second data latch unit, respectively. The drains of these N-channel transistors 110 and 120 are connected to the first
And the input side of the second data latch unit. The source of the N-channel transistor is
It is connected to a low voltage side power supply Vss (for example, ground). One of the complementary input data signals ird0x is N
The data is held in the first data latch unit based on the start timing of the control signal pi0z supplied via the channel transistor 130. The signal held in this way is output from the terminal to which one output data signal dl0x is output. The other input data signal ird0z is also based on the start timing of the control signal pi0z supplied via the N-channel transistor 140.
The data is held in the second data latch unit. The signal held in this way is output from the terminal to which one output data signal dl0x is output.

Further, in the latch circuit of FIG. 5, in order to surely clear the input data signal held in the first data latch section before the next input data signal is input, the reset signal drst0x is set to The data is supplied to the first data latch unit via the P-channel transistor 170. On the other hand, in order to surely clear the input data signal held in the second data latch unit before the next input data signal is input, the reset signal drst is used.
0x is the second through the P-channel transistor 180
Are supplied to the data latch unit. The drains of the P-channel transistors 170 and 180 are connected to the input sides of the first and second data latch units, respectively. The source of the P-channel transistor is connected to a high-voltage power supply Vii (for example, Internal power supply).

The operation of the semiconductor memory device of FIG. 4 is as shown in FIG. First to third latch circuits 10-1 to 10
-3 so that the data DATA (first to fourth data D0, D1, D2, and D3) input to -3 can be latched in the order in which they are received. The rise (“L” → “H”) and the fall (“H” →
"L") must be within the validity period of the desired data (for example, the first data D0). Further, reset signals drst0x, drst1x, and d
When each of rst2x (for example, a negative pulse reset signal drst0x) is supplied to the latch circuit, data cannot be input to the latch circuit during a period in which the reset signal is supplied.

For example, if the control signal pi0z rises to the "H" level when the state of the first data D0 has not yet been determined, the first data latch unit and the second data latch A phenomenon occurs in which the outputs of the sections become the same level (for example, the outputs of both data latch sections become “L” level), and the data once held may be destroyed. Further, the second data D
Even when the control signals pi1z and pi2z rise to the "H" level when the states of the first and third data D2 have not been determined yet, as in the case described above, they are once held. Data may be corrupted. In addition, since there is a variation in the time until the state of the input data is completely determined, the control signal (for example, the first latch signal) is set after the state of the data (for example, the first data D0) is determined. Control signal pi for circuit control
It was necessary to take a certain margin between the rise of 0z) and the start of the data latch.

[0012]

As described above, when data is latched by a plurality of latch circuits in a conventional semiconductor memory device, a margin is required between the time when the data state is determined and the time when the data latch is started. Therefore, there is a problem that a time delay until the data is held in the latch circuit increases, and a data access time increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a semiconductor device capable of shortening the data access time when data is latched by a plurality of latch circuits in a data read operation as compared with the related art. It is an object to provide a storage device.

[0014]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention, which inputs and outputs data in synchronization with a clock, temporarily holds the data in a data read path. A plurality of latch circuit sections for performing the above operation. Each of these latch circuit sections, when a control signal corresponding to the data is input, passes the data input to the latch circuit section as it is. When the control signal is not input, data is held. Preferably, in the semiconductor memory device of the present invention, data held in each of the latch circuit units can be reset.

FIG. 1 is a block diagram showing the principle configuration of the present invention. FIG. 1 is shown to further clarify the features of the semiconductor memory device of the present invention. As shown in FIG. 1, a semiconductor memory device according to the present invention which inputs and outputs data DATA in synchronization with a clock includes a plurality of latch circuit units (first units) for temporarily holding data in a data read path. Of latch circuits 1-1 to n-th). Each of the first to n-th latch circuit units 1-1 to 1-n includes a data holding unit (first data holding unit) including at least one flip-flop that sequentially stores the data state bit by bit. 3-1
N-th data holding means 3-n) and switching means (first switching means) for switching between passing and holding of data, respectively, depending on whether or not control signals Sc0 to Scn corresponding to the data are input. 2-1 to n-th switching means 2-
n).

In FIG. 1, when the control signal (either a positive pulse or a negative pulse) is input to the switching means, the data input to the data holding means is passed as it is, Is not input to the switching means, the state of the data which has passed through the data holding means last is stored in the flip-flop. The data that has passed through the data holding means is output to the outside of the semiconductor memory device via the data output circuit 4 (output data DQ).

Preferably, in the semiconductor memory device according to the present invention, the switching means includes at least one AND gate having the control signal and the data as input signals.
More preferably, in the semiconductor memory device of the present invention, the state of data stored in the flip-flop can be reset using reset signals Sr0 to Srn.

According to the semiconductor memory device having the data latch function of the present invention, as described above, at the timing when the control signal is input to each of the plurality of latch circuits, the data input to the above-mentioned latch circuit portion is deleted. Let it pass,
Since the last passed data is held at the timing when the control signal ends, it is not necessary to strictly set the timing from the determination of the data state to the input of the control signal. That is, the start timing of the control signal for data can be made timing-free.

Thus, according to the present invention, it is not necessary to take a margin between the time when the data state is determined and the time when the data latch is started during the data read operation. It is possible to greatly reduce the data access time.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention (hereinafter, referred to as an embodiment) will be described with reference to the accompanying drawings (FIGS. 2 to 3). FIG. 2 is a circuit diagram showing a specific configuration of the latch circuit according to one embodiment of the present invention, and FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention.

Also in this case, similarly to the above-described prior art, the configuration of the semiconductor memory device in the case where the wave pipeline control is performed using the FIFO composed of three latch circuits provided in parallel to the data read path. And the operation will be exemplified. However, the schematic configuration of such a semiconductor memory device is the same as that shown in FIG.
The configuration is the same as Therefore, here, the configuration and operation of one embodiment of the present invention will be described with reference to FIGS. 5, 2 and 3. Hereinafter, the same components as those described above will be denoted by the same reference numerals.

In a semiconductor memory device according to one embodiment of the present invention, a plurality of latch circuit portions of the present invention (see FIG. 1)
The first to third latch circuits 10-1 to 10-3 are provided in parallel with the data read path. These first to third latch circuits 10-1 to 10-1
Reference numeral -3 temporarily holds complementary data DATA read from a plurality of memory cells (not particularly shown) arranged in a matrix. These three latch circuits 10-1 to 10-3 have a function of sequentially holding data DATA bit by bit in synchronization with the clock, and sequentially output data DATA 8 from the data DATA held earlier. , And is generally called a FIFO.

More specifically, the above-mentioned three latch circuits 10-1 to 10-3 are provided with corresponding control signals pi0z, pi1z and p1 for data latch control, respectively.
Based on i2z, input data signals irdx and irdz representing complementary data DATA are sequentially held for each bit. These control signals pi0z, pi1z, and pi2z correspond to the control signals Sc0 to Scn shown in FIG. Further, the latch circuit 10- is first connected so that the next input data signal can be reliably held.
The input data signals held in 1 to 10-3 are reset to corresponding reset signals drst0x and drst1.
x and drst2x. These reset signals drst0x, drst1x
And drst2x are the reset signal Sr shown in FIG.
0 to Srn. That is, the control signals pi0z,
With pi1z and pi2z, the latch circuits 10-1 to 10-1
The state (“H” level or “L” level) of the data stored in 10-3 is released. A data bus indicating a read path of the data DATA is commonly connected to the three latch circuits 10-1 to 10-3, and the input data signals irdx and irdz are commonly input to the three latch circuits.

In FIG. 2, the latch circuit 10-
Complementary format data (dlx and dlz) passed through 1 to 10-3 are output data signals dl0x, dl0z, d
These are sent to the selector 7 as l1x, dl1z, dl2x and dl2z. The output data signals dl0x, dl0z, dl1 sequentially selected by the selector 7
x, dl1z, dl2x, and dl2z are output to the outside of the semiconductor memory device via the data output buffer 8 (output data DQ). In this case, although there are three types of data, since each data is in a complementary format,
One output data signal is output.

A latch circuit 10 according to an embodiment of the present invention
The specific configuration of each of 1 to 10-3 is as shown in FIG. The latch circuit of FIG. 2 (for example, the first latch circuit 10-1) serves as a data holding means (see FIG. 1) of the present invention, and is used to sequentially store the state of the complementary input data signal bit by bit. A first flip-flop including two NAND gates 13 and 14 and a second flip-flop including two NAND gates 15 and 16 are provided. Here, the first flip-flop is a flip-flop for storing the "H" level or "L" level state of one input data signal ird0x, and the second flip-flop is used for storing the other input data signal ird0x. ird
This is a flip-flop for storing the state of “H” level or “L” level of 0z.

Further, the latch circuit of FIG. 2 uses a control signal (for example, control signal pi0z) for data latch control and one input data signal ird0x as two switching means (see FIG. 1) of the present invention. A first NAND gate (logical product gate) 11 serving as an input signal, a control signal for controlling data latching, and the other input data signal ir
A second NAND gate (logical product gate) 12 having d0x as two input signals is provided.

When the control signal pi0z is supplied (for example, the signal is at "H" level), the first NAND gate receives one input data signal ird0x.
Is input to the first flip-flop, and the control signal pi0z is not supplied (for example,
When the signal is at "L" level, a signal at "H" level is input to the first flip-flop regardless of the state of the data signal. That is, only when the control signal pi0z is supplied, the first flip-flop is operated to hold the input data signal. On the other hand, the above-mentioned second NAND gate outputs the control signal pi0z
Is at the "H" level, a signal obtained by inverting the level of the other input data signal ird0z is input to the second flip-flop. When the control signal pi0z is at the "L" level, An "H" level signal is input to the second flip-flop regardless of the state. That is, in this case, the control signal pi0 of the positive pulse
While z rises and is at the “H” level, the flip-flop is operated to sequentially pass the input data signal, and the input data signal passed through the flip-flop is held at the falling timing of the control signal. , The state of the input data signal is finally determined.

Therefore, in the latch circuit of FIG. 2, the rising timing of the control signal with respect to the data can be made timing-free. Therefore, even if the control signal is supplied earlier than the data, the falling of the control signal can be achieved. It is finally possible to hold correct data at the timing of (1). The operation of the embodiment of FIG. 2 is as shown in FIG. First to third latch circuits 10-1 to 10-1
10-3 input data DATA (first to fourth data).
Each of the control signals pi0z, pi1z and piz falls ("H" → "L") so that the data latches can be performed in the order in which the data D0, D1, D2 and D3) have entered. Must be within the validity period of the desired data (for example, the first data D0). However, as described above, the control signal p
The rising edge (i.e., "L" → "H") of each of i0z, pi1z, and pi2z does not need to be set strictly, and therefore, regardless of whether the data state is determined or not.
The control signal (for example, the first control signal pi0z) can be supplied at a timing earlier than the start of the data (for example, the first data D0).

Therefore, in the embodiment of the present invention, after the state of the data (for example, the first data D0) is determined, the control signal (for example, the first control signal pi0z) is raised to activate the data latch. Since there is no need to take a margin before starting, there is almost no time delay until data is held in the latch circuit, and data access time is greatly reduced. In this case, after the state of the last passed data (for example, the first data D0) is determined, the reset signal (for example, the first reset signal dr)
st0x) to the latch circuit to release the state (“H” level or “L” level) of the data stored in the flip-flop in the latch circuit,
It becomes possible to input the fourth data D3.

[0030]

As described above, according to the semiconductor memory device of the present invention, first, when the control signal for data latch control is inputted, the data inputted to the plurality of latch circuit portions are provided. Is passed as it is, and when the control signal is not input, the data is held. Therefore, there is no need to take a margin between the time when the data is determined and the time when the control signal is started. Can be greatly reduced.

Furthermore, according to the semiconductor memory device of the present invention, secondly, after the data transfer, the data held in the latch circuit can be quickly reset, so that the data access time is increased. This makes it possible to output the data accurately in the order in which the data has entered. Further, according to the semiconductor memory device of the present invention, thirdly, when a control signal for data latch control is input, the flip-flops of the plurality of latch circuit sections are operated to pass data, and When a signal is not input, data is stored.Therefore, there is no need to take a margin between data confirmation and the timing of starting a control signal, and data access time can be greatly reduced. Will be possible.

Further, according to the semiconductor memory device of the present invention, fourthly, it is determined whether or not a control signal is input by NAN.
The data is detected by the D gate, and the data passing or data holding by the flip-flops of the plurality of latch circuits is switched in accordance with the result of the detection. Can be held in the flip-flop of the section.

Fifth, according to the semiconductor memory device of the present invention, after the data is transferred from the flip-flop of the latch circuit portion, the data in the flip-flop can be quickly reset, so that data access is possible. Without increasing the time, the data can be output accurately in the order in which the data enters the flip-flop.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle configuration of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a latch circuit according to one embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a semiconductor memory device having a general data latch function.

FIG. 5 is a circuit diagram showing a configuration of a latch circuit according to a conventional semiconductor memory device.

FIG. 6 is a timing chart for explaining the operation of FIG. 4;

[Explanation of symbols]

1-1 to 1-n... First to n-th latch circuit portions 2-1 to 2-n... First to n-th switching means 3-1 to 3-n. 4 Data Output Circuit 7 Selector 8 Data Output Buffer 10-1 to 10-3 First to Third Latch Circuits 11 to 16 NAND Gates 110, 120, 130 and 140 N-Channel Transistors 150 and 155 , 160 and 165: inverter 170, 180: P-channel transistor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yuichi Uzawa 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kunori Kawabata 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Limited (72) Inventor Yo Kikutake 4-1-1 Kamiodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1 (1) Inventor Tohru Koga 4-chome Kamiodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 No. 1 Fujitsu Limited F term (reference) 5B015 AA07 BA64 5B024 AA15 BA29 CA07 5J039 EE15 KK04 KK29 MM03 NN06

Claims (5)

[Claims] 1. A semiconductor memory device comprising: a plurality of latch circuits for inputting / outputting data in synchronization with a clock and temporarily holding the data in a path for reading the data; When a control signal corresponding to the data is input, each of the plurality of latch circuit units passes the data input to the latch circuit unit as it is, and when the control signal is not input, A semiconductor memory device characterized by holding the following. 2. The semiconductor memory device according to claim 1, wherein data held in each of said latch circuit units can be reset. 3. A semiconductor memory device comprising: a plurality of latch circuit sections for inputting and outputting data in synchronization with a clock and for temporarily holding the data in a path for reading the data; Each of the plurality of latch circuit units includes a data holding unit including at least one flip-flop that sequentially stores a state of the data for each bit, and according to whether a control signal corresponding to the data is input. Switching means for switching the passage or holding of data, when the control signal is input to the switching means,
The semiconductor memory device according to claim 1, wherein the data input to the data holding means is passed as it is, and when the control signal is not input to the switching means, the data is stored in the flip-flop. 4. The semiconductor memory device according to claim 3, wherein said switching means includes at least one AND gate that receives said control signal and said data as input signals. 5. The state of data stored in the flip-flop can be reset.
13. The semiconductor memory device according to claim 1.