JP2000021163A - Refresh control circuit for storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable refreshing of a plurality of memory modules without adversely affecting a normal memory access operation by allowing the respective memory modules to be refreshed based on update history of each memory module. SOLUTION: A memory module update management circuit 11 manages update history of a memory access for each of memory modules 17 and 18, and contains memory module updating flags and self-refresh performing flags each corresponding to the respective memory modules. In addition, it is determined to which memory module an address corresponds based on a memory module address signal that has been input from a main control circuit 12, and it is further determined whether or not self-refreshing has been performed. The main control circuit 12 then performs the self-refreshing for the memory module that has not been updated for a long period of time, while simultaneously allowing an access to the other memory modules to be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a refresh control circuit for a storage device, and more particularly, to a refresh control circuit for a storage device for refreshing a plurality of memory modules.

[0002]

2. Description of the Related Art Conventionally, a refresh control circuit for refreshing a storage device has been known. In the refresh control circuit of this storage device, an asynchronous DRAM (dynam) is used.
When refreshing a plurality of memory modules configured by random access memory, access to a storage element is stopped and all memory modules are refreshed.

[0003]

However, every time the memory module is refreshed, the memory access to the storage elements is stopped and all the memory modules are refreshed. Therefore, the memory access is in a standby state during the refresh period. turn into. In addition, since the refresh period is long, refreshing has been a cause of system performance degradation.

An object of the present invention is to provide a refresh control circuit of a storage device capable of refreshing a plurality of memory modules without affecting a normal operation of memory access.

[0005]

In order to achieve the above object, a refresh control circuit of a storage device according to the present invention comprises:
In a refresh control circuit of a storage device for refreshing a plurality of memory modules, refresh is performed for each memory module based on an update history for each memory module.

With the above configuration, when refreshing a plurality of memory modules, refresh is performed for each memory module based on the update history for each memory module. Thus, a plurality of memory modules can be refreshed without affecting the normal operation of memory access.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a refresh control circuit of a storage device according to an embodiment of the present invention. As shown in FIG. 1, the refresh control circuit 10 includes a memory module update management circuit 11, a main control circuit (memory module access control means) 12, an address output circuit 13, a clock enable output circuit 14, a timing signal output circuit 15, and It has a timer circuit 16.

The refresh control circuit 10 is connected to two memory modules 17 and 18. These memory modules 17 and 18 are composed of a synchronous DRAM capable of performing a self-refresh operation.

The memory module update management circuit 11 manages an update history of memory access to each of the memory modules 17 and 18, and
8 has a memory module update flag and a self-refresh execution flag.

This memory module update management circuit 11
Determines which of the memory modules 17 and 18 is the address based on the memory module address signal input from the main control circuit 12, and determines whether or not the self refresh is being executed.

According to the address determination, the memory module 1
7 is set to the corresponding memory module update flag, and to the memory module 18, the corresponding memory module update flag is set to "1". If it is determined that the self-refresh is being executed, the corresponding self-refresh execution flag is set to "1".

The reset of the memory module update flag and the self-refresh execution flag is executed when the periodic refresh is performed.

The main control circuit 12 performs an address output circuit 13, a clock enable output circuit 14, and a timing signal so that a self-refresh can be performed on a memory module having a long non-updated period and at the same time an access can be performed on another memory module. A control signal is output to the output circuit 15.

By receiving the control signal, the address output circuit 13 outputs the memory address signal ADR, and the clock enable output circuit 14 outputs the clock enable signal CKE.
And the timing signal output circuit 15 outputs various timing signals to the memory modules 17 and 18, respectively.

The timer circuit 16 has respective timers (not shown) corresponding to the respective memory modules 17 and 18. When the periodic refresh is performed, all the timers are reset or the timers of the respective memory modules 17 and 18 are reset. Each time the timer is updated, the timer corresponding to the memory module is reset, and the timer starts counting again.

The main control circuit 12 has an address signal ADR
And the command signal CMD, and the clock signal CLK is supplied to the refresh control circuit 10 and both the memory modules 17 and 18.

FIG. 2 is a time chart of an address signal, a clock enable signal, and various timing signals during a self-refresh operation. In the figure, a indicates a self refresh start timing, and b indicates a self refresh end timing. FIG. 3 is a time chart of an address signal, a clock enable signal, and various timing signals during a memory access operation. In the figure, c is the operation reception timing, d is the command reception timing, and e is the operation end timing.

First, the main control circuit 12 which has received the address signal ADR and the command signal CMD from a processor (not shown) outputs a module address signal to the memory module update management circuit 11. The memory module update management circuit 11 sets an update flag corresponding to the memory module accessed by the module address signal, and outputs update information to the main control circuit 12.

Next, the main control circuit 12 includes the timer circuit 1
6. Monitor each timer inside 6. When a certain timer counts 8 μs, the main control circuit 12 receiving the non-update report signal output from the timer circuit 16
Determines which memory module corresponds to the signal from the timer, and determines a memory module having no update history of 8 μs count.

In this embodiment, for example, if the non-update period of the memory module 18 exceeds 8 μs, as a result of the determination, the clock enable output circuit 14 receives the control signal from the main control circuit 12 and sends it to the memory module 18. A clock disable signal which is a negative value of the clock enable signal CKE is output.

The timing signal output circuit 15 receives a control signal from the main control circuit 12 and executes a self-refresh to the memory module 18. Therefore, as shown in FIG. chip select: chip selection),
RAS (row address strobe: row address strobe), CAS (column addr)
It outputs various timing signals such as ess strobe: column address strobe and WE (write enable: writable).

By the operation of the refresh control circuit 10 described above, the memory module 1 whose non-update period is 8 μs or more is
8 executes self-refresh. At the same time, the memory module update management circuit 11 that has received the self-refresh execution report signal of the memory module 18 output from the main control circuit 12 sets the self-refresh execution flag corresponding to the memory module 18 to “1”. This self-refresh ends at the self-refresh end timing b.

When a periodic refresh request is received, the main control circuit 12 refreshes the address output circuit 13 and the clock enable output circuit so as to refresh only the memory module whose self-refresh execution flag corresponds to "0". 14 and timing signal output circuit 15
To output a control signal.

While the memory module 18 is performing the self-refresh, the processor
3, the clock enable signal CKE, the memory address signal ADR, and various timing signals (C) at the operation reception timing c, the command reception timing d, and the operation end timing e, as shown in FIG.
S, RAS, CAS, WE, etc.)
7, the normal operation is executed.

As described above, the refresh control circuit 10 of the storage device according to the present invention includes the memory modules 17 and 1
8 has a memory module update management circuit 11 for managing the update history of memory access, and a main control circuit 12 capable of executing a self-refresh for a memory module having a long non-updated period and simultaneously accessing other memory modules. ing. Therefore, self-refresh and periodic refresh can be performed without affecting the normal operation of memory access, and system performance can be improved.

[0027]

As described above, according to the present invention,
When refreshing a plurality of memory modules, the refresh is performed for each memory module based on the update history for each memory module, so that the plurality of memory modules provided are not affected without affecting the normal operation of memory access. Refresh can be performed without deteriorating system performance.

[Brief description of the drawings]

FIG. 1 is a block diagram of a refresh control circuit of a storage device according to an embodiment of the present invention.

FIG. 2 is a time chart of an address signal, a clock enable signal, and various timing signals during a self-refresh operation.

FIG. 3 is a time chart of an address signal, a clock enable signal, and various timing signals during a memory access operation.

[Explanation of symbols]

 Reference Signs List 10 refresh control circuit 11 memory module update management circuit 12 main control circuit 13 address output circuit 14 clock enable output circuit 15 timing signal output circuit 16 timer circuit 17, 18 memory module ADR memory address signal CKE clock enable signal CMD command signal CLK clock signal CS Chip select timing signal RAS Row address strobe timing signal CAS Column address strobe timing signal WE Writable timing signal a Self-refresh start timing b Self-refresh end timing c Operation reception timing d Command reception timing e Operation end timing

Claims (6)

[Claims] 1. A refresh control circuit of a storage device for refreshing a plurality of memory modules, wherein the refresh control circuit of the storage device refreshes each memory module based on an update history of each memory module. . 2. A memory module update management means for managing a memory access update history in each memory module, a self-refresh execution for a memory module having a long non-updated period, and an access to another memory module during the self-refresh execution. 2. A memory module access control means for executing the program.
3. The refresh control circuit for a storage device according to claim 1. 3. The refresh control circuit according to claim 2, wherein said memory module update management means has a memory module update flag and a self-refresh execution flag corresponding to each memory module. 4. A refresh control circuit of a storage device for refreshing a plurality of memory modules, comprising: a memory module update flag and a self-refresh execution flag corresponding to each memory module; Memory module update management means for managing an update history, and memory module access control means for outputting a control signal for executing access to another memory module simultaneously with execution of self-refresh for a memory module having a long non-updated period Address output means for outputting a memory address signal in response to input of the control signal; clock enable output means for outputting a clock enable signal in response to input of the control signal; and various timings in response to input of the control signal Refresh control circuit of the memory device, wherein the timing signal output means for outputting the items, in that it has a timer means for performing a timer reset of the respective memory module. 5. The memory module access control means executes a self-refresh of each of the memory modules when the non-updated period is equal to or longer than a predetermined value, and sets a self-refresh execution flag to "0" when a periodic refresh request is received. 5. The refresh control circuit according to claim 2, wherein only the memory module corresponding to "0" is refreshed. 6. The refresh control circuit according to claim 1, wherein each of said memory modules comprises a synchronous DRAM capable of performing a self-refresh operation.