JP2000020392A - Cyclic address generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a cyclic address for arbitrary step width (increment) in any arbitrary address space of a data memory. SOLUTION: This circuit is provided with a start address setting means 11 for setting a start address to become the start point of the cyclic address for accessing a data memory 4, increment setting means 51 for setting the increment of the address until the cyclic address is once circulated, access time setting means 8 for setting the number of times of access to the data memory until the cyclic address is once circulated, and arithmetic means 21, 61 and 7 for successively integrating the increment set by the increment setting means 51 each time the data memory 4 is accessed, adding that integrated value to the start address, outputting the result as the cyclic address and clearing the integrated value when the number of times of access set by the access time setting means 8 is reached.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cyclic address generating circuit capable of generating an address for circulating and accessing a fixed memory space (hereinafter referred to as a "circular address") when performing memory access. .

[0002]

2. Description of the Related Art In recent years, digital technology has been applied to various products. In digital signal processing, access to a certain continuous memory space is often repeated.

For this reason, in the prior art, by setting the first address of a memory space for accessing a data memory, a cyclic address generation that can repeatedly and sequentially access a certain range of addresses from the first address is performed. Circuits are provided (see, for example,
3-158622).

Hereinafter, this type of conventional cyclic address generation circuit will be described with reference to the drawings.

FIG. 7 is a block diagram showing a configuration of a cyclic address generation circuit provided in a conventional digital signal processor.

Referring to FIG. 1, reference numeral 1 denotes a start address register for registering in advance a start address serving as a starting point of a cyclic address specified in a data memory; 10 a binary counter for sequentially increasing addresses; Is an address generating adder for adding the outputs of the register 1 and the binary counter 10, and 9 is a buffer pointer which takes in the output of the address generating adder 3 and designates the address of the data memory 4 each time a memory access occurs. Is a data memory in which predetermined data is stored.

Next, the operation of the cyclic address generation circuit having the configuration shown in FIG. 7 will be described.

A value counted by the binary counter 10;
The address generation adder 3 adds the start address As held in the start address register 1 in advance. The result of the addition is held in the buffer pointer 9 and the address of the data memory 4 specified by the buffer pointer 9 is accessed.

In this case, the addition result added by the address generation adder 3 is initially A as shown in FIG.
Since the count value of the binary counter 10 returns to “0” after the last address As + 2 ⁿ⁻¹ is continuously updated starting from the address of s, the buffer pointer 9
Is updated again to the start address As, and the address is accessed cyclically. Therefore, the memory area of the data memory 4 has an address space in the range of As to As + ^2n-1 .

[0010]

However, in the conventional cyclic address generation circuit shown in FIG. 7, since the address increment is always "1", the following inconvenience may occur.

(1) When storing data in the data memory 4, if the data length of the data to be stored is longer than the storage width of the data memory, the data to be stored is divided into a plurality of pieces and stored in the memory. Need to be done. In such a case, there is a case where continuous addresses cannot be designated by the conventional device.

For example, when 16-bit data is to be written, if the data memory 4 has an 8-bit configuration, the upper 8 bits and lower 8 bits are usually divided and stored in even and odd addresses of the memory. Will do.

When data processing is performed with such a data structure, if the calculation accuracy is not so high, the top 8
Even if only the bits are used, the operation result may be a sufficient value.

In such a situation, only the upper 8 bits of data need be accessed, so that every other address (ie, only even addresses or only odd addresses) can be specified for the data memory 4. It will be good.

However, in the conventional cyclic address generation circuit, since the increment of the address is always "1", it is not possible to specify every other address with the configuration.

In order to realize such access, an arithmetic circuit for thinning out every other address is separately inserted between the adder 3 and the data memory 4, or the data is stored in the memory. In this case, the upper 8 bits must be relocated to another address space as new data to perform the operation.

(2) When accumulating data for each item, usually, data having the same meaning is collectively stored. If the number of data is the same for each item,
The m-th data of each item is stored with a fixed step.

When it is desired to operate the m-th data of each item, if the data cannot be accessed in a fixed increment, the processing efficiency is reduced.

(3) In a database or the like, there are many cases where the contents are different but the same kind of data is contained. If these restrictions are placed on the data arrangement address, etc., the number of data cannot be increased or the storage order cannot be changed. Therefore, it must be arranged anywhere in the memory space.

At this time, in the conventional cyclic address generation circuit, as shown in FIG. 8, since there is only one start address As, it is desired to repeat the same processing for data placed in a memory space different from this. In some cases, for example, after the first processing is completed, the start address must be changed and the processing must be performed again, and it is not possible to continuously address a plurality of memory spaces.

An object of the present invention is to solve such a conventional problem, and it is an object of the present invention to generate a cyclic address which can be accessed in an arbitrary address space while regularly adding an arbitrary increment. I do.

[0022]

According to the present invention, there is provided a circuit for generating a cyclic address for cyclically accessing a data memory in a part of its memory space. The configuration is as follows.

That is, in the invention according to claim 1,
Start address setting means for setting a start address serving as a start point of the cyclic address; increment setting means for setting an increment of an address until the cyclic address makes one round;
Access number setting means for setting the number of accesses to the data memory during one cycle of the cyclic address; and increments set by the increment setting means each time the data memory is accessed, and the integrated value is added to the start address. And output as a cyclic address, and an arithmetic means for clearing the integrated value when the number of accesses set by the access number setting means is reached.

According to the second aspect of the present invention, in the first aspect,
In the cyclic address generation circuit described above, the start address setting means is configured to be able to set a plurality of start addresses, and the arithmetic means is configured to individually add the integrated value to each start address. It is configured.

According to a third aspect of the present invention, in the cyclic address generating circuit according to the second aspect, the increment setting means includes:
The arithmetic means is configured to be able to set a plurality of increments, and the arithmetic means is configured to individually add each integrated value obtained by individually integrating the increments set by the increment setting means to each start address. Have been.

[0026]

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a cyclic address generation circuit according to Embodiment 1 of the present invention.

[0027] In the figure, 1 ₁ is the start address register for storing a start address serving as a starting point a cyclic address, 2 ₁ denotes an adder for calculating the increment of the address. The adder 2 ₁ adds the value supplied from the increment input register 5 ₁ below and its output, and outputs the added value, the addition value output is cleared by the coincidence signal from the comparator 7 It has become so.

[0028] 5 ₁ increment input register in advance stores the increment of address when repeatedly accessing the data memory 4, 6 ₁ a counter for counting the number of accesses to the data memory 4. And this counter 6
₁ is such that each time a memory access signal indicating that the data memory 4 has been accessed is input, the count value is incremented and the count value is cleared by the coincidence signal output from the comparator 7. Has become.

Further, a cyclic step register for 8 to set the upper limit of the count value of the counter ₆₁ in advance, 7
Is a comparator that compares the value of the counter 6 with the value of the cyclic step register 8 and outputs a match signal when the values match.

[0030] Then, the start address setting means start address register 1 ₁ described above in the claims, the increment setting means increment input register 5 ₁ in the appended claims, the cyclic steps register 8 in the claims access number setting means, the adder 2 _1, the counter ₆₁ and the comparator 7 respectively correspond to the calculating unit in the claims.

Reference numeral 3 denotes an address generating adder, 4 denotes a data memory, and 9 denotes a buffer pointer. These components are the same as those of the conventional example shown in FIG.

Next, the operation of the configuration shown in FIG. 1 will be described with reference to the timing chart shown in FIG. Here, for ease of understanding, now, is "0" in the start address register 1 _1, the cyclic steps in the register 8 is "3", the increment input register 5 ₁ "1
It is assumed that "0" is set in each case.

[0033] In the initial state, the adder when the 2 ₁ and the counter ₆₁ value is cleared to have become "0", the address generation adder 3, the start address register 1 ₁ and the adder 2 _Since the value of ₁ has been entered,
The output value becomes "0", and this value is set in the buffer pointer 9.

Here, when the first memory access occurs, the data memory 4 is accessed at the address “0” already specified by the buffer pointer 9.

[0035] The access, the count value becomes "1" the counter ₆₁ is incremented, cyclic Since step value of the register 8 is "3", the comparator 7 mismatch signal (low here from Level signal) is output.

The adder 2 _1, because the addition of the increment input register 5 ₁ and its output, the value is "0" + "10" =
It becomes “10”. Further, the address generation adder 3
Since adding this value is the output value of the start address register 1 ₁ to "0", the value of "10" + "0" = "10" is set in the buffer pointer 9.

Here, when the second memory access occurs, the data memory 4 is accessed at the address “10” already specified by the buffer pointer 9.

[0038] This access, since the counter ₆₁ is the count value is incremented is "2",
The comparator 7 outputs a non-coincidence signal (for example, a low-level signal).
Is output. The adder 2 _1, because the addition of the increment input register 5 ₁ and its output, the value is "10" + "1
0 "=" 20 ". Further, since the address generation adder 3 adds this value to" 0 "which is the output value of the start address register 1," 20 "+" 0 "=" 2 ".
A value of “0” is set in the buffer pointer 9.

Here, when the third memory access occurs, the data memory 4 is accessed at the address “20” already specified by the buffer pointer 9.

[0040] The access counter _61, since the count value is "3" is incremented is equal to the preset in which the value "3" in a cyclic step register 8. Therefore, the comparator 7 outputs a coincidence signal (here, a high-level signal).

[0041] In response to this coincidence signal, the added value of the adder 2 ₁ output value is cleared to "0", the output value of the address generation adder 3 is also "0", the buffer pointer This value “0” is set in 9. At the same time, the count value of the counter ₆₁ by the coincidence signal be cleared becomes "0". That is, they all return to the initial state.

Next, when occurs fourth memory accesses, as described above, the address generation adder 3 start address register 1 ₁ and the adder 2 ₁ values are input output value is "0", Since this is set in the buffer pointer 9, the data memory 4 stores the buffer pointer 9
Is accessed at address "0" specified by.

As described above, the addresses accessed for the data memory 4 are "0", "10", "2".
0 ”→“ 0 ”,“ 10 ”,“ 20 ”→“ 0 ”, etc. In other words, the output is repeated within a fixed address range (“ 0-20 ”in this example). (In this example, "10"), the address is generated in a cyclic manner.

A plurality of components other than the buffer pointer 9 and the data memory 4 in the first embodiment are provided in parallel, and the output of the address generation adder 3 is alternately switched in a time-division manner to the buffer pointer 9. With this configuration, it is possible to generate a cyclic address that can be accessed while adding an independent increment to each of a plurality of address spaces, although the overall configuration is complicated.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration of a cyclic address generation circuit according to Embodiment 2 of the present invention. In FIG. 3, parts corresponding to the configuration of Embodiment 1 shown in FIG. Assign a sign.

[0046] In the second embodiment, the start address register 1 ₂ is adapted to store the start address of the N (N ≧ 2) at the same time, among the N number of the start address by the start pointer 11 described later Is designated, only one designated start address is read.

[0047] 11 is a start pointer for designating one of the N number of the start address that is registered in advance in the start address register 1 _2, the start pointer 11 that is accessed to the data memory 4 Each time the indicated memory access signal is inputted, the designation of the start address is changed one by one.

[0048] 2 ₂ adders, 6 ₂ is a counter, a basic structure of such adders 2 ₂ and the counter 6 ₂ is the same as in embodiment 1 shown in FIG. 1, this In the second embodiment, further two 2 _2, 6 ₂ operation permission signal to the
(Here, a high level signal) is given together, and operation is possible only when this operation permission signal is given, and a state where the operation permission signal is not given (here, a low level state) so both 2 _2, 6 ₂ are configured such that operation is forcibly stopped.

Here, the above-mentioned operation permission signal corresponds to C
PU provided by the PU or the like.
The first (against which the data memory 4, a block last address is the same as the time point designated Accordingly buffer pointer 9 of the cyclic address) the start address is specified when only adders 2 ₂ and counter by 6 ₂
Is output to

[0050] Incidentally, the address generation adder 3, the data memory 4, increment input register 5 _1, configuration of the comparator 7, a cyclic step register 8, and the buffer pointer 9 are similar to those in the embodiment 1, Here, detailed description is omitted.

Next, the operation of the configuration shown in FIG. 3 will be described with reference to the timing chart shown in FIG. Here, for ease of understanding, in advance as a start address in the start address register 1 ₂ "1
00 ”and“ 2000 ”are set (thus, N = 2),
Moreover, cyclic in the step register 8 "2" is assumed to the increment input register 5 ₁ "5" is set, respectively.

In the initial state, the start pointer 11
Is reset, further, adders 2 ₂ and the counter 6 ₂
Is cleared and its value is "0". At this time, the operation both 2 ₂ permission signal is not given together to an adder 2 ₂ and the counter 6 _2, 6 ₂ are both in an operable state and, as a start address from the start address register 1 ₂ " 100 ", the output of the address generation adder 3 is" 0 "is read out, also in order to the adder 2 ₂ is reset" 100 ", and this value is set in the buffer pointer 9.

Here, when the first memory access occurs, the data memory 4 is accessed at the address “100” already specified by the buffer pointer 9.

With this access, the start pointer 1
1, because it specifies the following "2000" as the start address of the start address register 1 _2, the start address "2000" is read out. At this time, since the operation permission signal is not output, the adder 2 ₂ and the counter 6 ₂
Does not operate, the output of both 2 _2, 6 ₂ is directly held, an output of the adder 2 ₂ "0", the output of the counter 6 ₂ which is still "0". Therefore, the output of the address generation adder 3 is "2000", and this value is set in the buffer pointer 9.

Here, when the second memory access occurs, the data memory 4 is accessed at the address "2000" already specified by the buffer pointer 9.

With this access, the start pointer 1
1, since specify "100" as the start address of the start address register 1 _2, the start address "100" is read. At this time, since the operation permission signal is out, adder 2 _2, since the sum of the output of its output and incremental input register 5 _1, the value is "0" + "5" = "5" Becomes Also, counter 6
₂ is incremented and its count value becomes "1". In this case, the value of the cyclic step register 8 is "2"
Therefore, the comparator 7 outputs a mismatch signal (here, a low-level signal). Therefore, the buffer pointer 9, the output "100" of the start address register 1 _2, adding a value "5" of the adder 2 ₂ "10
5 "is set.

Next, when the third memory access occurs, the data memory 4 is accessed at the address "105" already designated by the buffer pointer 9.

By this access, the start pointer 1
1 is the start address register 1 _TwoStart address
Since "2000" is specified as the
The dress “2000” is output. At this time, operation permission
Since there is no signal, adder 2_TwoAnd counter 6_TwoWorks
Without, both 2_Two, 6_TwoOutput is held as it is
, Adder 2_TwoIs "5" and the counter 6_TwoThe output of
It remains "1". Therefore, the addition for address generation
The output of the device 3 becomes “2005” and the buffer pointer 9
Is set to this value.

Next, when the fourth memory access occurs, the data memory 4 is accessed at the address “2005” already specified by the buffer pointer 9.

With this access, the start pointer 1
1, since specify "100" as the start address of the start address register 1 _2, the start address "100" is read. At this time, since the operation permission signal is out, the counter 6 _2, the count value is incremented is "2". In this case, since the value of the cyclic step register 8 is “2”, the comparator 7 outputs a match signal (here, a high-level signal).
The output of the adder 2 ₂ This coincidence signal is cleared becomes "0". Accordingly, the output of the address generation adder 3, the start address register 1 ₂ output "10
", The adder 2 ₂ values" 0 0 "value added" 10 ", and this value is set in the buffer pointer 9. At the same time, the counter 6 _second count value by a match signal from the comparator 7 Cleared to "0", that is, all return to the initial state.

Next, when the fifth memory access occurs, the data memory 4 is accessed at the address “100” already specified by the buffer pointer 9.

By repeating this, the data memory 1
4 is changed from “100” to “200”.
0 "→" 105 "→" 2005 "→" 100 "→" 20 "
00 ”→“ 105 ”→“ 2005 ”→“ 100 ”→..., And within a plurality of arbitrary distant address ranges
(In this example, “100 to 105” and “2000 to 200
It can be seen that the cyclic address is generated with the same increment (in the range of "5") (in this example, "5").

In the second embodiment, the description has been made on the assumption that N = 2. However, if N is 2 or more, it is arbitrary and the same effect can be obtained.

(Embodiment 3) FIG. 5 is a block diagram showing a configuration of a cyclic address generation circuit according to Embodiment 3 of the present invention, and the portions corresponding to the configuration of Embodiment 2 shown in FIG. Assign a sign.

[0065] In this embodiment 3, increment input register 5 ₂ is adapted to increment the address to be stored N number (which is equal to the number of the start address of the start address register 1 ₂₎ only in advance, start Pointer 1
When one of the N increment values is designated by 1, only the designated one increment value is read.

[0066] The operation permission signal is adapted to be applied only to the counter 6 _2, unlike the output timing Embodiment 2 of the operation permission signal, the number of access operations to the data memory 4, ( The data is output only when the value matches a value of +1) × n (where n is an integer) preset in the cyclic step register 8.

Further, in the third embodiment, the multiplier 12
And a flip-flop (DFF) 13.

[0068] The multiplier 12 is for multiplying the incremental input register 5 ₂ and the output of the counter 6 ₂ output, the multiplier 12 and the output of the start address register 1 ₂ and the output of the address generation adder 3 Are configured to be added.

The flip-flop 13 latches the output from the comparator 7 only when the data memory 4 is accessed. When the output Q of the flip-flop 13 goes high, this signal is input as a clear signal to the counter 6 _2.

The other structure is the same as that of the second embodiment shown in FIG.
In this case, the detailed description is omitted here.

Next, the operation of the configuration shown in FIG. 5 will be described with reference to the timing chart shown in FIG. Here, for ease of understanding, the start address register 1 _2, as a start address "10
0 "and" 2000 "are set (therefore, N =
2) Further, as previously increment the increment input address register 5 ₂ "5" and "10" is set (thus, N = 2),
Further, it is assumed that “1” is set in the cyclic step register 8. Therefore, the operation permission signal is output when the number of access operations is “2”, “4”, “6”, “8”,.

In the initial state, the start pointer 11
Is reset, also, the multiplier 12 and the counter 6 ₂
Is cleared and its value becomes “0”, and the flip-flop 1
Assume that the output Q of 3 is at a low level. At this time, in order to start pointer 11 is reset, the "100" as the start address from the start address register 1 _2, the increment input register 5 ₂ are respectively read "5". The counter 6 ₂ its output is reset is "0", the even outputs of the multipliers 12 "0". Therefore, the output of the address generation adder 3 is “100” + “0” = “100”, and this value is set in the buffer pointer 9.

Here, when the first memory access occurs, the data memory 4 is accessed at the address “100” already specified by the buffer pointer 9.

With this access, the start pointer 1
1, because it specifies the following "2000" as the start address of the start address register 1 _2, the start address "2000" is read out. At the same time, start pointer 11, so specify "10" as the incremental value of the increment input register 5 _2, the increment "10" is input to the multiplier 12 is output.

[0075] In this case, the operation permission signal is not yet not since the counter 6 ₂ operates out, since its output remains at "0", the output of the multiplier 12 is "10" × "0" = "0" is there. Therefore, the output of the address generation adder 3 is
“2000” + “0” = “2000”, and this value is set in the buffer pointer 9.

Here, when the second memory access occurs, the data memory 4 is accessed at the address “2000” already specified by the buffer pointer 9.

With this access, the start pointer 1
1, since specify "100" as the start address of the start address register 1 _2, the start address "100" is read. At the same time, start pointer 11, so specify "5" as the incremental value of the increment input register 5 _2, the increment "5" is output.

[0078] At this time, since the operation permission signal is output, the counter 6 _2, the count value is incremented in response to the memory access operation is "1". Therefore, the output of the multiplier 12 is “5” × “1” = “5”. Therefore, the output of the address generation adder 3, the multiplier output "100" of the start address register 1 ₂ 1
The result is “105” obtained by adding the output “5” of 2 and is set in the buffer pointer 9.

In this case, the cyclic step register 8
Is "1", the comparator 7 outputs a match signal (high-level signal in this case) and supplies it to the flip-flop 13. At this timing, the second memory access operation to the data memory 4 is performed. to the already terminated, it remains output Q does not change the low level of the flip-flop 13, therefore, the counter 6 ₂
Is not cleared and the output remains "1".

Therefore, the output of the multiplier 12 is "5"
× "1" = "5", since the output of the start address register 1 ₂ is "100", the buffer pointer 9,
By adding the value of both 1 _2, 12 "105" is set.

Next, when the third memory access occurs, the data memory 4 is accessed at the address “105” already specified by the buffer pointer 9.

With this access, the start pointer 1
1, because it specifies the "2000" as the start address of the start address register 1 _2, the start address "2000" is output. At the same time, start pointer 11, so specify "10" as the incremental value of the increment input register 5 _2, the increment "10" is input to the multiplier 12 is output. Furthermore, for latching the output of the flip-flop 13 is a comparator 7 by the memory access, but clear signal is input to a counter 6 _2, since operation permission signal in the time counter 6 ₂ is not input, the counter 6 ₂ does not operate, its output remains "1" without being cleared.

Therefore, the output of the multiplier 12 is "1"
0 ”ד 1 ”=“ 10 ”, start address register 1
_Since the output of No. ₂ is "2000", the output of the address generating adder 3 is "2010", and this value is set in the buffer pointer 9.

Next, when the fourth memory access occurs, the data memory 4 is accessed at the address “2010” already specified by the buffer pointer 9.

With this access, the start pointer 1
1, since specify "100" as the start address of the start address register 1 _2, the start address "100" is read. At the same time, start pointer 11, so specify "5" as the incremental value of the increment input register 5 _2, the increment "5" is input to the multiplier 12 is output. Furthermore, for latching the output of the flip-flop 13 is a comparator 7 by the memory access, but clear signal is input to a counter 6 _2, since operation permission signal in the time counter 6 ₂ is input, the counter 6 ₂ is its output is cleared to "0".

Therefore, the output of the multiplier 12 is "5"
× "0" = "0", since the output of the start address register 1 ₂ is "100", the output of the address generation adder 3 is "100", and this value is buffer pointer 9
Is set to That is, it returns to the initial state.

By repeating this, the data memory 4
Is changed from “100” to “2000”.
→ "105" → "2010" → "100" → "200"
0 ”→“ 105 ”→“ 2010 ”..., And an arbitrary plurality of address ranges in the memory space of the data memory 4 (in this example,“ 100 to 105 ”and“ 2000 to 2000 ”).
Each address range of “2010” can be sequentially accessed in a plurality of increments (“5” and “10” in this example).

In the third embodiment, the description has been made on the assumption that N = 2. However, if N is 2 or more, it is arbitrary and the same effect can be obtained.

[0089]

According to the present invention, the following effects can be obtained.

(1) According to the first aspect of the invention, it is possible to generate a cyclic address that can be accessed while adding a fixed increment in one address space.

(2) According to the second aspect of the present invention, it is possible to generate a cyclic address that can be accessed while adding a fixed increment to a plurality of address spaces.

(3) According to the third aspect of the present invention, it is possible to generate a cyclic address that can be accessed while adding an independent increment to each of a plurality of address spaces.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cyclic address generation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a cyclic address generation circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the circuit of FIG. 3;

FIG. 5 is a block diagram showing a configuration of a cyclic address generation circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the circuit of FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional cyclic address generation circuit.

FIG. 8 is an explanatory diagram of a cyclic address of a data memory area specified by the conventional circuit of FIG. 7;

[Explanation of symbols]

1 ₁ , 1 ₂ ... start address register, 2 ₁ , 2 ₂ ... adder, 3 ... adder for address generation, 4 ... data memory, 5
₁ , 5 ₂ ... increment input register, 6 ₁ , 6 ₂ ... counter, 7 ...
Comparator, 8: cyclic step register, 9: buffer pointer, 11: start pointer, 12: multiplier, 13 ...
flip flop.

Claims (3)

[Claims] 1. A circuit for generating a cyclic address for cyclically accessing a data memory in a part of its memory space, wherein a start address for setting a start address as a starting point of the cyclic address is provided. Setting means; increment setting means for setting an increment of an address until the cyclic address makes one cycle; access number setting means for setting the number of accesses to the data memory until the cyclic address makes one cycle; Each time it is accessed, the increments set by the increment setting means are sequentially integrated, the integrated value is added to the start address and output as a cyclic address,
And a computing means for clearing the integrated value when the number of accesses set by the access number setting means has been reached. 2. The cyclic address generating circuit according to claim 1, wherein said start address setting means is configured to be able to set a plurality of start addresses, and said arithmetic means is configured to set the start address for each start address. A cyclic address generation circuit configured to individually add integrated values. 3. The cyclic address generation circuit according to claim 2, wherein said increment setting means is configured to be able to set a plurality of increments, and said arithmetic means sets each increment set by said increment setting means. A cyclic address generation circuit configured to individually add each integrated value individually integrated to each start address.