JP2000013609A - Encoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a satisfactory device suitable for the storage, transmission, etc., of a digital image signal without accompanying the increase, etc., of a circuit scale by storing data which is obtd. by successively, simultaneously and parallelly coding processing of pixel data in each group while corresponding to an odd position and an even position as one file in a memory. SOLUTION: This device has an image buffer 12 constituting an image data dividing means, encoding processing parts 13A and 13B constituting an encoding processing means, an encoding buffer 14 constituting a coded data combining means and a memory controlling part 16. And, the device simultaneously and parallelly processes through different coding and processing routes according to whether an arrangement position on an image file of image data that becomes an object for coding processing is an odd number or an even number. And, mutual encoded data are associated with the initial arrangement position, are alternately arranged again to make them into the same file, are outputted to a memory and are stored there. Thus, it is possible to simplify address management of data on the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding apparatus for compressing image data, and more particularly to a good data coding apparatus used for storing and transmitting digital image signals and the like.

[0002]

2. Description of the Related Art A technique for speeding up encoding / decoding of image data and the like applied to a facsimile apparatus and the like will be described with reference to FIGS. FIG.
Shows a schematic configuration of a known encoding device,
FIG. 10 shows a division form of the image file in the memory.

As shown in FIG. 9, an encoding device 10 'includes an input arbitration unit 11, image buffers 12A and 12B,
Encoding processing units 13A, 13B, code buffers 14A, 1
4B, an output arbitration unit 15, and a memory control unit 16. First, as shown in FIG. 9, image data stored in a memory (not shown) is divided into a plurality of blocks A1, B1, A2,
B2,... Here, each block is stored at a discrete (different) address on the memory.

Next, the input arbitration unit 11 converts the image data read from the address on the memory into blocks A1,
(Hereinafter, referred to as group A) and blocks B1, B2,... (Hereinafter, referred to as group B) are assigned to paths for encoding processing. The image buffers 12A and 12B are constituted by, for example, FIFOs. Hold.

[0005] The encoding processing units 13A and 13B
The image data of each of the groups A and B is subjected to an encoding process according to a predetermined procedure, and the code buffers 14A and 14B are configured by, for example, FIFOs, like the image buffers 12A and 12B, and store the encoded data. Output arbitration unit 15
When a predetermined amount of code data is stored in each of the code buffers 14A and 14B, in order to write the code data to a predetermined address of the memory for each of the groups A and B, the output order of the data and the writing to the memory The position is controlled, and the memory control unit 16 generates a predetermined control signal for writing the code data to the memory.

According to the encoding apparatus 10 'having such a configuration, one image file is divided into a plurality of blocks (see FIG. 1).
0 is divided into two), and the divided image data can be subjected to encoding processing in parallel through separate encoding paths for each group, so that only one encoding path is provided and Has the advantage that the processing can be speeded up as compared with the case where the data is sequentially processed in series.

[0007]

In the above-mentioned conventional encoding apparatus, circuits having the same function (encoding processing paths 12A to 14A, 12B) are used to perform the encoding processing in parallel.
... 14B) are required, which causes a problem that the circuit scale is greatly increased. Further, two sets of image data stored at discrete addresses on the memory are read and subjected to an encoding process.
Since the set of image data (code data) is stored again at discrete addresses on the memory, there is a problem that the data management method becomes complicated.

An object of the present invention is to solve the above-mentioned problems and to provide a good coding apparatus applicable to accumulation and transmission of digital image signals without increasing the circuit scale and complicating data management. Aim.

[0009]

According to the present invention, in order to solve the above-mentioned problems, according to the first aspect of the present invention, horizontally continuous pixels constituting image data are converted into odd-numbered pixels in accordance with the arrangement order. Group, and image data dividing means for dividing into even-positioned pixel groups, encoding processing means for encoding the divided pixel groups in parallel through different paths having substantially the same compression ratio, The data encoded in parallel with each other, corresponding to the continuity of pixels in the image data,
And code data merging means for alternately arranging the same for each predetermined length and outputting the same as the same file.

According to a second aspect of the present invention, in the encoding device according to the first aspect, the encoding processing means uses a compression process based on predictive encoding and arithmetic encoding. Other than the pixels processed in parallel, a pixel located above the encoding target pixel or a pixel located on the left side of the encoding target pixel is selected as a reference pixel to form a template. .

According to a third aspect of the present invention, in the encoding apparatus according to the first or second aspect, a plurality of code data holding units each holding data coded in parallel by the coding processing unit. And code data selection means for selectively controlling the output of the data held by the code data holding means to the code data merging means.

Further, the invention according to claim 4 is the invention according to claim 3.
In the encoding device according to the present invention, a data output monitoring unit that monitors an output state of code data in the encoding processing unit, and a data input monitoring unit that monitors an input state of code data in the code data merging unit, When one of the code data output by the encoding processing means is insufficient compared to the other, the code data selecting means selects a specific code indicating the output insufficiency state and adds the specific code to the insufficient data. And output.

The invention described in claim 5 is the third invention.
In the encoding device according to the present invention, a data output monitoring unit that monitors an output state of code data in the encoding processing unit, and a data input monitoring unit that monitors an input state of code data in the code data merging unit, If one of the code data output by the encoding processing means is insufficient compared to the other, the code data selection means, select a specific code data to control the decoding process of the code data, It is characterized in that it is added to the missing data and output.

That is, according to the present invention, the image data is divided into an odd part and an even part by the image data dividing means at the time of encoding one symbol of the image data, that is, the image data to be compressed. The continuous pixels are divided into separate groups according to whether they are at odd-numbered positions and even-numbered positions, and pixel data for each group is sequentially and simultaneously and parallelly encoded by two sets of encoding processing means. The encoded data is stored in the memory as one file in association with the odd position and the even position by the code data merging means.

Therefore, since only two sets of encoding processing means are provided and other processing paths (configurations) can be shared, an increase in circuit scale can be suppressed, and
Since the pixel data and the code data are stored and managed at adjacent positions on the memory, the management of the image data can be simplified. Further, as an encoding process in the encoding processing means, the image data is divided into odd-numbered position and even-numbered position pixel groups in the horizontal direction, and prediction encoding and arithmetic encoding are performed using different templates for each pixel group. Therefore, the encoding process can be realized efficiently and with high accuracy.

Further, each code data output from the encoding processing means is temporarily held by the code data holding means, and the output timing of the held code data is controlled by the code data selection means, so that the code data is output. Can be sequentially selected and output one by one, so that the processing operations of the code data merging means can be synchronized, and the merging processing such as alternate arrangement of the code data and filing can be performed easily and favorably.

The output state of the encoded data and the retained amount are monitored by the encoded output monitoring means and the data holding amount monitoring means, and the output of either one of the encoded data from the two sets of encoding processing means is insufficient. Is detected, the code data merging unit can insert, fill, and output a specific code indicating the FILL state or code data for controlling the decoding process, instead of the insufficient code data. Synchronization of the code data merging processing operation can be achieved, and appropriate processing is executed in accordance with the specific code or code data added at the time of decoding the data, so that good image data can be transmitted.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An encoding apparatus according to an embodiment of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a schematic configuration diagram showing a first embodiment of the encoding apparatus of the present invention, and FIG. 2 is a schematic diagram showing image data to be subjected to encoding processing. Note that FIG.
Will be described with the same reference numerals.

Here, the encoding apparatus according to the present embodiment is applied to a system for predicting an encoding target pixel from a reference pixel and encoding the result by arithmetic encoding. That is, one pixel is predicted from the reference pixel, and the likelihood is parameterized as the appearance probability. This parameter varies depending on the nature of the image, and is initialized to a predetermined value at the beginning of encoding. In the course of the progress of the encoding process, it fluctuates in accordance with the distribution of the success or failure of prediction, thereby enabling prediction with higher probability. Then, a value obtained by an arithmetic operation using this parameter is used as a sign of the encoding process. Details will be described later.

First, the overall configuration will be described with reference to FIG. The encoding device of the present invention, as shown in FIG.
An image buffer 12 constituting image data dividing means, and encoding processing sections 13A and 13B constituting encoding processing means
And a code buffer 14 constituting code data merging means.
And a memory control unit 16.

(Image Buffer) Next, an image buffer applied to this embodiment will be described with reference to FIG.
As shown in FIG. 2, the image buffer 12
O, which is constituted by line memories LM1 to LM3 and shift registers SR1 to SR3.

The line memories LM1 to LM3 store data for three consecutive lines located at the top and bottom in line units. The shift registers SR1 to SR3 hold the pixels to be encoded and the generated reference pixels, and are provided corresponding to the line memories LM1 to LM3, respectively. The data transferred from each of them is sequentially held, and is shifted to the left, for example, by two bits in accordance with the end of the encoding processing of the unit pixel. Then, when the fixed-length data is shifted and input to the subsequent encoding processing unit, the next data is transferred from the line memories LM1 to LM3.

Next, data transferred from the image buffer 12 to the encoding processing units 13A and 13B will be described with reference to FIGS. Here, FIG. 3 is a schematic diagram illustrating image data to be subjected to the encoding process, and FIG. 4 is a diagram illustrating image data (Line1: B1 to B1) in a range indicated by a thick line in FIG.
2, Line2: A1 to A3, Line3: A1, B1), that is, only the reference pixels constituting the template used for the encoding process are extracted, and the pixels indicated by “?” The target pixel.

As shown in FIG. 3, the image buffer 12
Image data A1 to A4, B for three lines Line1 to Line3
1 to B4, and horizontal direction A1, B from the left end of Line1
1, A2, B2, ..., from Line 1 to the lower Li
Data is sequentially read out to ne3 and updated. Image data X1 to X10 in the range shown in FIG. 4A, that is, image data located at odd-numbered positions counted from the left end, are transferred from the image buffer 12 to the encoding processing unit 13A, and the transferred image data is referred to. Then, the pixel indicated by “?” Is coded using the technique of predictive coding and arithmetic coding.

Similarly, the image data X1 in the range shown in FIG.
To X9, that is, the image data located at the even-numbered position counted from the left end is transferred, and the pixels indicated by “?” Are encoded with reference to the transferred image data. In this way, as shown in FIG. 3, the image data is read out from left to right of each line and sequentially from top to bottom in line units, and each code is read through the image buffer 12. Conversion unit 1
Image data at odd-numbered positions (A) and even-numbered positions (B) are individually transferred to 3A and 13B.

(Encoding unit) Next, the encoding unit 13
The encoding process in A and 13B will be described with reference to FIG. As shown in FIG. 1, the encoding processing unit 13A,
13B have the same image compression processing function, and the image buffer 12B is capable of performing processing operations simultaneously and in parallel.
Are provided in parallel for the image data from.

Then, as described above, the image buffer 1
2 are transferred to the encoding processing units A and B, respectively, as reference pixels, that is, templates (FIGS. 4A and 4B), and the encoding process is performed using the templates. One pixel indicated by the target "?" Is predicted, the result is sequentially processed by arithmetic operation, and the result is used as a code.

That is, in the encoding process of the image data at the odd-numbered position, as shown in FIG.
In the encoding process of the image data at the even-numbered position using the template using X10, as shown in FIG. 4 (b), as shown in FIG. Reference pixels X1 to X9 excluding pixel X10)
Use a template with.

Here, the image data "?" At the odd-numbered position and the image data "?" At the even-numbered position need to be processed simultaneously in the encoding process and the decoding process. Therefore, when processing the image data at the even-numbered position, if the immediately preceding pixel (pixel to be processed, which corresponds to pixel X10 in FIG. 4A) is used, simultaneous processing is performed at the time of decoding processing. It becomes impossible.

The image data encoded using the above-described template is output as code data to the code buffer 14 at the subsequent stage. Note that the template is a geometric pattern indicating the positions of the pixels related to the pixel “?” To be encoded, and the pixels indicated by X1 to X10 indicate normal pixels in the template.
The pixels in the template are combined to form a context value. For example, when the number of pixels in the template is 10 as shown in FIG. 4A, 2 ¹⁰ = 1024 different context values are obtained.

(Code Buffer) Next, the encoding processing unit 13
The code data output from A and 13B and the code buffer 14 will be described with reference to FIG. As described above, the encoding process of the image data performed by the encoding processing units 13A and 13B is a compression process, and a considerable amount of image data is usually converted into a smaller amount of code data.

As shown in FIG. 5A, when the code data groups 13a and 13b are input to the code buffer 14 in units of bytes from the coding processing units 13A and 13B, respectively, as shown in FIG. As shown, the code data group 13a,
13b, one byte of which output timing is synchronized is combined as one set and stored in the same position of the code buffer 14.

Here, the code buffer is configured by, for example, a FIFO for temporarily storing code data. As described above, the code data groups 13a and 13b output from the encoding processing units 13A and 13B are stored in the code buffer 1
4, the data is merged so as to be alternately arranged for each sample, that is, for each byte, and stored at a predetermined address of the memory according to a control signal generated by the memory control unit 16. Note that the memory control unit 16 has the same configuration as that of the related art, and a description thereof will be omitted.

According to the present invention having the above-described configuration, the arrangement position of the image data to be encoded on the image file is odd or even depending on whether the arrangement position is an odd or even number. Simultaneously processed in parallel through different encoding processing paths, the encoded data are made to correspond to the initial arrangement position, and are alternately arranged again to be the same file, output to the memory, and stored. Address management of data on the memory can be simplified.
Further, according to such a data arranging method, it is possible to simplify the management of the address from which the code data is read at the time of the decoding process.

In the present embodiment, there has been shown a case where there is no difference in the amount of codes generated independently by the encoding processing units 13A and 13B during the encoding process. That is, the pixel data (odd-position data and even-position data) processed in the above-described encoding processing units 13A and 13B simultaneously and in parallel are adjacent pixels in the same file, and there is almost no difference due to the nature of the image. Since there is no code data, there is almost no difference in the amount of generated code data.

Therefore, a timing chart of the merging process of the code data in the code buffer of the present embodiment is shown in FIG. That is, as shown in FIG. 6, at each of the predetermined timing periods T1, T2, T3,..., A predetermined data length (a difference in the number of code data is within a certain number) from each of the encoding processing units 13A and 13B. ), The code data is output, so that the code buffer 14 corresponds to the continuity of the arrangement position in the original image file (odd-numbered-even-odd-number...). Thus, the respective code data are alternately arranged and output in units of 1 bit, and the respective code data are stored in adjacent addresses on the memory.

(Second Embodiment) Next, a second embodiment of the encoding apparatus according to the present invention will be described with reference to FIGS. This embodiment is different from the above-described first embodiment when the output amount of the code data from the coding processing units 13A and 13B has a difference of a certain number or more, that is, the type of the image data is unique. A large difference occurs in the output amount of code data. "
It is characterized in that it has a configuration for synchronizing the code data merging processing when it is in the “asynchronous state”.

As shown in FIG. 7, the encoding apparatus according to the present embodiment includes code number counters 21A and 21B constituting data output monitoring means between the encoding processing units 13A and 13B and the code buffer 14. It has buffers 22A and 22B constituting code data holding means, a selector 23 constituting code data selection means, and a code data selection control section 24 constituting data input monitoring means. The other configuration is the same as that of the first embodiment, and the description thereof is omitted.

The code number counters 21A and 21B individually count the number of code data output from each of the coding processing units 13A and 13B, and output the code data selection control unit 24 described later. Each of the buffers 22A and 22B is a fixed-length shift register that temporarily stores code data output from each of the coding processing units 13A and 13B.

The selector 23 controls the buffer 22 based on an instruction from a code data selection / selection control unit 24, which will be described later.
A, 22B, and specific code data 22C set in advance as data meaning specific processing contents (or a specific code set as a code indicating a storage state of specific data) And outputs it to the code buffer 14 at the subsequent stage.

The code data selection control unit 24 controls the code number counters 21A and 21B during the coding processing period of a predetermined amount of image data in the coding processing units 13A and 13B.
The number actually counted as the output of the code data is compared, and a selection signal for setting which of the code data held in the buffers 22A and 22B and the specific code data 22C is output to the code buffer is output to the selector 23. I do.

At the same time, the input state of the code data and the like to the code buffer 14 is monitored, and upon completion of the merging process of the predetermined amount of code data, the count values of the code number counters 21A and 21B are reset to set the next code. Count the number of data groups. Next, an encoding process in the encoding device according to the present embodiment will be described with reference to FIGS.

First, as in the first embodiment, when the number of code data output from the encoding processing units 13A and 13B is within a predetermined fixed number, the above-described FIG.
As shown in the timing chart of FIG.
Code data groups 13a and 13b are selected from 2A and 22B,
The code data group 13
Each code data is alternately arranged in the order of a → 13b → 13a →... and output to the memory.

On the other hand, if the difference between the number of code data output from the coding processing units 13A and 13B exceeds a preset fixed number or more, the specific code data is selected and becomes insufficient due to the code buffer. The data is combined and added to the data length and output to the memory. The details will be described below. As shown in the timing chart of FIG. 8, when the encoding processing units 13A and 13B complete the encoding processing of a predetermined amount of image data, the actual output amount of encoded data is counted by the code number counters 21A and 21B. And
When only the code data group 13a from the encoding processing unit 13A is counted and the code data group 13b from the encoding processing unit 13B is not output (timing T1, T2, T3), the code data selection control unit 24 sets the selector 23 is switched to "F" which is the specific code data 22C in place of the code data group 13b in which the output amount of the code data is insufficient.
F 08 ”is selected and output to the code buffer 14.

The code buffer 14 stores each of the code data “13” and “4B” having the insufficient data length and the specific code data “FF 08” into the code data group 13a → specific code data 22C → 13a → 22C.・ ・ Alternatively arrange in the order of and output to memory.

Here, the specific code data or the specific code is predetermined in the encoding processing side and the decoding processing side so as to have a predetermined meaning, processing content, and the like. When the data “FF” is treated as a code by image compression, it is distinguished by adding “00” specially. In the case of a code other than “00”, the code is treated as an escape code. For example, “FF 08” has a specific meaning as indicating skip processing.

According to such a configuration, the encoding processing unit 1
The code data output from 3A and 13B is stored in a buffer 22.
A shortage of the data length of the code data to be merged in the code buffer 14, that is, an “asynchronous state” can be detected by monitoring the amount of output code data while temporarily holding the data by A and 22B. Therefore, the selector 23 is switched by the code data selection control unit 24, and specific code data or a specific code is inserted into a shortage of data, thereby synchronizing data merging processing in the code buffer.

Therefore, the encoding process of the image data can be speeded up with a simple circuit configuration and the management of the encoded data on the memory can be simplified. The system can be easily configured with a minimum number of additional components by mixing with a standardized coding method.

[0049]

As described above, according to the encoding apparatus of the present invention, when encoding one symbol of image data by the image data dividing means, the image data is divided into odd and even parts. Division, that is, division into separate groups according to whether continuous pixels of image data to be compressed are at odd-numbered positions and even-numbered positions, respectively, and two sets of encoding processing means are used to divide pixel data for each group. Sequentially
Simultaneous and parallel coding processing is performed, and the coded data is stored in the memory as one file in association with the odd position and the even position by the code data merging means, thereby suppressing an increase in circuit scale. In addition, it is possible to reduce the time required for the encoding process, and to realize an encoding device that simplifies the management of image data because pixel data and encoded data are stored and managed at adjacent positions on a memory. Can be.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a first embodiment of an encoding device according to the present invention.

FIG. 2 is a conceptual diagram illustrating data processing in an image buffer according to the present embodiment.

FIG. 3 is a schematic diagram showing image data to be subjected to an encoding process.

FIG. 4 is a schematic diagram showing reference pixels used for encoding processing.

FIG. 5 is a conceptual diagram illustrating data processing in a code buffer according to the present embodiment.

FIG. 6 is a timing chart (No. 1) showing a process of merging code data.

FIG. 7 is a schematic configuration diagram showing a second embodiment in the encoding device of the present invention.

FIG. 8 is a timing chart (No. 2) illustrating a process of merging code data.

FIG. 9 is a diagram showing a schematic configuration of a known encoding device.

FIG. 10 is a schematic diagram showing a division mode of an image file.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input control part 12, 12A, 12B Image buffer 13A, 13B Encoding processing part 13a, 13b Code data group 14, 14A, 14B Code buffer 15 Output adjustment part 16 Memory control part 21A, 21B Code number counter 22A, 22B buffer 22C Specific code data 23 Selector 24 Code data selection control unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tsuyoshi Mizuta 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (Reference) 5B057 CA16 CB18 CG03 CG07 CH04 CH11 CH18 5C059 KK13 MA01 ME11 RC07 RC09 UA02 UA05 5C078 BA21 BA32 BA35 CA31 CA36 DA01 DB11

Claims (5)

[Claims] An image data dividing means for dividing horizontally continuous pixels constituting image data into a pixel group at an odd position and a pixel group at an even position according to an arrangement order; Encoding processing means for encoding a group of pixels in parallel through different paths having substantially the same compression ratio, and the data encoded in parallel in correspondence with the continuity of pixels in the image data. And a code data merging unit that is arranged alternately for each predetermined length and outputs the same file. 2. The coding processing means uses a compression process based on predictive coding and arithmetic coding, and performs a process other than the pixels processed in parallel during the coding.
2. The encoding device according to claim 1, wherein a pixel located above the encoding target pixel or a pixel located on the left side of the encoding target pixel is selected as a reference pixel to form a template. 3. A plurality of code data holding units each holding data encoded in parallel by said encoding processing unit, and a plurality of code data holding units for each of the data held in said code data holding unit. 3. A code data selection means for selectively controlling an output.
An encoding device according to claim 1. 4. A data output monitoring means for monitoring an output state of code data in said encoding processing means, and a data input monitoring means for monitoring an input state of code data in said code data merging means, If one of the code data output by the conversion processing means is insufficient compared to the other, the code data selecting means selects a specific code indicating the output insufficiency state and adds it to the insufficient data. 4. The encoding device according to claim 3, wherein the encoding device outputs. 5. A data output monitoring means for monitoring an output state of code data in said encoding processing means, and a data input monitoring means for monitoring an input state of code data in said code data merging means, When one of the code data output by the decoding processing means is insufficient compared with the other, the code data selecting means selects a specific code data controlling a decoding process of the code data, and 4. The encoding device according to claim 3, wherein the encoding device outputs the data in addition to the data.