JP2000013457A - Clock phase detector and clock phase detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a correct phase error even when a point on an axis is fluctuated by a noise or the like. SOLUTION: This device is provided with absolute value detecting parts 6a and 6b for detecting the absolute values of two signals detected by signal point sample detecting parts 3a and 3b and absolute value discriminating parts 7a and 7b for comparing the absolute values detected by the absolute value detecting parts 6a and 6b with a predetermined reference value. Then, the compared results at the absolute value discriminating parts 7a and 7b and values outputted from multipliers 5a and 5b are inputted to AND gates 8a and 8b and only when the absolute values detected by the absolute value detecting parts 6a and 6b are larger than the reference value, the value outputted from the multiplier 5a is outputted through the AND gates 8a and 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase detector and a clock phase detection method, and more particularly, to a clock phase detector and a clock phase detection method for detecting a clock phase of a phase shift modulated signal.

[0002]

2. Description of the Related Art Conventionally, in the transfer of digital data, phase shift modulation (Phase Shift Modulation) in which the phase of each data is transferred based on the value of the data and the transfer is performed.
Keying (PSK) method.

In the phase shift keying method, data to be transferred is mapped as a value having a predetermined phase on a coordinate of a complex plane having an I axis and a Q axis according to the value, and the data of the Ich and the Qch are mapped. The data is orthogonally modulated and transferred.

[0004] The transferred data is orthogonally demodulated into Ich and Qch data, and is recognized as digital data based on the values.

[0005] Here, at the data transfer destination, if the data is not recognized at an accurate timing, it is recognized as data having an incorrect phase.

Therefore, at the data transfer destination, the phase error is corrected by correcting the point (hereinafter, referred to as the zero cross point) at which the orthogonally demodulated Ich and Qch data becomes "0" (hereinafter, referred to as "zero cross point"). Data can be recognized at the timing, and a clock phase detector is provided to detect a shift amount of a zero cross point serving as phase error information.

FIG. 2 is a block diagram showing a configuration example of a conventional clock phase detector.

In this conventional example, as shown in FIG. 2, a quadrature demodulated Ich or Qch signal is input, and a sampling circuit 1 for sampling the signal at twice or more the modulation speed is provided.
The signal point sample code detection unit 3 that detects the code of the signal sampled by the sample circuit 1 is compared with the code of two consecutive signals detected by the signal point sample code detection unit 3, and the comparison is performed. A sample code comparing section 4 for outputting the result, a zero-crossing point sample detecting section 2 for detecting a signal value at a central sampling timing of two signals whose codes are compared by the sample code comparing section 4, A multiplier 5 is configured to multiply the comparison result in the comparator 4 by the value detected by the zero-cross sample detector 2 and output the result.

The operation of the clock phase detector configured as described above will be described below.

When the Ich or Qch signal is sampled by the sample circuit 1, the signal point sample code detection section 3 detects the code of the signal sampled by the sample circuit 1.

Next, in the preceding and succeeding sample code comparing section 4, the codes of two consecutive signals among the codes detected by the signal point sample code detecting section 3 are compared. "0", "-1" when the sign of the previous signal is positive and the sign of the subsequent signal is negative, and "1" when the sign of the previous signal is negative and the sign of the subsequent signal is positive. Output as a result.

In the zero-cross sample detecting section 2, the sign is compared by the sign comparing section 4 before and after the sample.
The signal value at the center sampling timing of the two signals is detected.

Thereafter, the multiplier 5 multiplies the comparison result of the preceding and succeeding sample code comparison section 4 by the value detected by the zero-cross sample detection section 2 and outputs the multiplication result as phase error information.

Here, if the signs of the two signals compared by the preceding and following sample sign comparing section 4 are different from each other, the value detected by the zero-cross sample detecting section 2 is used as it is or the sign is inverted and the phase error information is obtained. However, if the signs of the two signals compared by the preceding and succeeding sample code comparing unit 4 are the same, “0” is output from the preceding and succeeding sample code comparing unit 4 as a comparison result. The value detected by the unit 2 does not make sense as the phase error information.

When the phase error information is output from the clock phase detector, the zero cross point is corrected based on the output phase error information.

By the above-described series of operations, data can be recognized at an accurate timing at the data transfer destination.

[0017]

Generally, a signal subjected to quadrature demodulation has some fluctuation due to the influence of noise or the like.

Therefore, when at least one of the two signals whose signs are compared by the preceding and succeeding sample sign comparing units is positive or negative despite the fact that it is a point on the axis, If the signal at the signal point is close to the axis, the phase detection should not be performed because the signal does not pass through the middle point on the axis between the signal points.

However, in this case, if the sign of the signal at the preceding signal point is different from the sign of the signal at the succeeding signal point, the conventional clock phase detector as described above uses the central sampling of those signals. There is a problem that the signal value at the timing is determined as the signal value at the zero crossing point, and the signal value is output as phase error information, so that a correct phase error cannot be detected.

FIG. 3 is a diagram for explaining a problem in the clock phase detector shown in FIG. 2, and shows an eye pattern of a quadrature-modulated signal.

In FIG. 3, when the signal at the point C changes to the positive side, the central value of the transition from the point C to the point d or the point e is determined to be the zero cross point.

Similarly, when the signal at the point C changes to the negative side, the transition from the point C to the point a or b, and when the signal at the point c changes to the positive side, the point changes from the point D or E to the point c. Transition, c
If the point fluctuates to the negative side, the signal value at the center sampling timing of the transition from point A or point B to point c is determined to be the signal point at the zero crossing point.

The present invention has been made in view of the above-described problems of the conventional technology, and can detect a correct phase error even when a point on an axis fluctuates due to noise or the like. It is an object to provide a clock phase detector and a clock phase detection method.

[0024]

In order to achieve the above object, the present invention provides a sampling means for sampling a quadrature demodulated signal, and detecting two consecutive signals among the signals sampled by the sampling means. Signal point detecting means, a sign comparing means for comparing signs of two signals detected by the signal point detecting means, and a signal at a central sampling timing of the two signals detected by the signal point detecting means. A signal value at a central sampling timing detected by the zero-cross point detecting means only when the signs of the two signals are different from each other in the comparison result by the sign comparing means; A clock phase detector that has first output control means and outputs error information of the clock phase of the quadrature demodulated signal. An absolute value detecting means for detecting the absolute values of the two signals detected by the signal point detecting means; and comparing the absolute value detected by the absolute value detecting means with a predetermined reference value. An absolute value determining means, and a second output control means for outputting a value output from the first output control means only when the absolute value detected by the absolute value detecting means is larger than the reference value. It is characterized by having.

The signal point detecting means, the sign comparing means, the zero-cross point detecting means, the first output control means, the absolute value detecting means, the absolute value judging means and the second output controlling means are respectively provided for an I channel and a Q channel. And adding means for adding a value output from the second output control means of the I channel and a value output from the second output control means of the Q channel and outputting the result. It is characterized by.

Also, a third output control for outputting the signal added by the adding means only when the signs of the two signals are different from each other in the comparison results of the sign comparing means for both the I channel and the Q channel. Means.

Further, the second output control means receives the value output from the first output control means at one input terminal and receives the comparison result of the absolute value determination means at the other input terminal. And a logical product gate for calculating a logical product of a value output from the first output control means and a comparison result of the absolute value determining means.

Also, the quadrature demodulated signal is sampled, two consecutive signals among the sampled signals and the center value of the two signals are detected, and only when the signs of the two signals are different from each other, In a clock phase detecting method for outputting a center value as phase error information, an absolute value of the two signals is detected, and the phase error information is output only when the detected absolute value is larger than a predetermined reference value. It is characterized by doing.

Further, the quadrature demodulated signal is sampled in each of the I channel and the Q channel.
Detecting the signal value at the center sampling timing of the two signals, detecting the absolute value of the two signals,
The phase error information is output only when the two signals have different signs and the detected absolute value is larger than a predetermined reference value.

Further, the present invention is characterized in that the phase error information output from each of the I channel and the Q channel is added and output.

Only when the signs of the two signals are different from each other in both the I channel and the Q channel,
The added phase error information is output.

(Operation) In the present invention configured as described above, only when the absolute value of a signal detected as a sample is larger than a predetermined reference value, the two signals having different signs have different signal values. The signal value at the sampling timing at the center of is output as phase error information, so even if a point on the axis fluctuates due to noise or the like, that point is not used for detecting a zero-cross point, and the correct phase error Is detected.

Further, since the detection of the zero cross point is performed on both the I channel and the Q channel, the number of detection points is increased, and more precise detection is performed.

Further, phase error information is output only when the signs of two consecutive signals are different from each other in both the I channel and the Q channel, that is, only when a zero-cross point is detected. Is detected.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the clock phase detector of the present invention.

In this embodiment, as shown in FIG. 1, a quadrature demodulated Ich signal is input, and a sampling circuit 1a that samples the Ich signal at twice or more the modulation speed, and a signal circuit sampled by the sampling circuit 1a. A signal point sample detector 3a for detecting two consecutive signals and a preceding and succeeding sample code comparator 4a for comparing the signs of the two signals detected by the signal point sample detector 3a and outputting the comparison result.
A zero-crossing point sample detecting section 2a for detecting a signal value at the center sampling timing of two signals detected by the signal point sample detecting section 3a; a comparison result of the preceding and succeeding sample code comparing sections 4a; The first to multiply and output the value detected by
, An absolute value detector 6a for detecting the absolute value of the signal detected by the signal point sample detector 3a, and an absolute value detected by the absolute value detector 6a. An absolute value determining unit for comparing the determined reference value and outputting a comparison result; and a second output control unit for calculating a logical product of the multiplication result in the multiplier and the comparison result in the absolute value determining unit a , An AND gate 8a, a quadrature-demodulated Qch signal, and a sampling circuit 1b for sampling them at twice or more the modulation speed, and a continuous two signals among the signals sampled by the sampling circuit 1b. A signal point sample detector 3b to be detected;
The sign of the two signals detected by the signal point sample detection unit 3b is compared, the preceding and following sample code comparison unit 4b that outputs the comparison result, and the center of the two signals detected by the signal point sample detection unit 3b. A zero-cross point sample detector 2b for detecting a signal value at the sampling timing, and first output control means for multiplying the comparison result in the preceding and succeeding sample code comparator 4b by the value detected by the zero-cross sample detector 2b and outputting the result. A certain multiplier 5b, an absolute value detector 6b for detecting the absolute value of the signal detected by the signal point sample detector 3b, and an absolute value detected by the absolute value detector 6b and a predetermined reference value And an absolute value determination unit 7b that outputs a comparison result, and a second product that calculates a logical product of the multiplication result in the multiplier 5b and the comparison result in the absolute value determination unit 7b. AND gate 8b is a force control means
AND gate 9 serving as third output control means for calculating the logical product of the comparison result of the preceding and succeeding sample code comparing unit 4a and the comparison result of the preceding and following sample code comparing unit 4b
And an adder 10 that adds and outputs the logical product calculated by the AND gate 8a and the logical product calculated by the AND gate 8b, and the logical product calculated by the AND gate 9 and the adder 10. And an AND gate 11 which is a third output control means for calculating and outputting a logical product with the addition result.

Hereinafter, the operation of the clock phase detection circuit configured as described above will be described.

When the Ich signal is sampled by the sample circuit 1a, the signal point sample detector 3a
Two consecutive signals among the signals sampled by the sample circuit 1a are detected.

Next, in the preceding and succeeding sample code comparing section 4a, the signs of the two signals detected by the signal point sample detecting section 3a are compared. When the two signs are the same, "0" is set. When the sign is positive and the sign of the subsequent signal is negative, “−1” is output as the comparison result, and when the sign of the previous signal is negative and the sign of the subsequent signal is positive, “1” is output as the comparison result.

In the zero-cross sample detecting section 2a, a signal value at the center sampling timing of the two signals detected by the signal point sample detecting section 3a is detected.

Next, in the multiplier 5a, the comparison result in the preceding and succeeding sample code comparing section 4a is multiplied by the value detected in the zero cross sample detecting section 2a, and the multiplied result is input to the AND gate 8a.

If the signs of the two signals detected by the signal point sample detector 3a are different from each other, the value detected by the zero-cross sample detector 2a is used as it is or the sign is inverted and the AND gate 8a However, if the signs of the two signals detected by the signal point sample detection unit 3a are the same, the preceding and following sample code comparison units 4a
Is output as the comparison result, the value detected by the zero-cross sample detection unit 2a is not output from the AND gate 8a.

The absolute value detector 6a detects the absolute value of the signal detected by the signal point sample detector 3a.

When the absolute value is detected by the absolute value detecting section 6a, the absolute value judging section 7a compares a predetermined reference value with the absolute value detected by the absolute value detecting section 6a. “1” is set when the absolute value detected by the value detector 6a is larger than the reference value, and “0” is set when the absolute value detected by the absolute value detector 6a is equal to or smaller than the reference value. Output as a comparison result.

Thereafter, in the AND gate 8a, the logical product of the multiplication result in the multiplier 5a and the comparison result in the absolute value judging section 7a is calculated, and the calculation result is input to the adder 10.

Here, in the AND gate 8a, if the absolute value detected by the absolute value detector 6a is larger than the reference value in the comparison result in the absolute value determiner 7a, the multiplication result in the multiplier 5a is output. However, if the absolute value detected by the absolute value detection unit 6a is equal to or smaller than the reference value, the result of the multiplication in the multiplier 5a may be that "0" is output as the determination result from the absolute value determination unit 7a. Is not output.

Thus, when the signal at the signal point is near the axis, the signal is not used for phase error detection.

On the other hand, when the Qch signal is sampled by the sample circuit 1b, the signal point sample detector 3b detects two consecutive signals among the signals sampled by the sample circuit 1b.

Next, in the preceding and following sample code comparing section 4b, the signs of the two signals detected by the signal point sample detecting section 3b are compared. If the two signs are the same, "0" is set. When the sign is positive and the sign of the subsequent signal is negative, “−1” is output as the comparison result, and when the sign of the previous signal is negative and the sign of the subsequent signal is positive, “1” is output as the comparison result.

The zero-cross sample detector 2b detects the center value of the two signals detected by the signal point sample detector 3b.

Next, the multiplier 5b multiplies the comparison result of the preceding and succeeding sample code comparison section 4b by the value detected by the zero-cross sample detection section 2b, and inputs the multiplication result to the AND gate 8b.

If the signs of the two signals detected by the signal point sample detector 3b are different from each other, the value detected by the zero-cross sample detector 2b is used as it is or the sign is inverted and the AND gate 8b However, if the signs of the two signals detected by the signal point sample detection section 3b are the same, the preceding and following sample code comparison sections 4b
Is output as the comparison result, the value detected by the zero-cross sample detector 2b is not output from the AND gate 8b.

The absolute value detector 6b detects the absolute value of the signal detected by the signal point sample detector 3b.

When the absolute value is detected by the absolute value detecting section 6b, the absolute value judging section 7b compares a predetermined reference value with the absolute value detected by the absolute value detecting section 6b. “1” is set when the absolute value detected by the value detector 6b is larger than the reference value, and “0” is set when the absolute value detected by the absolute value detector 6b is equal to or smaller than the reference value. Output as a comparison result.

Thereafter, in the AND gate 8b, the logical product of the multiplication result in the multiplier 5b and the comparison result in the absolute value judging section 7b is calculated, and the calculation result is input to the adder 10.

Here, in the AND gate 8b, if the absolute value detected by the absolute value detector 6b is larger than the reference value in the comparison result in the absolute value determiner 7b, the multiplication result in the multiplier 5b is output. However, if the absolute value detected by the absolute value detector 6b is equal to or smaller than the reference value, "0" is output as the determination result from the absolute value determiner 7b, and the multiplication result in the multiplier 5b is No output.

The comparison results in the preceding and succeeding sample code comparison units 4a and 4b are input to the multipliers 5a and 5b and also to the AND gate 9, where the comparison result in the multiplier 5a and the multiplier 5b are input. Is calculated with the comparison result in.

That is, from the AND gate 9, the signs of the two Ich signals detected by the signal point sample detector 3a are different from each other and the signal point sample detector 3b
"1" is output only when the signs of the two Qch signals detected at are different from each other, and "0" is output in other cases.

The logical product calculated by the AND gate 8a and the logical product calculated by the AND gate 8b are input to the adder 10, where the logical product calculated by the AND gate 8a is calculated. And the logical product calculated by the AND gate 8b are added.

Thereafter, the logical product calculated by the AND gate 9 and the addition result by the adder 10 are added to the AND gate 1
1 and the AND gate 11 calculates the logical product of the logical product calculated by the AND gate 9 and the addition result in the adder 10, and outputs the calculation result as phase error information.

When the phase error information is output from the clock phase detector, the zero-cross point is corrected based on the output phase error information.

As described above, in this embodiment, Ic
In each of h and Qch, only when the absolute value of a signal detected as a sample is larger than a predetermined reference value, the center value of two signals having different signs is output. Even if the upper point fluctuates, that point is not used for detecting the zero cross point.

Further, since the detection of the zero-cross point is performed in both Ich and Qch, the number of detection points is increased, and more precise detection is performed.

Furthermore, phase error information is output only when a zero-cross point is detected in both Ich and Qch, so that the phase error can be detected more accurately.

By the above-described series of operations, data can be recognized at an accurate timing at the data transfer destination.

[0067]

Since the present invention is configured as described above, it has the following effects.

According to the first and fifth aspects, only when the absolute value of a signal detected as a sample is larger than a predetermined reference value, the central value of two signals having different signs is changed. Since it is output as phase error information, even when a point on the axis fluctuates due to noise or the like, the point is not used for detecting a zero-cross point, and a correct phase error can be detected.

In the second, sixth and seventh aspects, the zero-cross point is detected on both the I channel and the Q channel, and the respective errors are added, so that the gain of the error is increased. be able to.

According to the third and eighth aspects, the I
Channel 2 and Q channel 2
Only when the signs of the two signals are different from each other, that is, when the zero-cross point is detected, the phase error information is output, so that the phase error can be detected more accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a clock phase detector of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a conventional clock phase detector.

FIG. 3 is a diagram for explaining a problem in the clock phase detector shown in FIG. 2;

[Explanation of symbols]

 1a, 1b Sample circuits 2a, 2b Zero-cross point sample detectors 3a, 3b Signal point sample detectors 4a, 4b Sample code comparison units before and after 5a, 5b Multipliers 6a, 6b Absolute value detectors 7a, 7b Absolute value determiners 8a, 8b, 9, 11 AND gate 10 Adder

Claims (8)

[Claims] 1. Sampling means for sampling a quadrature demodulated signal, signal point detecting means for detecting two consecutive signals among the signals sampled by the sampling means, and detecting by the signal point detecting means. Code comparison means for comparing the signs of the two signals obtained, zero-cross point detection means for detecting a signal value at the central sampling timing of the two signals detected by the signal point detection means,
First output control means for outputting a signal value at a central sampling timing detected by the zero-crossing point detection means only when the signs of the two signals are different from each other in the comparison result of the sign comparison means. A clock phase detector for outputting error information of a clock phase of a quadrature-demodulated signal; an absolute value detecting means for detecting absolute values of two signals detected by the signal point detecting means; Means for comparing an absolute value detected by the means with a predetermined reference value; and the first value only when the absolute value detected by the absolute value detecting means is larger than the reference value. A second output control means for outputting a value output from the output control means. 2. The clock phase detector according to claim 1, wherein said signal point detecting means, sign comparing means, zero crossing point detecting means, first output control means, absolute value detecting means, absolute value determining means and 2 output control means for each of the I channel and the Q channel. Further, a value output from the second output control means for the I channel and a value output from the second output control means for the Q channel A clock phase detector comprising an adding means for adding and outputting 3. The clock phase detector according to claim 2, wherein the adding means only performs the operation when the signs of the two signals are different from each other in the comparison result of the sign comparing means for both the I channel and the Q channel. And a third output control means for outputting the added signal. 4. The clock phase detector according to claim 1, wherein said second output control means has one input terminal connected to said first output terminal.
The value output from the output control means is input, the comparison result of the absolute value determination means is input to the other input terminal, and the value output from the first output control means is compared with the absolute value determination means. A clock phase detector, which is a logical product gate for calculating a logical product with a result. 5. A quadrature demodulated signal is sampled,
Two consecutive signals among the sampled signals and a central value of the two signals are detected, and only when the signs of the two signals are different from each other, a signal value at the central sampling timing is output as phase error information. A clock phase detection method, comprising: detecting an absolute value of the two signals; and outputting the phase error information only when the detected absolute value is larger than a predetermined reference value. . 6. The clock phase detecting method according to claim 5, wherein quadrature demodulated signals are sampled in each of an I channel and a Q channel, and two consecutive signals among the sampled signals are output. The signal value at the sampling timing at the center of the two signals is detected.
Detecting the absolute values of the two signals, and outputting the phase error information only when the signs of the two signals are different from each other and the detected absolute value is larger than a predetermined reference value. Clock phase detection method. 7. The clock phase detection method according to claim 6, wherein the phase error information output from each of the I channel and the Q channel is added and output. 8. The clock phase detecting method according to claim 7, wherein the added phase error information is output only when the signs of the two signals are different from each other in both the I channel and the Q channel. Clock phase detection method.