JP2000013190A - Matching circuit automatic adjusting device for receiver - Google Patents

Matching circuit automatic adjusting device for receiver

Info

Publication number
JP2000013190A
JP2000013190A JP10173089A JP17308998A JP2000013190A JP 2000013190 A JP2000013190 A JP 2000013190A JP 10173089 A JP10173089 A JP 10173089A JP 17308998 A JP17308998 A JP 17308998A JP 2000013190 A JP2000013190 A JP 2000013190A
Authority
JP
Japan
Prior art keywords
control voltage
matching circuit
rssi
receiver
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10173089A
Other languages
Japanese (ja)
Inventor
Hiroyuki Demura
博之 出村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP10173089A priority Critical patent/JP2000013190A/en
Publication of JP2000013190A publication Critical patent/JP2000013190A/en
Pending legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a matching circuit automatic adjusting device which can always automatically adjust the matching circuit of a receiver in optimum and adjusts the reception sensitivity of the receiver to the maximum. SOLUTION: A variable capacitor diode 4 is installed in a matching circuit 3. Output with an adjusted matching state is monitored in RSSi 8 and a CPU controller 9 controls the follow-up of a control voltage circuit 5 so that a level measuring value becomes maximum. CPU 9 is provided with a table of variable capacitor diode control voltages against a channel. Control voltage corresponding to a reception channel is set by using the table. CPU 9 stores the level measurement value of RSSi 8 at control voltage which is set in the register. The level measurement value of RSSi 8 when control voltage is raised (or dropped) by one bit or several bits is compared with a register storage value. When the level measurement value is large, it is stored in the register and voltage control is repeated again. When the level measurement value is smaller as a result, follow-up for holding a state where control voltage is dropped (raised) by one bit is executed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、受信機の整合回路
の自動調整装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for automatically adjusting a matching circuit of a receiver.

【0002】[0002]

【従来の技術】受信機の整合回路は、L、C同調回路に
より受信機の受信チャネルの選択を行うものであるが、
従来の回路構成は、固定チップ部品で構成したもの。
トリマ調整部品を使って、製造時にある周波数帯にの
み整合がとれるようにしたもの。バリキャップダイオ
ードを用いてチャネル毎に制御電圧を予め設定しておい
て、切替えるようにしたもの。受信帯域が広い受信機
では、2つの周波数帯の回路で対応するようにしたもの
等の方式が提案されている。
2. Description of the Related Art A matching circuit of a receiver selects a receiving channel of the receiver by an L and C tuning circuit.
The conventional circuit configuration consists of fixed chip components.
A device that uses a trimmer adjustment component to match only a certain frequency band during manufacturing. A control voltage is preset for each channel using a varicap diode, and is switched. For a receiver having a wide reception band, a system in which circuits in two frequency bands are used has been proposed.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記
の方式では、実装後の調整が不可能で、部品のバラツキ
がそのまゝ整合のバラツキに反映され、さらに受信する
チャネルの違いによるインピーダンスの変化も同様に反
映される。また、の方式では、実装後の調整が可能で
あるが、エンドユーザに渡った後の調整は不可能なの
で、受信帯域が広い場合は受信するチャネルの違いによ
るインピーダンスの変化が不整合の原因となる。の方
式では、設定電圧の切替によって調整できても、温度に
よるインピーダンスの変化や、周囲部品の時間的特性変
化には対応できない。またの方式では、受信帯域幅が
広い受信機では、LNA(Low Noise Amp)2つ使い
分けなければならない場合がある。といった欠点があ
る。
However, in the above-mentioned method, adjustment after mounting is impossible, and variations in components are directly reflected in variations in matching, and changes in impedance due to differences in receiving channels are also affected. It is reflected similarly. In the above method, adjustment after mounting is possible, but adjustment after reaching the end user is not possible.If the reception band is wide, the change in impedance due to the difference of the receiving channel may cause the mismatch. Become. In the method described above, even if the adjustment can be performed by switching the set voltage, it cannot cope with a change in impedance due to temperature or a change in temporal characteristics of peripheral components. In another method, a receiver having a wide reception bandwidth may have to use two LNAs (Low Noise Amp). There are drawbacks.

【0004】本発明の目的は、上記従来の、固定チップ
部品のバラツキにより整合のバラツキが生じる、受信す
るチャネルの違いによるインピーダンスの変化に整合回
路が対応しない、温度や周囲部品の経年変化に整合回路
が対応しない、広い受信帯域の受信機では1つの回路で
対応できないときがある、といった問題点を解決し、整
合回路を常に最適に自動調整し、受信機の受信感度を最
大にする自動調整装置の提供にある。
[0004] It is an object of the present invention to provide a matching circuit that does not cope with a change in impedance due to a difference in receiving channels, a matching circuit that does not cope with changes in temperature and surrounding components over time. Solves the problem that a circuit does not support, and a receiver with a wide reception band may not be able to respond with one circuit, and automatically adjusts the matching circuit automatically and optimally to maximize the receiving sensitivity of the receiver In providing the equipment.

【0005】[0005]

【課題を解決するための手段】上記の目的は、受信信号
の整合回路にバリキャップダイオードを設け、該整合回
路の出力をモニタするRSSI(Receiving Signal
Strength Indicator)と、該RSSIのモニタレベル
が常に最大になるよう上記バリキャップダイオードの印
加電圧を調整するコントローラを設けたことによって達
成される。
An object of the present invention is to provide a receiving signal matching circuit provided with a varicap diode and monitoring the output of the matching circuit by an RSSI (Receiving Signal).
(Strength Indicator) and a controller for adjusting the applied voltage of the varicap diode so that the monitor level of the RSSI is always maximized.

【0006】また上記の目的は、上記コントローラが、
チャネル対バリキャップダイオード制御電圧のテーブル
を有し、該テーブルに対応した制御電圧の近辺をモニタ
するものであることによって達成される。
[0006] The above object is also achieved by the above-mentioned controller,
This is achieved by having a table of channel to varicap diode control voltages and monitoring the vicinity of the control voltage corresponding to the table.

【0007】上記の手段によると、コントローラは、バ
リキャップダイオードの電圧をコントロールし調整しな
がらRSSIをモニタし、RSSIの出力レベルが最大
となる電圧をバリキャップダイオードに印加し整合回路
を最適整合状態に保持する。
According to the above means, the controller monitors the RSSI while controlling and adjusting the voltage of the varicap diode, applies a voltage at which the output level of the RSSI becomes maximum to the varicap diode, and adjusts the matching circuit to the optimum matching state. To hold.

【0008】また、上記コントローラは、チャネル対バ
リキャップダイオードの制御電圧のテーブルを有し、そ
のテーブを用いてテーブルに対応した制御電圧の近辺を
モニタすることにより、迅速に最適値を見つけるように
動作する。
The controller has a table of control voltages of the channel-to-varicap diode and monitors the vicinity of the control voltage corresponding to the table using the table to quickly find an optimum value. Operate.

【0009】[0009]

【発明の実施の形態】以下、本発明の実施の形態を図面
を用いて説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0010】図1は、本発明の一実施形態の構成図であ
る。受信機は、アンテナ1から受信した電波をLNA
(Low Noise Amp)で増幅し、整合回路3で受信チャ
ネルの選択同調を行なう。整合回路3には印加電圧によ
って容量が可変するバリキャップダイオード4を設け、
この可変制御により同調周波数を受信電波のチャネルに
整合する。整合回路で整合された受信周波数はミキサ6
により局部発振周波数と混合され中間周波数に変換さ
れ、さらに中間周波増幅器7で増幅される。この中間周
波数増幅器7の増幅出力をRSSI8でモニタし、モニ
タ出力が常に最大になるようCPUコントローラ9でバ
リキャップダイオード4の制御電圧回路5を追従制御す
る。
FIG. 1 is a configuration diagram of an embodiment of the present invention. The receiver converts the radio wave received from antenna 1 to LNA
(Low Noise Amp) and the matching circuit 3 performs selective tuning of the reception channel. The matching circuit 3 is provided with a varicap diode 4 whose capacity varies according to the applied voltage.
By this variable control, the tuning frequency is matched to the channel of the received radio wave. The reception frequency matched by the matching circuit is
Is mixed with the local oscillation frequency, converted into an intermediate frequency, and further amplified by the intermediate frequency amplifier 7. The amplified output of the intermediate frequency amplifier 7 is monitored by the RSSI 8, and the CPU controller 9 controls the tracking of the control voltage circuit 5 of the varicap diode 4 so that the monitored output is always maximized.

【0011】CPU9は、各部の制御をするためのソフ
トウエア及びデータをROM、RAM等のメモリに保持
しておく、また、予め、数ポイントの周波数でRSSI
8の測定値が最大となるバリキャップダイオード制御電
圧を設定し、それから予想できる受信チャネル対制御電
圧のテーブルを作成し、それをメモリに記憶・保持して
おき、そのテーブルに対応した制御電圧で制御し、且つ
その制御電圧の近辺をモニタして最適値を見つけるよう
に制御する。
The CPU 9 stores software and data for controlling each unit in a memory such as a ROM or a RAM, and also stores RSSI at a frequency of several points in advance.
8 sets the varicap diode control voltage at which the measured value becomes the maximum, creates a table of the reception channel pair control voltage that can be predicted from the varicap diode control voltage, and stores and stores it in the memory, and uses the control voltage corresponding to the table. The control is performed, and control is performed so as to find the optimum value by monitoring the vicinity of the control voltage.

【0012】図2及び図3は、CPU9の動作時のフロ
ーチャートを示す。電源ON(S1)したときは、制御
電圧テーブルのセンタ値で制御電圧回路5を制御するよ
う動作する(S2)。入力部から所望の受信チャネル信
号を入力すると、CPU9はこれを判断してメモリに記
憶・保持された制御電圧テーブルから受信チャネル対応
の電圧データを読み出し出力部から制御電圧回路5に対
応データを出力してバリキャップダイオード4を制御す
る(S6)。
FIG. 2 and FIG. 3 are flowcharts when the CPU 9 operates. When the power is turned on (S1), an operation is performed to control the control voltage circuit 5 with the center value of the control voltage table (S2). When a desired reception channel signal is input from the input unit, the CPU 9 judges this, reads out the voltage data corresponding to the reception channel from the control voltage table stored and held in the memory, and outputs the corresponding data to the control voltage circuit 5 from the output unit. Then, the varicap diode 4 is controlled (S6).

【0013】バリキャップダイオード4の電圧制御によ
り整合回路3が受信チャネルに整合するよう調整される
が、そのときの整合状態はRSSI8でモニタされる。
RSSI8のレベル測定値はCPU9の有するレジスタ
に格納される(S7)。
The matching circuit 3 is adjusted to match the reception channel by controlling the voltage of the varicap diode 4, and the matching state at that time is monitored by the RSSI 8.
The measured level of the RSSI 8 is stored in a register of the CPU 9 (S7).

【0014】次にCPU9は制御電圧を1ビット分だけ
上げるように制御電圧回路5にデータ出力し、整合回路
3を調整する(S8)。そのときのRSSI8の測定値
をレジスタに格納したデータ値と比較し(S9)、測定
値が格納値より大きいとき、RSSI8のレベル測定値
をレジスタに格納し(S10)、フラグ1を立てる(S
11)。更にステップ(S8)に戻り再び制御電圧を1
ビット分上げて、RSSI8の測定値をレジスタ格納値
と比較し(S9)、測定値が大きいとそれをレジスタに
格納し(S10)、制御電圧を1ビット分上げる(S
8)。この制御ループを繰返して整合回路3の最適値を
求める。
Next, the CPU 9 outputs data to the control voltage circuit 5 so as to increase the control voltage by one bit, and adjusts the matching circuit 3 (S8). The measured value of RSSI8 at that time is compared with the data value stored in the register (S9). If the measured value is larger than the stored value, the measured level of RSSI8 is stored in the register (S10), and flag 1 is set (S10).
11). Further, returning to step (S8), the control voltage is again set to 1
The measured value of RSSI 8 is compared with the value stored in the register (S9). If the measured value is large, it is stored in the register (S10), and the control voltage is increased by one bit (S9).
8). This control loop is repeated to determine the optimum value of the matching circuit 3.

【0015】ステップ(S9)の比較において、RSS
I8の測定値がレジスタ格納値より小さいと、ステップ
(S12)に進み、フラグが1である場合、フラグを0
にし、制御電圧を1ビット分下げたデータを出力し制御
電圧回路5を制御し、かつその状態を保持する(S1
3)。またステップ(12)でフラグが1でない場合
は、制御電圧を2ビット分下げたデータを出力して制御
電圧回路5を制御する(S14)。
In the comparison of step (S9), RSS
If the measured value of I8 is smaller than the value stored in the register, the process proceeds to step (S12), and if the flag is 1, the flag is set to 0.
And outputs data in which the control voltage is reduced by one bit to control the control voltage circuit 5 and maintain the state (S1).
3). If the flag is not 1 in step (12), the control voltage circuit 5 is controlled by outputting data obtained by lowering the control voltage by 2 bits (S14).

【0016】更にRSSI8のレベル測定値をレジスタ
格納値と比較し(S15)、測定値が格納値より小さい
とフラグを0にし、制御電圧を1ビット上げたデータを
出力し制御電圧回路5を制御しその状態を保持する(S
16)。また測定値が格納値より大きい場合はその測定
値をレジスタに格納(S17)すると共に、制御電圧を
1ビット分下げる(S18)。
Further, the level measured value of the RSSI 8 is compared with the value stored in the register (S15). If the measured value is smaller than the stored value, the flag is set to 0, and the control voltage is increased by one bit to output the control voltage circuit 5, thereby controlling the control voltage circuit 5. And keep that state (S
16). If the measured value is larger than the stored value, the measured value is stored in the register (S17) and the control voltage is reduced by one bit (S18).

【0017】更にRSSI8のレベル測定値をレジスタ
格納値と比較し(S19)、測定値が格納値より大きい
とステップ(S17)に戻って測定値をレジスタに格納
する。比較により測定値が格納値より小さいとフラグを
0にし、制御電圧を1ビット分上げたデータを出力し制
御電圧回路5を制御し、かつその状態を保持する(2
0)。
Further, the measured level value of the RSSI 8 is compared with the value stored in the register (S19). If the measured value is larger than the stored value, the process returns to step (S17) to store the measured value in the register. If the measured value is smaller than the stored value by the comparison, the flag is set to 0, the control voltage is increased by one bit, data is output, the control voltage circuit 5 is controlled, and the state is maintained (2).
0).

【0018】以上のようなフローにしたがってCPU9
は動作し、データ出力して制御電圧回路5を制御し、バ
リキャップダイオード4を制御し、整合回路3を受信チ
ャネルに整合するよう調整する。整合回路3の整合状態
はRSSI8でモニタし、この測定値が常に最大になる
よう制御する。RSSI8の測定値レベルが最大となる
制御電圧をバリキャップダイオード4に印加し続けるこ
とにより整合回路3は最適な整合状態を保ち、受信チャ
ネルを高感度で選択し受信することができる。
The CPU 9 follows the above flow.
Operates, outputs data and controls the control voltage circuit 5, controls the varicap diode 4, and adjusts the matching circuit 3 to match the reception channel. The matching state of the matching circuit 3 is monitored by the RSSI 8, and control is performed such that the measured value is always maximum. By continuously applying the control voltage at which the measured value level of the RSSI 8 is maximized to the varicap diode 4, the matching circuit 3 can maintain an optimum matching state, and can select and receive a reception channel with high sensitivity.

【0019】また、受信チャネルが変更された時(S
5)はステップ(S6)から始める。また、他のチャネ
ルをモニタする時も、上記図2、図3のフローにしたが
ってCPU9が動作を繰返すことによって最適な受信を
することができる。
When the receiving channel is changed (S
5) starts from step (S6). Also, when monitoring other channels, the CPU 9 repeats the operation in accordance with the flow shown in FIGS.

【0020】最適受信モニタは、予めチャネル対制御電
圧のテーブルを作成し、チャネル変更時、そのテーブル
に対応したコントロール電圧を中心にその近辺をモニタ
することにより最適値を見つけるので、最適整合を極め
て迅速にすることができる。
The optimum reception monitor prepares a channel-to-control voltage table in advance and finds an optimum value by monitoring a control voltage corresponding to the table when the channel is changed. Can be quick.

【0021】またRSSIをモニタし、RSSIが最大
になる点でコントロール電圧を一時固定し、あとは、受
信チャネルを変更したとき、別のチャネルをモニタする
とき、受信機の温度が変化する一定時間間隔毎(送受信
機の構成により予測)、に再度RSSIをモニタしなが
らコントロール電圧の調整を行なう。
Further, the RSSI is monitored, the control voltage is temporarily fixed at the point where the RSSI becomes maximum, and when the receiving channel is changed or another channel is monitored, the temperature of the receiver changes for a certain period of time. At every interval (estimated by the configuration of the transceiver), the control voltage is adjusted while monitoring the RSSI again.

【0022】[0022]

【発明の効果】以上説明したように、本発明によれば、
部品のバラツキによる不整合から生じる受信機感度劣化
が改善できる。また受信するチャネルの変化による不整
合から生じる受信機感度劣化を改善できる。温度変化や
周囲部品の時間的特性劣化による不整合から生じる受信
機感度劣化を改善できる。また広い受信帯域の受信機で
も1つの回路で対応できる。
As described above, according to the present invention,
It is possible to improve receiver sensitivity degradation caused by mismatch due to component variation. Further, it is possible to improve receiver sensitivity degradation caused by mismatch due to a change in a channel to be received. It is possible to improve receiver sensitivity deterioration caused by mismatch due to temperature change or deterioration of temporal characteristics of peripheral components. Further, even a receiver having a wide reception band can be handled by one circuit.

【0023】また受信感度はインピーダンス整合だけで
なく、NF(Noise Figure)にも大きく依存し、実際
の設計段階では両者を調整しながら各部品の定数を決め
るのに手間がかゝるが、本発明によれば、受信感度に直
接つながるRSSIをモニタしながら調整することによ
り、その手間が簡略化できる。
Also, the receiving sensitivity greatly depends not only on impedance matching but also on NF (Noise Figure), and in the actual design stage, it is troublesome to determine the constant of each component while adjusting both. According to the present invention, the adjustment can be performed while monitoring the RSSI directly connected to the reception sensitivity, thereby simplifying the operation.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の構成ブロック図。FIG. 1 is a configuration block diagram of an embodiment of the present invention.

【図2】本発明の一実施形態の動作時のフローチャー
ト。
FIG. 2 is a flowchart at the time of operation of an embodiment of the present invention.

【図3】本発明の一実施形態の動作時のフローチャー
ト。
FIG. 3 is a flowchart at the time of operation of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…アンテナ、2…LNA、3…整合回路、4…バリキ
ャップダイオード、5…制御電圧回路、6…ミキサ、7
…IF増幅器、8…RSSI、9…コントローラ(CP
U)。
DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... LNA, 3 ... matching circuit, 4 ... Varicap diode, 5 ... Control voltage circuit, 6 ... Mixer, 7
... IF amplifier, 8 ... RSSI, 9 ... Controller (CP
U).

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 受信機の整合回路を最適に自動調整する
装置において、受信信号の整合回路にバリキャップダイ
オードを設け、該整合回路の出力をモニタするRSSI
と、該RSSIのレベル測定値が常に最大になるように
上記バリキャップダイオードに印加する制御電圧を調整
するコントローラを設けたことを特徴とする受信機の整
合回路自動調整装置。
1. An apparatus for automatically adjusting a matching circuit of a receiver, wherein a varicap diode is provided in a matching circuit of a received signal, and an RSSI for monitoring an output of the matching circuit is provided.
And a controller for adjusting a control voltage applied to the varicap diode so that the measured level of the RSSI is always maximized.
【請求項2】 上記コントローラは、予めチャネル対バ
リキャップダイオード制御電圧のテーブルを備え、該テ
ーブルに対応した制御電圧の近辺をモニタするものであ
ることを特徴とする請求項1記載の受信機の整合回路自
動調整装置。
2. The receiver according to claim 1, wherein said controller is provided with a channel-to-varicap diode control voltage table in advance, and monitors the vicinity of the control voltage corresponding to the table. Automatic matching circuit adjustment device.
JP10173089A 1998-06-19 1998-06-19 Matching circuit automatic adjusting device for receiver Pending JP2000013190A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10173089A JP2000013190A (en) 1998-06-19 1998-06-19 Matching circuit automatic adjusting device for receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10173089A JP2000013190A (en) 1998-06-19 1998-06-19 Matching circuit automatic adjusting device for receiver

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JP2000013190A true JP2000013190A (en) 2000-01-14

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JP10173089A Pending JP2000013190A (en) 1998-06-19 1998-06-19 Matching circuit automatic adjusting device for receiver

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7499676B2 (en) 2005-03-17 2009-03-03 Samsung Electronics Co., Ltd. Low voltage differential signaling transceiver
US7499677B2 (en) 2005-03-22 2009-03-03 Samsung Electronics Co., Ltd. Low voltage differential signaling transceiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7499676B2 (en) 2005-03-17 2009-03-03 Samsung Electronics Co., Ltd. Low voltage differential signaling transceiver
US7499677B2 (en) 2005-03-22 2009-03-03 Samsung Electronics Co., Ltd. Low voltage differential signaling transceiver

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