JP2000012775A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with an electrode where fine and granular semiconductors are uniformly formed on its surface at a low cost. SOLUTION: A gate electrode 103, a source electrode formed of an N-type diffused layer 104, and a drain electrode formed of an N-type diffused layer 105 are formed on a P-type silicon substrate 100 for the formation of a MOSFET, a columnar capacitor is composed of a second lower electrode 108, a dielectric film 110, and an upper electrode 111, where granular silicon germanium semiconductors are provided to the second lower electrode 108 for enlarging the capacitor in electrostatic capacity in a semiconductor memory device. The second lower electrode 108 of a polycrystalline silicon film is formed on the surface of a first lower electrode 107, and when silicon germanium is deposited on the surface of the second lower electrode 108, granular silicon germanium bodies 109 are formed by crystal grain boundaries present on the surface of the second lower electrode 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitance element for each unit memory cell, and more particularly to a semiconductor device having a plurality of minute conductive particles on the surface of one electrode of the capacitance element. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor memory device, it is necessary to provide a capacitor (capacitance element: capacitor) for each unit memory cell. This capacitor has a minimum static capacitance necessary for holding stable information. It is necessary to have capacitance. On the other hand, in order to increase the storage capacity of the semiconductor memory device, it is necessary to reduce the area per unit memory cell on the semiconductor substrate surface.

Therefore, various proposals have conventionally been made to secure a large capacitance with a small cell area.

[0004] For example, "Summary of the 22nd Solid State Device and Material Conference" (1990, pp.873-876) (Extended A
bstracts of the 22nd Conferenceon Solid State Devi
(ces and Materials, 1990, pp. 873-876), a polycrystalline silicon film with an uneven shape is formed directly on the surface of the lower electrode of a cylindrical capacitor, which has twice the normal capacitance. It discloses a method of causing the error to occur.

[0005] Similarly, "Summary of Solid-state Devices and Materials Conference in 1991" (1991, pp. 478-480) (Exte
nded Abstracts of the 1991 Conferenceon Solid Stat
e Devices and Materials, 1991, pp. 478-480) deposited amorphous silicon on the surface of the lower electrode, and heat-treated in vacuum to form granular polycrystalline silicon.
This discloses a method for increasing the capacitance.

A method of forming granular polycrystalline silicon by heat-treating amorphous silicon as in this method is more process-intensive than a method of directly forming a polycrystalline silicon film having an uneven shape. There is an advantage that high-precision temperature control is not required and hemispherical polycrystalline silicon can be formed on the inner and outer wall surfaces of the cylinder, but the size of the formed hemispherical polycrystalline silicon can be controlled. There is a problem in the point.

[0007] Therefore, "Applied Physics Lett" (1992, pp. 159-161) (Applied Physics Lett)
ers, pp. 159-161, (1992)), after forming an amorphous silicon film, selectively depositing silicon molecules on the surface thereof in an ultra-high vacuum, thereby starting the polycrystalline silicon. A method is disclosed in which sites for generating crystal nuclei (crystal growth points) are formed so as to make the size of granular polycrystalline silicon uniform.

[0008]

SUMMARY OF THE INVENTION Among the above prior arts,
In a method of forming a polycrystalline silicon film having an uneven shape directly on the surface of one electrode of a columnar capacitor, a method of forming a polycrystalline silicon film at a temperature of 5 ° C.
Since high-precision temperature control is required, there is a problem that it is extremely difficult to always form a polycrystalline silicon film having the same concavo-convex shape over the entire surface of the wafer or when the batch is different.

In the above-mentioned prior art, the method of heating an amorphous silicon film in a high vacuum to form hemispherical granular polycrystalline silicon involves the steps of depositing an amorphous silicon film and generating crystal nuclei. Since three types of processes, site formation and heat treatment, are required, there is a problem that it is extremely difficult to reduce the manufacturing cost.

An object of the present invention is to solve these problems of the prior art and to provide a semiconductor device having a fine granular semiconductor uniformly on the surface of an electrode at a low cost.

[0011]

The present inventors have conducted detailed studies on the formation of a granular semiconductor on the lower electrode of a capacitor, and as a result, have solved the above-mentioned problems of the prior art, and
At the same time, the present invention has been conceived of a configuration of a semiconductor device capable of improving the productivity. In other words, in the prior art, attention is paid to the surface of the base electrode, which is not considered at all, and the fine structure is selected by selecting the surface structure of the lower electrode. This enables uniform formation of fine granular semiconductors.

Therefore, according to the first aspect of the present invention, the above object is achieved by sequentially laminating a dielectric film and the other electrode film on the surface of one electrode having conductive granules formed on the surface. In the semiconductor device having a capacitance portion, when the conductive granular material deposits one of silicon germanium and germanium on the surface of polycrystalline silicon, a crystal grain boundary existing on the surface of the polycrystalline silicon is crystallized. This is achieved by being composed of silicon germanium or germanium particles formed as growth points.

At this time, the size of the crystal grain boundary of the polycrystalline silicon is larger than the particle diameter of the silicon germanium or germanium.
The sum may be smaller than the sum of the doubles. Similarly, the one electrode may include a polycrystalline silicon film having a thickness of 40 nm or less on the surface.

Next, according to a second aspect of the present invention, the above object is achieved by sequentially laminating a dielectric film and the other electrode film on the surface of one electrode having conductive granules formed on the surface. In a semiconductor device having a capacitance portion, the one electrode is formed of polycrystalline silicon having a metal film on a surface, and the conductive granules deposit one of silicon germanium and germanium on a surface of the metal film. This is achieved by forming the microstructure existing on the surface of the metal film with silicon germanium or germanium particles formed as crystal growth points.

Further, according to the third aspect of the present invention, the above object is attained by sequentially laminating a dielectric film and the other electrode film on the surface of one of the electrodes on which the conductive particles are formed. In the semiconductor device having a capacitance portion, the one electrode is formed of amorphous silicon deposited by a plasma CVD method, and the conductive granular material has silicon germanium and germanium on the surface of the amorphous silicon. This is achieved by depositing one of them, comprising silicon germanium or germanium particles formed on the surface of the amorphous silicon.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the illustrated embodiments. <Embodiment 1> FIG. 1 shows Embodiment 1 of the present invention, in which 100 is a P-type silicon substrate having a plane orientation (100), 101 is a silicon oxide film, 102 is a gate oxide film,
103 is a gate electrode; 104 and 105 are N-type diffusion layers;
06 is a first interlayer insulating film, 107 is a first lower electrode, 108
Is the second lower electrode, 109 is granular silicon germanium,
110 is a dielectric film, and 111 is an upper electrode.

Embodiment 1 is an example of a case where the present invention is implemented as a semiconductor memory device, and is a cross-sectional view of a unit memory cell portion constituting a semiconductor memory device. The gate electrode 103 and N-type diffusion layers 104 and 105 are shown in FIG. MOSFET is formed by the source electrode and the drain electrode comprising
Lower electrode 108, dielectric film 110, and upper electrode 11
1 forms a columnar capacitor, which constitutes a unit memory cell portion.

At this time, by providing granular silicon germanium 109 comprising a plurality of substantially hemispherical particles on the surface of the second lower electrode 108, the electrode area is increased, thereby increasing the capacitance. A memory cell having a columnar capacitor is obtained. The semiconductor memory device having the unit memory cell portion shown in FIG. 1 was manufactured as follows.

First, as shown in FIG. 2, a silicon oxide film 101 and a gate oxide film 10 are formed on a p-type silicon substrate 100.
2. A gate electrode 103 is provided thereon. For this purpose, a P-type silicon substrate 100 having a plane orientation (100) is first prepared, a mask oxide film (not shown) is formed on one surface thereof, and a silicon nitride film (not shown)
Deposited to a thickness of Thereafter, the mask oxide film and the nitride film are removed by a photolithography technique, leaving only a predetermined portion serving as an element region, and about 40 nm is removed by thermal oxidation.
A silicon oxide film 101 having a thickness of 0 nm is formed as shown in FIG.

Next, after the remaining mask oxide film and silicon nitride film are removed by wet etching, 9
An oxidation treatment is performed at a temperature of 50 ° C. to form a gate oxide film 102 having a thickness of 15 nm on the surface of the P-type silicon substrate 100 exposed in the element region. Further, 200 nm by the CVD method.
A polycrystalline silicon film is deposited to a thickness of 2 μm, and a normal photolithography technique and a dry etching technique are used.
The gate electrode 103 is formed as shown in FIG.

Next, as shown in FIG.
4 and 105 and a first interlayer insulating film 106 are provided. Therefore, first, the gate oxide film 10 of the P-type silicon substrate 100 is
The portion 2 is exposed, by an acceleration energy of 80 keV, arsenic is implanted at a density of 2 × 10 ¹⁵ cm ^-2, as shown in FIG. 3, to form an N-type diffusion layer 104, 105. Next, the gate electrode 10 is wet-etched.
The gate oxide film 102 is removed except for the portion immediately below the gate oxide film 3, and thereafter, a silicon oxide film is deposited by a CVD method, and a first interlayer insulating film 106 is formed as shown in FIG.

Next, as shown in FIG.
07 is provided. Therefore, first, a part of the first interlayer insulating film 106 on the N-type diffusion layer 105 is removed by a normal photolithography technique and a dry etching technique. Then, a polycrystalline silicon film is deposited on this portion by the CVD method, and is processed by a normal photolithography technique and a dry etching technique to form the first lower electrode 107.

Next, as shown in FIG. 5, the second lower electrode 1
08 is provided. Therefore, the surface of the first lower electrode 107 is formed to a thickness of 20 nm by a selective growth technique using a low pressure CVD method.
Is formed, and thereby the second lower electrode 108 is obtained. At this time, the second lower electrode 108
It is necessary that the size (crystal grain size) of the crystal part of the polycrystalline silicon film forming the film be about 33 nm. Therefore, as described above, the film thickness of the polycrystalline silicon film becomes 20 nm. It is.

The conditions for growing the polycrystalline silicon film for this purpose are as follows. That is, the supply rate of hydrogen gas is 1 / min.
The supply amounts of liter and disilane gas are 0.1 liter per minute, the supply amount of hydrogen chloride gas is 0.01 liter per minute, the gas pressure is 1 Torr, and the growth temperature is 550 ° C.

Next, as shown in FIG. 6, a granular silicon germanium 109 is provided. For this reason, silicon germanium is deposited on the surface of the second lower electrode 108 by a low pressure CVD method. Then, the second lower electrode 108
Silicon germanium is generated as a plurality of substantially hemispherical particles on the surface of the substrate, and granular silicon germanium 109 is formed.

This is because the second lower electrode 108 serving as a base when silicon germanium is deposited is formed of a silicon film having a polycrystalline structure.
At this time, the portion where the boundary of the polycrystal (crystal grain boundary) is exposed on the surface becomes a crystal growth point when silicon germanium to be deposited is crystallized, and crystallization proceeds from this point. .

The conditions for forming silicon germanium particles by the low pressure CVD method at this time are as follows. That is, the supply amount of hydrogen gas is 1 liter per minute, the supply amount of dichlorosilane gas is 0.1 liter per minute, the supply amount of hydrogen chloride gas is 0.01 liter per minute, and the gas pressure is 1 Torr.
r, the growth temperature is 750 ° C., and the growth time is 3 minutes.

The particle diameter of the granular silicon germanium 109 thus obtained is about 30 nm, which reduces the size of the crystal part of the polycrystalline silicon film forming the second lower electrode 108, as described above. This is a result of 33 nm, which ensures that the particles of the granular silicon germanium 109 are formed in a state of being separated from each other as shown in the drawing without contact between adjacent particles.

If this is generally defined, the size of the crystal part of the polycrystalline silicon film forming the second lower electrode 108 is made larger than the particle diameter of the granular silicon germanium 109, and It is desirable to make the size smaller than the sum of the size of the crystal part and twice the thickness of the dielectric film 110 described later.

The size of the crystal part of the polycrystalline silicon film forming the second lower electrode 108 at this time is as follows:
By controlling the film pressure of the polycrystalline silicon film, the polycrystalline silicon film can be easily made any size.

Next, as shown in FIG.
Is provided. The dielectric film 110 is formed by depositing a high dielectric substance (Ba, Sr) TiO ₃ on the surface of the granular silicon germanium 109 and on the exposed portion of the second lower electrode 108. The thickness of the dielectric film 110 is 3
nm. In addition, as this dielectric film 110,
In addition to the above-described high dielectric substances, substances such as silicon oxide, nitride, oxynitride, and tantalum oxide may be used.

Next, as shown in FIG.
Is provided. That is, first, in the state of FIG. 7, a titanium nitride film is deposited on the entire surface, and then the dielectric film 11 is formed.
The upper electrode 111 is formed as shown in FIG. 8 by dry-etching while leaving the titanium nitride film only at a desired portion including the surface of the unit memory shown in FIG. A semiconductor memory device having a cell portion is obtained.

According to the semiconductor device according to the embodiment of the present invention shown in FIG. 1, the electrostatic capacity is two to three times that of the conventional case where polysilicon (polycrystalline silicon) is used as an electrode as it is. A capacitor part having a capacity was obtained. Also, it has been confirmed that the capacitor portion in this embodiment also has the same leak current characteristics and breakdown voltage characteristics as in the case where conventional polysilicon is used as it is as an electrode. Semiconductor device with high reliability can be easily obtained.

In the first embodiment, the lower electrode (inner electrode) of the capacitor is
The lower electrode 108 has a two-layer structure, but may have a multilayer structure of three or more layers. Further, granular germanium may be used instead of the granular silicon germanium 109.

<Second Embodiment> Next, FIG. 12 shows a second embodiment of the present invention, in which reference numeral 201 denotes a second lower electrode 201 made of a titanium silicide film, and the other components are the same as those in FIG. In the second embodiment, the second lower electrode 108 in the first embodiment is made of a titanium silicide film to improve the conductivity.
Manufacturing steps from the start of processing from 0 to the formation of the first lower electrode 107 are the same as those in the first embodiment shown in FIGS.

After the first lower electrode 107 is formed as shown in FIG. 4, in the second embodiment, as shown in FIG. 9, the second lower electrode 201 made of a titanium silicide film is formed.
Is provided. For this reason, first, in the state of FIG. 4, a titanium film is deposited to a thickness of 50 nm on the entire surface by a sputtering method, and thereafter, a titanium film is deposited in a nitrogen atmosphere at a temperature of 700 ° C.
The heat treatment is performed for one minute so that only the portion of the titanium film on the surface of the first lower electrode 107 is silicided.

Next, when the substrate is immersed in a hydrogen peroxide solution, only the titanium film on the first interlayer insulating film 106 is removed except for the silicided portion. As a result, as shown in FIG. 107 on the surface of titanium silicide film 2
01 is formed. Next, when silicon germanium is deposited on the surface of the titanium silicide film 201 by the low pressure CVD method, granular silicon germanium 109 is formed as shown in FIG.

At this time, the growth conditions by the low pressure CVD method are as follows: hydrogen gas 1 liter per minute, dichlorosilane gas 0.1 liter per minute, hydrogen chloride gas 0.01 liter per minute, pressure 1 Torr, growth temperature 750 ° C. The time was 3 minutes, whereby the particle diameter of the formed granular silicon germanium 109 was about 30 nm.

Here, the reason why the granular silicon germanium 109 is formed only by depositing silicon germanium on the surface of the titanium silicide film 201 is as follows.
It can be explained as follows.

When observed with an electron microscope, a fine discontinuous structure similar to a crystal grain boundary is found on the surface of the titanium silicide film 201. This is because, as described above, as a result of reducing the thickness of the titanium silicide film 201 to about 50 nm, the titanium silicide film 201 is strongly affected by the polycrystalline silicon film constituting the first lower electrode 107 as the base. it is conceivable that. Then, this titanium silicide film 201
It can be considered that the fine discontinuous structure on the surface serves as a crystal growth point when silicon germanium is deposited and crystallized, and as a result, granular silicon germanium 109 is formed.

Next, a high dielectric substance (Ba, Sr) TiO ₃ is deposited on the surface of the granular silicon germanium 109 and the portion where the titanium silicide film 201 is exposed.
As shown in FIG. 7, a dielectric film 110 is formed. The thickness of the dielectric film 110 is also set to about 3 nm.

As in the first embodiment, as the dielectric film 110, a silicon oxide film, a nitride film, an oxynitride film, a tantalum oxide film, or the like is used instead of the above-mentioned high dielectric substance. May be implemented.

Next, a titanium nitride film is formed, and the titanium nitride film is left only at a predetermined position by dry etching. As shown in FIG.
As a result, a semiconductor memory device having a unit memory cell portion was completed as shown in the figure.

According to the semiconductor device according to the second embodiment of the present invention shown in FIG. 12, similar to the first embodiment described above, the semiconductor device according to the second embodiment is different from a case where conventional polysilicon (polycrystalline silicon) is used as it is as an electrode. As a result, a capacitor portion having a capacitance of two to three times was obtained. And
It has been confirmed that the capacitor portion according to the second embodiment also has the same leak current characteristics and breakdown voltage characteristics as those in the case where the conventional polysilicon is used as it is as the electrode. Therefore, according to the second embodiment, the reliability is improved. In addition, it is possible to easily obtain a semiconductor device having a high density, improve the conductivity by the titanium silicide film 201, and speed up data writing and reading.

In the second embodiment, a titanium silicide film was used as the lower electrode. However, similar results were obtained by using various silicide films such as cobalt silicide or a metal film such as tungsten. Further, granular germanium may be used instead of the granular silicon germanium 109.

Third Embodiment Next, FIG. 16 shows a third embodiment of the present invention, in which 301 is a first lower electrode.
Others are the same as FIG. In this embodiment, the second lower electrode 108 in the first embodiment is omitted, and only the first lower electrode made of an amorphous silicon film is used to simplify the manufacturing process. In the case of the third embodiment, the manufacturing process starting from the P-type silicon substrate 100 in the first embodiment and before forming the first lower electrode is the same as that of the first embodiment shown in FIGS. Is the same as when

First, in the same manner as in the first embodiment, after forming a first interlayer insulating film 106 as shown in FIG.
A part of the first interlayer insulating film 106 on the N-type diffusion layer 105 is removed by ordinary photolithography and dry etching. Next, amorphous silicon is deposited in a film shape on the entire surface by a plasma CVD method, and thereafter, the amorphous silicon film is patterned by a normal dry etching method, and as shown in FIG. A first lower electrode 301 made of a silicon film is formed.

Next, silicon germanium was deposited on the surface of the first lower electrode 301 by the low pressure CVD method, thereby forming granular silicon germanium 109 as shown in FIG. At this time, the growth conditions by the reduced pressure CVD method are as follows: hydrogen gas 1 liter per minute, dichlorosilane gas 0.1 liter per minute, hydrogen chloride gas 0.01 liter per minute, pressure 1 Torr, growth temperature 750 ° C., and growth time 3 minutes. As a result, granular silicon germanium 302 having a particle diameter of about 30 nm was generated.

Here, although the mechanism of forming the granular silicon germanium 109 only by depositing silicon germanium on the surface of the first lower electrode 301 made of an amorphous silicon film is not clear at present,
By using the first lower electrode 301 made of amorphous silicon deposited by the plasma CVD method, the formation of the granular silicon germanium 109 can be actually obtained.

Next, a high dielectric substance (Ba, Sr) TiO ₃ is deposited on the surface of the granular silicon germanium 109 and on the exposed portion of the first lower electrode 301, as shown in FIG. Then, a dielectric film 110 is formed. At this time, the thickness of the dielectric film 110 is about 3 nm. Note that, as described above, the dielectric film 110 may be a silicon oxide film, a nitride film, an oxynitride film, or a tantalum oxide film.

Next, after depositing titanium nitride in the form of a film on the entire surface, the titanium nitride film is left only by a predetermined amount by dry etching to obtain a film shown in FIG.
As shown in FIG. 5, an upper electrode 111 is formed,
As shown, a semiconductor memory device having a unit memory cell portion was completed.

According to the semiconductor device according to the second embodiment of the present invention shown in FIG. 16, similar to the first embodiment described above, the semiconductor device is different from the case where conventional polysilicon (polycrystalline silicon) is used as it is as an electrode. As a result, a capacitor portion having a capacitance of two to three times was obtained. And
It has been confirmed that the capacitor portion according to the second embodiment also has the same leak current characteristics and breakdown voltage characteristics as those in the case where the conventional polysilicon is used as it is as the electrode. Therefore, according to the second embodiment, the reliability is improved. Semiconductor device can be easily obtained, and the lower electrode
Since only the lower electrode 301 is used, the manufacturing process can be simplified, and the cost can be reduced.

In the third embodiment, an amorphous silicon film is used as the first lower electrode 301, but similar results can be obtained with an amorphous germanium film. Also in the third embodiment, the granular silicon germanium 1
Instead of 09, granular germanium may be formed.

[0054]

According to the present invention, an upper electrode is provided on a semiconductor substrate.
In a semiconductor memory device formed by laminating a dielectric film and a lower electrode, the crystal grain size of polycrystalline silicon as a lower electrode is preferably larger than that of silicon germanium formed on the lower electrode, and the granular semiconductor It was smaller than the sum of twice the grain size of the grains and the thickness of the dielectric film.

Here, polycrystalline silicon has a crystal grain boundary at a boundary between crystal grains. Since the silicon germanium grains are formed near the crystal grain boundaries in the early stage of growth, the grain boundary density of the polycrystalline silicon, that is, the crystal grain size of the polycrystalline silicon is controlled to control the grain size of the granular silicon germanium. The distribution can be controlled. Therefore, according to the present invention, it is possible to provide a low-cost semiconductor device having a fine granular semiconductor uniformly on the surface of the electrode.

In the present invention, the lower electrode has a multilayer structure, and a polycrystalline silicon film is formed on the outermost surface of the lower electrode. At this time, the polycrystalline silicon film preferably has a thickness of 40 nm.
It was as follows. As a result, the outermost surface of the lower electrode has a thickness of 40
Since there is a polycrystalline silicon film of nm or less, the distribution of silicon germanium particles can be easily controlled regardless of the material and shape of the lower electrode before the polycrystalline silicon film is formed.

Further, according to the present invention, the lower electrode is made of a metal material such as silicide or tungsten, so that the conductivity of the lower electrode is improved, and the influence of the crystal structure is changed. This has the effect that silicon germanium can be easily formed.

In addition, in the present invention, since the lower electrode is made of an amorphous semiconductor material such as an amorphous silicon film by a plasma CVD method, an effect that uniform and fine granular silicon germanium can be obtained at low cost can be obtained. Have.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing a first embodiment when the present invention is applied to a semiconductor memory device.

FIG. 2 is a cross-sectional structure diagram for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a sectional structural view for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional structure diagram for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a sectional structural view for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 6 is a sectional structural view for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 7 is a sectional structural view for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 8 is a sectional structural view for explaining a manufacturing process according to the first embodiment of the present invention.

FIG. 9 is a sectional structural view for explaining a manufacturing process according to the second embodiment of the present invention.

FIG. 10 is a sectional structural view for explaining a manufacturing process according to the second embodiment of the present invention.

FIG. 11 is a sectional structural view for explaining a manufacturing process according to the second embodiment of the present invention.

FIG. 12 is a sectional structural view showing a second embodiment when the present invention is applied to a semiconductor memory device.

FIG. 13 is a sectional structural view for explaining the manufacturing process of the third embodiment of the present invention.

FIG. 14 is a sectional structural view for explaining a manufacturing process according to the third embodiment of the present invention.

FIG. 15 is a cross-sectional structure diagram for explaining a manufacturing process according to a thirty-second embodiment of the present invention.

FIG. 16 is a sectional structural view showing a third embodiment in which the present invention is applied to a semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 100 P-type silicon substrate 101 Silicon oxide film 102 Gate oxide film 103 Gate electrode 104 N-type diffusion layer 105 N-type diffusion layer 106 First interlayer insulating film 107 First lower electrode 108 Second lower electrode 109 Granular silicon germanium 110 Dielectric film 111 Upper electrode 201 Titanium silicide film 301 First lower electrode made of amorphous silicon film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takaya Suzuki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. Address Central Research Laboratory, Hitachi, Ltd. (72) Inventor Takeo Shiba 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. Inside the development center (72) Inventor Akira Okawa 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Hideki Tomioka 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72 Inventor Satoshi Yamamoto 2326 Imai, Ome, Tokyo F-term in Hitachi, Ltd. Device Development Center 5F038 AC04 AC05 AC09 AC16 AC18 AV06 DF05 EZ01 EZ13 EZ14 EZ15 EZ20

Claims (5)

[Claims] 1. A semiconductor device having a capacitance portion formed by sequentially laminating a dielectric film and another electrode film on the surface of one electrode having a surface on which conductive particles are formed, wherein the conductive particles When the body deposits one of silicon germanium and germanium on the surface of polycrystalline silicon,
A semiconductor device comprising silicon germanium or germanium particles formed using crystal grain boundaries existing on the surface of the polycrystalline silicon as crystal growth points. 2. The invention according to claim 1, wherein a size of a crystal grain boundary of the polycrystalline silicon is larger than a particle diameter of the silicon germanium or germanium, and a sum of the particle diameter and twice the diameter of the dielectric film. A semiconductor device characterized by being smaller than the above. 3. The semiconductor device according to claim 1, wherein the one electrode includes a polycrystalline silicon film having a thickness of 40 nm or less on a surface. 4. A semiconductor device having a capacitance portion formed by sequentially laminating a dielectric film and another electrode film on the surface of one electrode having conductive granules formed thereon, wherein the one electrode Is formed of polycrystalline silicon having a metal film on the surface, and the conductive granular material, when one of silicon germanium and germanium is deposited on the surface of the metal film, a microstructure existing on the surface of the metal film A semiconductor device comprising silicon germanium or germanium particles formed by using as a crystal growth point. 5. A semiconductor device having a capacitance portion formed by sequentially laminating a dielectric film and another electrode film on the surface of one electrode having conductive granules formed thereon, wherein the one electrode Is formed of amorphous silicon deposited by a plasma CVD method, and when the conductive particles deposit one of silicon germanium and germanium on the surface of the amorphous silicon, the surface of the amorphous silicon A semiconductor device comprising silicon germanium or germanium particles formed on the substrate.