JP2000012737A - Manufacture of wiring board - Google Patents
Manufacture of wiring boardInfo
- Publication number
- JP2000012737A JP2000012737A JP10189928A JP18992898A JP2000012737A JP 2000012737 A JP2000012737 A JP 2000012737A JP 10189928 A JP10189928 A JP 10189928A JP 18992898 A JP18992898 A JP 18992898A JP 2000012737 A JP2000012737 A JP 2000012737A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- hole
- manufacturing
- wiring board
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は例えば半導体チップ
等が搭載される配線基板の製造方法に関する。The present invention relates to a method for manufacturing a wiring board on which, for example, a semiconductor chip or the like is mounted.
【０００２】[0002]
【従来の技術】半導体装置は高密度化、小型化を図るも
のとしてＢＧＡ型半導体装置が提案されている。前記Ｂ
ＧＡ型半導体装置は例えば基板の一方の面に半導体チッ
プを搭載し、他面に外部接続端子の半田ボ−ルを設ける
が、該基板には配線基板が使用される。2. Description of the Related Art A BGA type semiconductor device has been proposed to increase the density and reduce the size of a semiconductor device. Said B
In the GA type semiconductor device, for example, a semiconductor chip is mounted on one surface of a substrate, and solder balls for external connection terminals are provided on the other surface. A wiring substrate is used for the substrate.
【０００３】配線基板は配線パタ−ンを絶縁性基板の両
面に設け、該両面の配線パタ−ンを電気的に接続するの
にスル−ホ−ルが穿設され、デスミア処理をし、当該ス
ル−ホ−ルの内壁に無電解めっき、電解めっきの双方あ
るいは一方を施して金属層を形成し、これを導電層とし
前記両面の配線パタ−ンを電気的に接続している。In a wiring board, wiring patterns are provided on both surfaces of an insulating substrate, through holes are formed in the wiring substrate to electrically connect the wiring patterns on both surfaces, and desmear processing is performed. Electroless plating and / or electrolytic plating are applied to the inner wall of the through hole to form a metal layer, and this is used as a conductive layer to electrically connect the wiring patterns on both surfaces.
【０００４】また前記スル−ホ−ルには前記めっきによ
る導電層を保護するとともに、電気的特性を安定化させ
るためにレジストインクが充填される。[0004] The through-hole is filled with a resist ink to protect the conductive layer by the plating and to stabilize the electrical characteristics.
【０００５】前記スル−ホ−ルに充填したレジストイン
クにはエア−等の気体が不可避的に混入しているので、
充填後に真空雰囲気の下で脱泡処理が施される。A gas such as air is inevitably mixed in the resist ink filled in the through hole.
After filling, a defoaming treatment is performed under a vacuum atmosphere.
【０００６】[0006]
【この発明が解決しようとする課題】前記のように従来
における配線基板の製造は、工程がスル−ホ−ルの穿
設、スル−ホ−ル内へのめっき、めっきしたスル−ホ−
ルへのソルダ−レジストの充填及び脱泡処理と多岐であ
り、生産性及び製品歩留りを高めることが難しい。また
製造コストが嵩む問題がある。As described above, in the conventional method of manufacturing a wiring board, the steps of forming a through hole, plating in the through hole, and plating the plated through hole are performed.
It is difficult to increase the productivity and the product yield because of the variety of filling and defoaming of the solder resist into the solder. There is also a problem that the manufacturing cost increases.
【０００７】本発明は製造工程が多岐にならず、また工
程を減らし、生産性、歩留りとも高められ、製造コスト
を低減できる配線基板の製造方法を目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a wiring board which does not require a wide variety of manufacturing steps, reduces the number of steps, improves productivity and yield, and reduces manufacturing costs.
【０００８】[0008]
【課題を解決するための手段】本発明の目的を達成する
ための要旨は、基板の両面に配線パタ−ンを設けるとと
もに、穿設したスル−ホ−ルを介して前記両面の配線パ
タ−ンを電気的に接続する配線基板の製造方法におい
て、前記基板に配線パタ−ンを形成した所望箇所を穿孔
し、該スル−ホ−ルに別途形成した導電体を埋設して前
記両面の配線パタ−ンを電気的に接続する配線基板の製
造方法にある。SUMMARY OF THE INVENTION The object of the present invention is to provide a wiring pattern on both surfaces of a substrate and to form wiring patterns on the both surfaces through a through hole. In a method of manufacturing a wiring board for electrically connecting the wiring, a desired portion of the board where a wiring pattern is formed is perforated, and a conductor separately formed is buried in the through hole to form the wiring on the both surfaces. The present invention relates to a method for manufacturing a wiring board for electrically connecting patterns.
【０００９】[0009]
【発明の実施の形態】本発明の実施例を図面を参照して
説明する。図面において、１は基板で、例えばガラス繊
維をベ−スとしてＢＴ（ビスマレイミドトリアジン）レ
ジン、エポキシ、又はポリイミドを含浸させたものが採
用される。該基板１には両面に予め貼着された金属箔か
ら配線パタ−ン２がエッチング技術により形成されてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. In the drawings, reference numeral 1 denotes a substrate, for example, a substrate made of glass fiber impregnated with BT (bismaleimide triazine) resin, epoxy, or polyimide. On the substrate 1, a wiring pattern 2 is formed by etching technology from a metal foil previously adhered to both surfaces.
【００１０】３は前記基板１を穿孔したスル−ホ−ル
で、前記配線パタ−ン２の所望箇所にレ−ザ−、ドリル
等で穿設されたものである。Reference numeral 3 denotes a through hole formed in the substrate 1 and is formed at a desired position of the wiring pattern 2 by a laser, a drill or the like.
【００１１】前記基板１の両面に形成された配線パタ−
ン２を電気的に接続するため、本発明では別途作成した
導電体４を前記スル−ホ−ル３に次のようにして埋設す
る。Wiring patterns formed on both sides of the substrate 1
In the present invention, a conductor 4 separately prepared is buried in the through hole 3 in the following manner in order to electrically connect the terminals 2.
【００１２】前記導電体４は例えばスル−ホ−ル３の内
径より若干小径の銅線材をレ−ザ−あるいは切断装置等
でカットして形成される。または、前記基板１と同等厚
みの例えば銅薄板５を図４に示すようなパンチ６とダイ
７を多数設けた金型装置８により打抜いて形成される。
打抜かれた導電体４を保持器９で受け取り保持し、該保
持器９を金型装置８外にへ移行して前記基板１のスル−
ホ−ル３に移し換え埋設する。あるいは前記カットした
導電体４を受け装置（図示しない）に収容し、前記スル
−ホ−ル３に埋設する。The conductor 4 is formed, for example, by cutting a copper wire having a diameter slightly smaller than the inner diameter of the through hole 3 with a laser or a cutting device. Alternatively, it is formed by punching, for example, a copper thin plate 5 having the same thickness as that of the substrate 1 by a mold apparatus 8 provided with a large number of punches 6 and dies 7 as shown in FIG.
The punched conductor 4 is received and held by a holder 9, and the holder 9 is moved out of the mold apparatus 8 to form a through hole of the substrate 1.
Transfer to hole 3 and bury it. Alternatively, the cut conductor 4 is stored in a receiving device (not shown) and embedded in the through-hole 3.
【００１３】導電体４の形成、及びスル−ホ−ル３への
埋設は、前記方法に限ることなく、導電体４をスル−ホ
−ル３に埋設し基板１の両面の配線パタ−ン２を電気的
導通させるのであれば、例えば導電性粉末からなる導電
体４を前記スル−ホ−ル３に埋設する等が適用できる。The formation of the conductor 4 and the embedding in the through hole 3 are not limited to the above-mentioned method, but the conductor 4 is embedded in the through hole 3 and the wiring patterns on both surfaces of the substrate 1 are formed. In order to electrically connect the through holes 2, for example, a conductor 4 made of a conductive powder may be buried in the through hole 3.
【００１４】埋設に際しては導電体４をスル−ホ−ル３
に押し込んで基板１の面より突出しないようにするとと
もに、該導電体４と配線パタ−ンの接触を密にすること
が好ましい。また必要によっては補助的に導電体４の上
面と配線パタ−ン２を半田等で接合させてもよい。At the time of burying, the conductor 4 is connected to the through-hole 3
It is preferable that the conductor 4 and the wiring pattern be in close contact with each other so that the conductor 4 does not project from the surface of the substrate 1. If necessary, the upper surface of the conductor 4 and the wiring pattern 2 may be joined together by soldering or the like.
【００１５】前記のようにして基板１の両面に形成され
た配線パタ−ン２が電気的に接続されるので、製造工程
は多岐にならず、また工程数も少なくなる。Since the wiring patterns 2 formed on both surfaces of the substrate 1 as described above are electrically connected, the manufacturing steps are not diversified and the number of steps is reduced.
【００１６】前記導電体４の埋設により両面の配線パタ
−ン２を電気的に接続した後、ソルダ−レジスト（図示
しない）が例えばスクリ−ン印刷により配線パタ−ン２
上に塗布され図３に示すような配線基板１０が製造され
る。After the wiring patterns 2 on both surfaces are electrically connected by burying the conductor 4, a solder resist (not shown) is formed by, for example, screen printing.
The wiring board 10 as shown in FIG.
【００１７】その後、図５に示すように前記配線基板１
０の一方の面には半導体チップ１１が搭載され、該半導
体チップ１１の端子と配線パタ−ン２がボンディングワ
イヤ−１２を介して接続され、基板１の他面には外部接
続端子の半田ボ−ル１３がランド（図示せず）を介して
配線パタ−ン２に接続して設けられる。Thereafter, as shown in FIG.
The semiconductor chip 11 is mounted on one surface of the semiconductor chip 11, the terminals of the semiconductor chip 11 are connected to the wiring pattern 2 via bonding wires 12, and the other surface of the substrate 1 is provided with solder terminals of external connection terminals. A wire 13 is provided connected to the wiring pattern 2 via a land (not shown).
【００１８】[0018]
【発明の効果】本発明によれば、前記のように基板の配
線パタ−ンを形成した所望箇所を穿孔し、該スル−ホ−
ルに別途形成した導電体を埋設して表面側の配線パタ−
ンと裏面側の配線パタ−ンを電気的に接続するので、製
造工程がシンプル化して配線基板を製造できる。また工
程が少なくなるので仕掛かり及び終り段階で不可避的に
生じる不良が無く、歩留りよく且つ生産性が高まり、製
造コストが低減する等の効果がある。According to the present invention, a desired portion of the substrate where the wiring pattern is formed is perforated as described above, and the through-hole is formed.
A separately formed conductor is buried in the wiring pattern on the front side.
Since the wiring pattern is electrically connected to the wiring pattern on the back side, the manufacturing process can be simplified and a wiring substrate can be manufactured. In addition, since the number of processes is reduced, there is no defect which is inevitably generated at the in-process and end stages, and there are effects such as good yield, high productivity, and reduction in manufacturing cost.
【図１】本発明の１実施例におけるスル−ホ−ルを穿設
した配線基板の側断面を示す図。FIG. 1 is a diagram showing a side cross section of a wiring board in which a through-hole is formed in one embodiment of the present invention.
【図２】本発明の１実施例におけるスル−ホ−ルに埋設
する導電体を示す図。FIG. 2 is a view showing a conductor buried in a through-hole according to an embodiment of the present invention.
【図３】本発明に１実施例においてスル−ホ−ルに導電
体を埋設した配線基板の側断面を示す図。FIG. 3 is a diagram showing a side cross section of a wiring board in which a conductor is embedded in a through hole according to one embodiment of the present invention.
【図４】本発明においてスル−ホ−ルに埋設する導電体
の形成を示す図。FIG. 4 is a diagram showing the formation of a conductor embedded in a through hole in the present invention.
【図５】本発明による配線基板を使用した半導体装置を
示す図。FIG. 5 is a diagram showing a semiconductor device using the wiring board according to the present invention.
１ 基板 ２ 配線パタ−ン ３ スル−ホ−ル ４ 導電体 ５ 銅薄板 ６ パンチ ７ ダイ ８ 金型装置 ９ 保持器 １０ 配線基板 １１ 半導体チップ １２ ボンディングワイヤ− １３ 半田ボ−ル DESCRIPTION OF SYMBOLS 1 Substrate 2 Wiring pattern 3 Through hole 4 Conductor 5 Copper thin plate 6 Punch 7 Die 8 Die apparatus 9 Cage 10 Wiring board 11 Semiconductor chip 12 Bonding wire 13 Solder ball
Claims (1)
もに、穿設したスル−ホ−ルを介して前記両面の配線パ
タ−ンを電気的に接続した配線基板の製造方法におい
て、前記基板に配線パタ−ンを形成した所望箇所を穿孔
し、該スル−ホ−ルに別途形成した導電体を埋設して前
記両面の配線パタ−ンを電気的に接続することを特徴と
する配線基板の製造方法。1. A method of manufacturing a wiring board, wherein wiring patterns are provided on both surfaces of a substrate, and the wiring patterns on both surfaces are electrically connected through perforated through holes. A wiring board formed by piercing a desired portion where a wiring pattern is formed, burying a separately formed conductor in the through hole, and electrically connecting the wiring patterns on both surfaces. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10189928A JP2000012737A (en) | 1998-06-19 | 1998-06-19 | Manufacture of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10189928A JP2000012737A (en) | 1998-06-19 | 1998-06-19 | Manufacture of wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000012737A true JP2000012737A (en) | 2000-01-14 |
Family
ID=16249565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10189928A Pending JP2000012737A (en) | 1998-06-19 | 1998-06-19 | Manufacture of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000012737A (en) |
-
1998
- 1998-06-19 JP JP10189928A patent/JP2000012737A/en active Pending
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