JP2000011638A - Semiconductor storage and memory access method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a power consumption from increasing and operating conditions from changing due to an address change, or to reduce the increase and the change thereof. SOLUTION: A coding address generator 71 for writing generates an address AI2 that changes successively according to a supplied clock CKI for writing and supplies AI2 to a memory core 1. A proper memory cell is accessed according to the AI2 by an address decoder 31 for writing in the memory core 1. In this case, a coded one is generated as the address AI2 by using the Gray code or the like so that the number of bits changing between adjacent addresses becomes smaller than an address due to a simple ascending order or the like. An address is generated by the similar coding based on a reading clock CKO also on reading. The Gray code is generated based on the count value of a clock due to the configuration of the combination or the like of an exclusive logic OR circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image memory,
In particular, the present invention relates to a memory core in a line memory, a field memory, a frame memory, and the like, a semiconductor storage device used in an image processing system, and a memory access method.

[0002]

2. Description of the Related Art In an image memory such as a line memory or a field memory or a frame memory, image data is written in the order of raster scanning, and image data is read out in that order. Here, a binary counter (hereinafter, referred to as a counter) is provided in the memory, and the count value of the counter is used as an address in the memory core.

The count value of such a counter is:
It is updated one by one by a method such as counting the clock for writing or reading together with the writing or reading of data. That is, in the memory core, input data is sequentially written according to the order of the addresses,
The written data is sequentially read.

[0004]

Incidentally, in a semiconductor memory, the larger the number of bits of an address whose logic changes when the address changes, the greater the possibility that problems such as an increase in power consumption and a change in various operating conditions may occur. Is high. That is,
At the same time, power consumption increases due to a change in logic in a larger number of circuits such as address buffers and address decoders, and changes in the potential of the power supply and the ground line change the operation such as noise margin and operation timing. Conditions change.

[0005] Alternatively, since there is an address skew in which the logic changes slightly for each bit, a transient logic change occurs in a circuit that originally has no logic change. Such transient logic changes increase power consumption and change operating conditions.

In order to compensate for changes in operating conditions and address skew as described above, a circuit design with a large margin is required. Thus, for example, if a design having a large timing margin is used, restrictions are imposed on achieving a high-speed operation, a high-frequency clock, and the like. Such a problem similarly occurs in the memory core in the image memory.

For this reason, in a large-capacity image memory having a high operating frequency, an image processing system using a large-capacity semiconductor memory having a high operating frequency, or a system having the same functions as those described above, the address change described above is performed. There was a need to eliminate the problems associated with this.

Accordingly, an object of the present invention is to prevent or reduce an increase in power consumption and a change in operating conditions due to a change in an address to be written or read. A semiconductor storage device and a memory access method are provided.

[0009]

According to a first aspect of the present invention, in a semiconductor memory device in which the order of data accessed in writing or reading is often fixed, the number of bits that change between adjacent codes is increased. A semiconductor memory device comprising coded address generating means for sequentially generating a write or read address by coding an address so as to reduce the number.

According to a third aspect of the present invention, there is provided a memory access method in a semiconductor memory device in which the order of data to be accessed in writing or reading is often fixed, a step of generating a sequentially changing write or read address, Receiving, and sequentially generating write or read addresses by encoding the addresses such that the number of bits changing between adjacent codes is smaller. is there.

According to the invention described above, the number of bits whose logic changes with an address change is reduced as compared with a case where the address changes in a simple ascending order (or descending order). Can be.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention, a commonly used image semiconductor memory will be described with reference to FIG. 1 for easy understanding. A clock CKI synchronized with the image data DI written in the raster scanning order is supplied to the writing counter 21. The write counter 21 counts the number of write clocks CKI, and generates an ascending address AI1 based on the count value. Then, this address AI1 is supplied to the memory core 1. The address AI1 is written by the write address decoder 31 in the memory core 1.
, An appropriate memory cell is accessed. The image data D is stored in the memory cells sequentially accessed in this manner.
I is written sequentially.

On the other hand, at the time of reading, a reading clock CKO with little jitter is supplied to the reading counter 22. The read counter 22 counts the number of read clocks CKO, and based on the count value, the address AO in ascending order.
Generates 1. Then, the address AO1 is supplied to the memory core 1. An appropriate memory cell is accessed in accordance with the address AO1 by the read address decoder 32 in the memory core 1. The written image data is read out as output data DO via the output buffer 5 from the memory cells sequentially accessed in this manner.

Here, addresses AI1, which are generated in ascending order,
In AO1, the number of bits whose logic changes between adjacent addresses has a width of at least 1 bit and a maximum of all bits constituting an address. Therefore, as the number of bits at which the logic changes increases, the likelihood of problems such as an increase in power consumption and changes in various operating conditions increases.

In view of the above, according to the present invention, the address which changes at the time of writing and reading data is set to a code (for example, a gray code, as will be described later) different from a simple ascending (or descending) order. , The number of bits whose logic changes with the number of bits is reduced, and in particular, the logic does not change over all bits forming the address.

Hereinafter, an embodiment of the present invention in which the present invention is applied to an image semiconductor memory will be described with reference to FIG. The same components as those of the example of the general image semiconductor memory described above with reference to FIG. 1 are denoted by the same reference numerals. A write clock CKI synchronized with the image data DI to be written is supplied to the write coded address generator 71. Coded address generator for writing 7
1 generates a coded address AI2 such that the number of bits whose logic changes in a sequentially changing address is always smaller than all bits, and supplies this AI2 to the memory core 1. An appropriate memory cell is accessed by the write address decoder 31 in the memory core 1 in accordance with the address AI2.

On the other hand, at the time of reading, a read clock CKO with little jitter is supplied to the read coded address generator 72. Coded address generator for reading 7
2 generates a coded address AO2 such that the number of bits whose logic changes in the sequentially changing address is always smaller than the total number of bits, and supplies this AO2 to the memory core 1. The read address decoder 32 in the memory core 1 accesses an appropriate memory cell according to AO2. The written image data is read out as output data DO via the output buffer 5 from the memory cells sequentially accessed in this manner.

A coded address generator which can be used as the coded address generator 71 for writing and the coded address generator 72 for reading will be described with reference to FIG. Such a coded address generator includes a counter 2 and a coder 8 that generates a coded address based on the count value generated by the counter 2.

It is preferable that the coder 8 generates a gray code in which a logical change of only one bit always occurs for a count value that changes by one. However, the present invention is not necessarily limited to the gray code, and can reduce the number of bits whose logic changes as compared with a case where an address is specified in a simple ascending order (or descending order) using a count value. If so, another code may be used.

The gray code will be described in more detail with reference to FIG. FIG. 4 shows a change in address according to a change in the number of clocks for a count value and a gray code in 4 bits. Here, the underlined bits are bits whose logic has changed in the count value or Gray code corresponding to a certain number of clocks as compared to the count value or Gray code for the previous number of clocks. For example, when the number of clocks is 0 → 1, the count value is' 0
000 '→' 0001 ', so only the first digit at the right end is'
0 '→' 1 '. Therefore, the rightmost '1' is underlined.

When the number of clocks is 1 → 2, the count value is “0001” → “0010”.
The digit changes from '01' to '10'. Therefore, the two digits '10' from the right are underlined. Similarly, the number of clocks 1 → 2
In this case, the gray code changes from '0001' to '0011', so that only the second digit from the right changes from '0' to '1'.
Therefore, the rightmost '1' is underlined.

From FIG. 4, when the number of clocks 1 changes,
It can be seen that the count value changes by a maximum of all bits (four digits in this example), while the gray code always changes by only one bit. That is, when the Gray code is used, the number of bits whose logic changes between adjacent codes is always 1 bit.

FIG. 5 shows an example of a configuration for generating a gray code as shown in FIG. 4 based on the count value. One such example is a more specific example of the coded address generator shown in FIG. The counter 2 has a register for four digits, and generates a count value in accordance with the supplied clock. The encoder 8 has three exclusive OR circuits 81, 82 and 83. And L of the counter 2
The SB (Least Significant Bit) and the register value of the second digit from the LSB side are supplied to the exclusive OR circuit 81,
The register values at the second and third digits from the SB side are supplied to the exclusive OR circuit 82, and further, at the third and fourth digits from the LSB side (that is, MSB (Most Significant).
Bit)) is supplied to the exclusive OR circuit 83.

The MSB of the counter 2 is directly used as the output value of the encoder 8. The output value is set to the MSB, and the subsequent digits are set to the output values of the exclusive OR circuits 83, 82, and 81, respectively (therefore, the output value of the exclusive OR circuit 81 is set to the LSB). Thus, a 4-digit Gray code can be generated.

It should be noted that the above-described embodiment of the present invention
As shown in FIG. 2, the present invention is applied on the premise of an image memory having one read / write port. On the other hand, the present invention can be applied assuming a different configuration, for example, an image memory having two reading ports.

Further, the present invention can be applied not only to the image memory itself but also to a component relating to a function of designating an address to be accessed in the image memory in the image processing system. .

Furthermore, the present invention can be applied to data other than image data when the order of data to be accessed in writing and / or reading is constant.

[0028]

As described above, the present invention is used as an image memory such as a line memory, for example, in which image data is written in the order of raster scanning, and image data is often read out in the order of the raster scanning. At the time of memory access in a semiconductor memory device, coding is performed using a gray code or the like so that the number of bits that change between adjacent codes is reduced, so that addresses to be written or read are sequentially determined. That is what happens.

As a result, the number of bits whose logic changes with a change in address can be reduced as compared with a case where addresses are expressed in a simple ascending order (or descending order). Therefore, it is possible to prevent or reduce problems such as problems such as an increase in power consumption and a change in various operating conditions due to a change in logic for a large number of bits.

This eliminates the need to design a circuit with a large margin to compensate for changes in operating conditions, address skew, and the like, thereby reducing restrictions in increasing the speed of operation and increasing the frequency of clocks. Can be contributed to.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an example of a commonly used image semiconductor memory.

FIG. 2 is a block diagram for describing an embodiment of the present invention.

FIG. 3 is a block diagram for describing in detail a partial configuration of an embodiment of the present invention.

FIG. 4 is a schematic diagram for explaining a gray code.

FIG. 5 is a block diagram showing a more specific configuration example of a part of the configuration of the embodiment of the present invention shown in FIG. 3;

[Explanation of symbols]

31 ... Write address decoder, 32 ... Read address decoder, 71 ... Write coded address generator, 72 ... Read coded address generator

Claims (3)

[Claims] In a semiconductor memory device in which the order of data to be accessed in writing or reading is often fixed, addresses are encoded so that the number of bits that change between adjacent codes is reduced. And a coded address generating means for sequentially generating a write or read address. 2. The semiconductor memory device according to claim 1, wherein said coded address generating means performs coding for generating a gray code. 3. A memory access method in a semiconductor memory device in which the order of data to be accessed in writing or reading is often fixed, a step of generating a sequentially changing write or read address; A memory access method, comprising the step of sequentially generating write or read addresses by encoding said addresses so that the number of bits that change between adjacent codes is smaller.