JP2000010959A - Processor and method for multiplying and accumulating operation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform fast multiplying and accumulating matching the IEEE 754-1985 standards by determining a rounded value needed to generate a final multiplying and accumulating result equivalent to individual multiplication instructions in which rounding is embedded and individual addition instructions in which following rounding is embedded. SOLUTION: The processor is equipped with a multiplier 120 which generates an unrounded multiplication result by multiplying two values by each other and further generates 1st data needed to determine rounding. Similarly, the processor is equipped with an adder which generates an unrounded multiplying and accumulating operation result by adding a specific value to the unrounded result and further generates 2nd data needed to determine rounding. The decision logic 150 uses the 1st and 2nd data to determine a rounding value needed to generate the final multiplying and accumulating operation result equivalent to the execution of individual multiplication instructions wherein rounding is incorporated and individual addition instructions wherein following rounding is incorporated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and method for performing a multiply-accumulate operation.

[0002]

2. Description of the Related Art Generally, a data processing device is required to execute various floating point operations on data. To ensure that such floating point calculations can be handled in a consistent manner on various data processing devices, one standard is 1985, "IEEE Standard for Binary Floating Point Arithmetic", ANSI / IEEE Standard 754-19.
85, established by the Institute of Electrical and Electronics Engineers (IEEE), New York, 10017 (hereinafter referred to as the IEEE 754-1985 standard). The standard stipulates, among other things, that a multiplication operation should end with a rounding operation, and that an addition or accumulation operation should also end with a rounding operation.
This IEEE 754-1985 standard further defines the IEEE 7
It also provides a definition of the number of rounding operations that are considered to conform to the 54-1985 standard.

[0003] General purpose processors are known to be incompatible with floating point computational performance, and therefore require special floating point units (FPs) to handle such computations.
U) has been developed.

[0004] One of the special floating point calculations generally required is a multiply-accumulate operation, in which two numbers are multiplied together and the product is added to a third number. The multiplication / accumulation operation is not specifically discussed in the IEEE 754-1985 standard, and the multiplication and the accumulation operation are separately discussed. Of course, the multiplication / accumulation operation can be realized by executing another accumulation instruction following the multiplication instruction.
Such an approach is relatively slow.

[0005] Accordingly, there is a great interest in developing FPUs specially configured to perform multiply-accumulate operations at high speed. One example of such an FPU is US-A-
No. 4,969,118, which describes an FPU for performing multiply-accumulate operations developed by IBM. According to the IBM technology, the partial multiplier is 2
A partial product of the two numbers is generated, and the partial product is sent to an adding circuit and added to the third number. Therefore, the multiplication / accumulation operation is “fused”, and the result of the multiplication is not determined separately before the accumulation operation. This method dramatically increases the speed of the multiplication / accumulation operation.

Further, the multiplication is performed with an internal precision that includes all the bits from the multiplication (2n bits for n * n bit multiplication), and then the accumulation is performed using all of the multiplication bits. This gives a particularly accurate result, since the result of the multiplication has not been rounded before it is used in subsequent accumulations. However, this technology is IEEE
It does not conform to the E754-1985 standard, since this standard specifies that rounding operations should be performed on multiplication results.

To increase the speed of multiplication / accumulation operation and /
Another example of a FPU specifically designed to reduce circuit complexity is US Pat. No. 5,241,493, U.S. Pat.
SA-5,375,078, US-A-5,53
0,663 and EP-A-0,645,699,
US-A-4,866,652 and US-A-4,
841,467. None of these documents mention rounding, especially none of the IEs
There is no interest in calculating results that meet the EE754-1985 standard.

[0008] An alternative approach used in the MIPS R10000 product is to maintain the multiplier and adder as separate logic units. In performing the multiply-accumulate operation, rounding is applied to the output of the multiplier unit and subsequently to the adder logic unit, the result of which is also rounded. This is IE
Although a result conforming to EE 754-1985 can be obtained for a multiply / accumulate operation, the speed advantage obtained from a special logic unit specially configured to execute the multiply / accumulate operation cannot be secured.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to execute individual multiply instructions incorporating rounding while efficiently performing multiply and accumulate operations in response to a single instruction, followed by rounding. To provide a data processing apparatus and method capable of obtaining a result equivalent to executing an addition instruction in which is incorporated.

[0010]

Accordingly, the present invention provides a data processing apparatus for executing a multiply / accumulate operation A + (B * C) in response to a single instruction for identifying the multiply / accumulate operation. A single multiplier configured to multiply the values B and C to produce a non-rounded multiplication result, and further to generate the first data required to determine the rounding; An adder configured to add the unmultiplied result to the value A to produce an unrounded multiplied accumulated result, and further to generate second data required to determine rounding; And using the second data to produce a final multiply-accumulate result equivalent to executing a separate multiply instruction with rounding followed by a separate add instruction with rounding. One or more And determination logic for determining the fit value;
And rounding logic for providing one or more rounded values to generate a final multiply / accumulate operation result.

According to the present invention, there is provided a multiplier for generating an unrounded multiplication result by multiplying the values B and C, and for generating first data necessary for determining the rounding. ing. Similarly, an adder is provided for adding the value A to the non-rounded result to generate an unrounded multiplication / accumulation result, and for generating second data necessary for determining rounding. I have. next,
The decision logic uses the first and second data to perform a final multiplication instruction equivalent to executing a separate multiply instruction with rounding followed by a separate add instruction with rounding.
It is configured to determine one or more rounding values required to generate the cumulative operation result.

In this manner, IEEE 754-19
It is possible to provide a dedicated multiplication / accumulation logic capable of generating a result conforming to the 85 standard and executing a multiplication / accumulation instruction at high speed.

In one embodiment, the decision logic can be configured to determine a plurality of round values provided at appropriate steps during the addition operation. However, in the preferred embodiment, the decision logic is applied to the unrounded multiply-accumulate result by the rounding logic and is configured to generate a single rounded value to produce the final multiply-accumulate result. This method further improves the execution speed of the multiplication / accumulation operation.

In a preferred embodiment, the first data generated by the multiplier includes guard and sticky bits, and the decision logic includes first logic for determining a multiplier round value from the first data. Further, the first data preferably includes the least significant bit of one or more multiplication results, which is also used in generating the multiplier rounding value. In such a preferred embodiment, the decision logic further includes second logic for determining one or more rounded values from the multiplier rounded value and the second data.

In a preferred embodiment, the adder aligns the value A with the smaller of the multiplication results before performing the addition.
er) and a detection unit for detecting whether the bits shifted out by the alignment shifter are all ones or all zeros. In this embodiment, the second data generated by the adder preferably includes guard and round bits and the output of the detection unit.

It will be apparent that the multiplier can be configured in a number of ways. However, in the preferred embodiment, the multiplier includes a multiply unit for producing a partial result in carry-save form and a product adder for producing the multiplied result. Further, the multiplier is preferably a glue adder for adding together a group of least significant bits of the partial product generated by the multiply unit, and a guard and glue bit for generating a guard and glue bit from the output of the glue adder. And a generator.

As will be appreciated, the final multiply-accumulate result can be generated using one or more rounding values in a number of ways. In a preferred embodiment,
The values A, B and C consist of a mantissa and an exponent, which are treated separately. Therefore, in the submitted example,
The unrounded multiply-accumulate result includes the mantissa and the exponent, the data processing device further includes an incrementer for incrementing the mantissa, and the rounding logic determines whether the mantissa or the incremented mantissa is the final. A multiplexer for outputting as a result of the multiplication / accumulation depending on one of the one or more rounded values generated by the decision logic. In such a preferred embodiment, one rounded value preferably includes a final increment signal input to the multiplexer, which indicates whether the mantissa or the incremented mantissa is to be output as the final mantissa. .

As will be appreciated, an overflow condition can occur when updating the mantissa. To illustrate this, the rounding logic preferably includes exponent updating logic for incrementing the exponent if the result of further incrementing the mantissa overflows, and the incremented mantissa is selected as the final mantissa.

In a preferred embodiment, the decision logic includes a first converter, which receives the second data generated by the adder and performs the operation on the unrounded multiply-accumulate result. To compensate for the right shift normalization. Further, the decision logic is preferably configured to determine a multiplier round value from the first data, and the decision logic preferably further provides a multiplier round value to an output of the first converter circuit. Including vessel. In such an embodiment, the decision logic preferably further comprises a third converter, which applies a predetermined rounding formula to the signal output from the second converter, and applies one or more rounding values. Generate

In view of the second aspect, the present invention provides a method for performing a multiply / accumulate operation A + (B * C) in response to a single instruction identifying the multiply / accumulate operation, This involves: multiplying the values B and C to generate an unrounded multiplication result, and generating the first data required for the rounding decision; adding the unrounded multiplication result to the value A and rounding. Generating a multiplication-accumulation result that is not rounded and generating second data required for the rounding decision; using the first and second data to execute a separate multiplication instruction incorporating rounding, followed by rounding. Determining one or more rounding values required to produce a final multiply-accumulate result equivalent to executing the embedded individual add instruction; and
Apply one or more rounding values to generate the final multiplication / accumulation result.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be further described, by way of example only, with reference to the submitted embodiment illustrated in the accompanying drawings, in which: FIG.

FIG. 1 illustrates a data processing system 22;
It includes a main processor 24, a floating point unit (FPU) coprocessor 26, a cache memory 28, a main memory 30, and an input / output system 32. Main processor 24, cache memory 28, main memory 30, and input / output system 32
Are linked via the main bus 34. Coprocessor bus 36 links main processor 24 to floating point unit coprocessor 26.

In operation, the main processor 24 (also A
RM core) executes a stream of data processing instructions that control general types of data processing operations, including interaction with cache memory 28, main memory 30, and input / output system 32. Coprocessor instructions are embedded in the stream of data processing instructions. Main processor 24 recognizes these coprocessor instructions as being to be executed on an attached coprocessor. Accordingly, main processor 24 issues these coprocessor instructions on coprocessor bus 36, from which they are received by the associated coprocessor. In this case, FPU coprocessor 2
6 accepts all received coprocessor instructions and executes as detected what is intended. This detection is performed via a coprocessor number field in the coprocessor instruction.

FIG. 2 is a block diagram illustrating the FPU coprocessor 26 of FIG. 1 in more detail. As shown in FIG. 2, FPU 26 includes a datapath component block 160 for performing floating point operations, a coprocessor interface 180 for interfacing with main processor 24 via coprocessor bus 36, and, in particular, a floating point It has a register file 170 for storing input values for the decimal point operation and results of the floating point operation.

Floating point instructions are sent from the main processor to the FPU
26, this is received at the coprocessor interface 180, which indicates that the floating point
Then, it is determined whether or not processing can be performed in step 6. Thus, if for some reason the datapath component block 160 cannot start executing the new instruction when the new instruction is received, then the coprocessor interface 180 notifies the main processor. However, if the coprocessor interface 180 determines that the instruction can be executed, it generates a control signal and sends it to the datapath component block 160 to initiate a floating point operation.

Before executing the floating-point operation, the input value for this operation is transferred to the register file 17 via the data bus.
Passed through 0. Next, the coprocessor interface 180
Sends a control signal to the register file 170 to store this input value in the appropriate source register.

When the floating point operation is started, the contents of the source register are output from register file 170 to datapath component block 160. Further, when the floating point operation is completed, the result is sent from the data path component block to the register file 170 for storage in the appropriate destination register.

FIG. 3 is a block diagram illustrating data path component block 160 of FIG. 2 in more detail. The data path component block 160 includes the data path logic 100 and the control circuit 110. Data path logic 1
00 has a multiplier 120 for multiplying the values B and C to generate a multiplication result and an adder 130 for adding the value A to the multiplication result. Further, rounding logic 140 is provided for rounding the value of the multiply-accumulate result which is the output of adder 130.

The control circuit 110 includes data for identifying an instruction (for example, addition, multiplication, or multiplication / accumulation) to be executed by the FPU 26 and inputs for operation (for example, A and B).
And C) to control the operation of various logic components within datapath logic 100 by sending various control signals to datapath logic. Further, at various points in the data path, the data path logic is configured to provide signals to the control circuit, which are used to generate the appropriate control signals at the control circuit. These signals are shown in FIG.
This will be described in more detail later with reference to FIG.

For simplicity, only the signaling between the data path and control logic involved in rounding is illustrated in FIGS. Thus, multiplier 120 sends the first data signal needed for the rounding decision to decision logic 150 in control circuit 110, and similarly, adder 130 sends the second data signal needed for the rounding decision to decision logic 150. provide. The decision logic 150 then uses these data signals to generate a rounding value and outputs it to the rounding logic 140 in the data path logic 100. Subsequently, the rounding logic 140 uses the rounded value to generate a final multiply-accumulate result.

As will be described in more detail below, the decision logic incorporates a separate multiply instruction whose rounding / accumulation result incorporates rounding, followed by rounding when the rounded value is provided by rounding logic 140. It is configured to generate a rounded value so as to guarantee that the result obtained by executing the individual addition instruction is equivalent to the result.

According to a preferred embodiment of the present invention, FP
U26 is a floating point multiplication / accumulation chain (FMAC: floating
point multiply-accumulate chained) operation, where the multiply-accumulate operation is performed with effective rounding between multiplication and accumulation. In the preferred embodiment, a four-stage pipeline having execution stages E1 to E4 is employed. In the submitted embodiment, the operations performed at each stage during the multiplication / accumulation operation are as follows: E1: The mantissa of the multiplier (Mant (C)) and the multiplicand (Mant (B)) Multiply and produce a result in verbose form. • Sum the multiplier and multiplicand indices to form the product index. • Compare this with the exponent of the augend, select the operand with the larger augend or product, and calculate the shift number for the smaller operand. E2:-The two parts of the multiplication result are summed to make a non-redundant format. Connect the smaller of the augend and the product to the register connected to the alignment shifter. -The larger of the augend and the product is determined by using the augend invert multiplexer (augment negative multiple).
xer) to the register connected to it. Calculate whether the product needs to be incremented for correct rounding. E3: Shift the smaller of the product to be added and the product, and align them with the larger number of addition. -When the operation is a substantial subtraction, the addend is inverted.・ Add the smaller number and the larger number. E4: Calculate the position of the leading 1 and 0 in the total value.・ Calculate whether rounding is necessary from multiplication rounding calculation and addition rounding calculation. -If necessary, increment the total value. -Normalize the total value. Calculate the final exponent and increment the exponent if the sum overflows during calculation or rounding.

The FMAC architecture outlined above is consistent with the IEEE 754-1985 standard and is similar to performing floating point multiplication followed by floating point addition together rounded together using the same rounding mode. Produces matching results at the bit level. The total number of cycles in the FMAC architecture is based on the prior art IBM
Only one greater than the approach, while maintaining throughput one cycle per operation for single precision operations and two cycles per operation for double precision.

In the preferred embodiment of the present invention, the data path logic 1 used to implement the FMAC described above
00 is described in more detail with reference to FIGS. 4 to 7 illustrate the components of the data path logic used to process the mantissa of the input value, while FIGS. 8 and 9 are used to process the exponent of the input value. FIG. 3 illustrates the components of the data path logic.

FIG. 4 illustrates the processing performed on the mantissa during stage E1 of the pipeline. The mantissas of the values B and C are input to a multiplier 200, which may be of any known design, and which is configured to multiply the values B and C by one another to produce a product in carry-preserve format. Have been. The total data is output to the register 230, and the carry data is output to the register 240. On the other hand, the mantissa of the value A is passed directly to the register 210. The mantissa of value B is also output to register 220 to perform a simple addition of A and B.

FIG. 8 illustrates the processing performed on the index during stage E1 of the pipeline. The exponents of the values B and C are input to a product exponent adder 600, which adds them here to produce a product exponent, which is an exponent select multiplexer 61.
Output to 0. The product exponent is also provided to multiplexer 640, which receives the exponent of value B as a second input. Multiplexer 640 is configured to receive the sum exponent select signal from control circuit 110, which controls which input is output from multiplexer 640. Since control circuit 110 receives data identifying the type of operation to be performed, it generates an addend exponent select signal and multiplexer 640 selects the exponent of value B if a simple add operation of A and B is to be performed. Alternatively, when a multiplication / accumulation operation is performed, a product exponent may be selected.

The output from the multiplexer 640 is passed to an adder 630, which is also configured to input the exponent of the value A as a second input, inverted by an inverter 620. Since the exponent of value A is inverted, adder 630
Operates as an exponent subtractor, and thus a signal on path 655 that identifies the difference between the two input exponents (hereinafter ExpD
iff signal). Further, adder 630 is configured to output a signal on path 650 indicating whether the exponent of value A is less than the other input exponents.
This A_Smaller signal is passed to the control circuit along with the ExpDiff signal and used by the control circuit to generate subsequent control signals for data path logic.

The exponent select multiplexer 610 receives three inputs, an A exponent, a B exponent, and a product exponent. The purpose of the exponent select multiplexer 610 is to select the largest exponent associated with the operation to be performed. The exponent selection multiplexer 610 is controlled by a control signal generated by the control circuit 110. Since the control circuit knows which operation is to be performed and has received the A_Smaller signal from adder 630, this is the exponent select multiplexer 610.
It has all the information needed to determine which of the three inputs to is to be output. Thus, when a pure addition operation is performed, the ExpMuxSelect signal indicates which of the A exponent or the B exponent should be output based on which is greater (as indicated by the A_Smaller signal). ExpMuxSelect if a pure multiply operation is performed
Let the signal select the product exponent. Finally, when a multiply-accumulate operation is performed, the ExpMuxSelect signal indicates which of the A exponent or the product exponent should be output based on which is greater.

As shown in FIG. 9, the output from exponent select multiplexer 610 is passed to register 670.
At pipeline stages E2 and E3, this output value is simply passed to registers 680 and 690, respectively.

FIG. 5 illustrates the mantissa processing performed in stage E2 of the pipeline. The sum and carry data from registers 230 and 240, respectively, is such that the most significant bit of the sum and carry data is sent to product adder 250 and the least significant bit of the carry and stored data is sent to attachment adder 260, respectively. Is separated into

The inputs to the attachment adder 260 are added together and output to the guard and attachment bit generator 270.
The guard and sticky bits determined by generator 270 are then output on path 280 to control circuit 110. When the result of the addition to the attachment adder 260 overflows, the overflow bit is passed over path 265 to product adder 250. The inputs to the product adder are added together to generate a product P taking into account all overflow bits received via path 265. The product P at this stage
Is not rounded and is not normalized.

The product P is provided to an addend multiplexer 320 and an addend multiplexer 330, which are also configured to receive the mantissas of the values A and B from registers 210 and 220, respectively. The number of least significant bits of the product P, bits 0 and 1 in the preferred embodiment, is output over 275 to control circuit 110. As will be appreciated by those skilled in the art, based on the least significant bit output on path 275 and the guard and sticky bits output on path 280, the control circuit determines whether the multiplication result P should be rounded. The rounding value that indicates
MulRound). However, although the control circuit generates the MulRound, no rounding is performed at this stage in the preferred embodiment.

In addition, the Movfl signal is output on path 285 for later use by the control circuit during rounding, and the Movfl signal has a logic 1 value if the output of product adder 250 overflows. If the output of the product adder 250 does not overflow, it has a logical 0 value.

The addend multiplexer 320 and the addend multiplexer 330 control signals, that is, the large selection (L_
Sel) and a small selection (S_Sel) signal, respectively, and these signals are generated by a control circuit. Since the control circuit knows which operation is being performed and has received the A_Smqller signal from adder 630, the control circuit 3
It has all the information needed to determine which of the two inputs should be output. When a pure addition operation is performed, the L_Sel signal causes the augend multiplexer 320 to select the larger of the values A and B (A_ derived from the exponent).
S_Sel, on the other hand, causes the adder multiplexer 330 to select the smaller of the values A and B, as indicated by the Smaller signal). When a pure multiplication operation is performed, the L_Sel signal causes the product P to be selected by the augend multiplexer while the S_Sel
The signal causes the adder multiplexer to output a zero value. Finally, if a multiply-accumulate operation is performed, the L_Sel signal causes the augend multiplexer 320 to select the larger of the values A and P (as indicated by the A_Smaller signal derived from the exponent), while S_Sel is Addition number multiplexer 33
0 causes the smaller of the values A and P to be selected. The outputs from addend multiplexer 320 and addend multiplexer 330 are then stored in registers 350 and 360 for later use in stage E3 of the pipeline.

FIG. 6 illustrates the mantissa processing performed in stage E3 of the pipeline. The smaller value stored in register 360 is passed to an alignment shifter 390, where it is shifted to be aligned with the larger value. This is achieved by the control circuit 110 providing the ShiftCount value to the alignment shifter 390 via the path 395.
The ShiftCount value is calculated by the control circuit 110 using the ExpDiff signal output by the data path logic 100 during exponential processing at stage E1 of the pipeline.

Alignment shifter 3 placed on path 420
The output of 90 consists of the aligned smaller value, the guard bit and the rounding bit. The guard bits and the rounding bits are passed on path 425 to control circuit 110, while the aligned smaller values are passed on path 430 to sum adder 450. In addition to the output on path 420, alignment shifter 390 also outputs on path 400 the bits that have been shifted out during the shifting process. These bits are input to logic 405, which determines whether the bits are all zeros or all ones. If each bit shifted out was zero, a logical 1 value is passed to path 4
A logic one value is output on path 415 if each bit shifted out was one while one was output one. These values are used in control circuit 110 along with the guard and round bit outputs on path 425 to determine rounding, as described in more detail below.

The larger value stored in register 350 in the middle of stage E2 is passed to multiplexer 380, along with an inverted version of that value inverted in inverter 370. The control circuit 110 determines that the cumulative logic is “addition of different signs” (USA: like signed ad) from the instruction and the sign of various input signals.
d), for example, determine whether to execute XY. In that case, the control circuit outputs an augend inversion signal having a logical value of 1, and causes the multiplexer to select the inverted larger value. Otherwise, the augend inverted signal has a logical value of 0, causing the multiplexer to select the larger value that is not inverted.

The output from multiplexer 380 is route 4
Above 40 is passed to sum adder 450 where it is added to the aligned smaller value. When the USA is executed, the AddCarryIn signal generated by the control circuit 110 is set to a logical 1 value and input to the sum adder 450. This is necessary to ensure that the correct two's complement of the larger value is used in the addition (the two's complement represents the negative state of the larger value). X mentioned above as an example
Considering -Y, this is equivalent to-(-X + Y),
The sum adder can be considered to perform the sum -X + Y. The output of sum adder 450 is then passed to register 455 for later use in stage E4 of the pipeline. Further, the least significant bits L [0], L [1] and L [2] are routed 452
Is output to the control circuit 110 and used later in determining rounding.

FIG. 7 illustrates the mantissa processing performed in stage E4 of the pipeline. The value stored in register 455 is passed to a normalizing shifter 457, which performs a right shift on the output of the sum adder if necessary.
Such USA and the same sign addition (LSA: Like Signed Ad)
d) For operations, the output of the sum adder can overflow and its output value needs to be shifted right by one or two bits to normalize the output (effectively shifting the decimal point to the left ). Accordingly, the control circuit is configured to determine from the output of sum adder 450 whether such an overflow has occurred and to generate a control signal that causes the alignment shifter to perform the appropriate shift of the output.

The value stored in register 455 is also passed to logic 480, where the leading zeros and leading ones are determined. This is because the USA operation is taken into consideration, and this operation may cause a cancellation that needs to be shifted left in order to normalize the output value of the sum adder 450. The position of the leading zero is output on the path 485 to the control circuit 110, and the position of the leading zero is on the path 4
The data above 90 is output to the control circuit 110. These signals are used in the control circuit to determine the NormShiftCount signal, which is used later in normalizing the mantissa. This NormShiftCount signal identifies the number of bit positions where the mantissa should be shifted left to account for any cancellations due to the UAS operation.

The output of the alignment shifter 457 is output to the inverter 46.
The value, which has been inverted by 0, is passed to multiplexer 465 together with the inverted version. The control circuit 110 evaluates whether or not the output of the adder 450 is negative.
The sult Negative control signal is sent on path 470 to a multiplexer 465 having a logical value of one. This causes multiplexer 465 to select the inverting input received from inverter 460. Otherwise, the non-inverting input received directly from register 455 is selected.

The output of the multiplexer 465 is supplied to the updater 50.
0 is passed to the rounding select multiplexer 510. Rounding select multiplexer 510 also receives the output of updater 500 and selects one of the two inputs and outputs it to normalizer 520 in response to the final increment signal passed on path 515 from control circuit 110. I do. The control circuit 110 provides paths 410, 415, 425 and 452 from the MulRound generated in stage E2 and between stages E3 of the pipeline.
The value of the final increment signal is determined from the various signals output above. The generation of the final increment signal in the control circuit 110 will be described later in detail.

The normalizer 520 receives the output from the rounding selection multiplexer 510 and receives the output from the NormShiftCount described above.
Perform all normalizations of the output as determined in.
The output from normalizer 520 is then stored in register 530 as the mantissa of the final result.

FIG. 9 illustrates the exponential processing performed in stage E4 of the pipeline. The exponent value stored in register 690 is input to exponent adjust adder 700, which also receives the output of multiplexer 710 as a second input. The multiplexer 710 is controlled by an ExpAdjust signal output from the control circuit 110, and this signal is output to any one of the four inputs to the multiplexer 710.
Indicates whether it should be output to 0. Thus, if a left shift of the mantissa is performed at stage E4 based on NormShiftCount, the ExpAdjust signal outputs the inverted NormShiftCount signal to the exponent adjustment adder 700 by multiplexer 710, and the exponent is inversely related to the mantissa. Let them adjust. Similarly, if, instead, the exponent was shifted right by shifter 457 during stage E4 of the pipeline,
The ExpAdjust signal causes multiplexer 710 to select the appropriate adjustment for the exponent. Therefore, for example, when the mantissa is shifted one bit to the right, the multiplexer 7
10 outputs a value of 1 and increments the exponent by 1.

The output of exponent adjustment adder 700 is passed to exponent updater 720 and final exponent select multiplexer 730. The final exponent select multiplexer 730 also receives the output from the exponent updater 720 and
Controlled by the nalExpSel signal, it determines which value to output to register 740 as the exponent of the final result. If the incremented mantissa overflows and is selected by the rounding selection multiplexer 510 shown in FIG. 7, the FinExpSel signal is driven high and the multiplexer 7
Let 30 select the incremented index. It should be noted that at this point the mantissa overflow has not been taken into account in the first normalization performed by the normalizer 520, and therefore the mantissa is not shown in FIG. Following normalization, it handles all overflows caused by incrementing the mantissa.

Having described the data path logic 100 in detail, the decision logic 150 used to generate the rounding value in the control circuit 110 will now be described. The rounding decision performed by the decision logic is performed by multiplying the seven signals generated in the stage E3 of the pipeline by the MulRound generated by the decision logic in the stage E2 indicating whether the multiplication result P should be rounded or not.
Used with the signal to calculate the final rounding that needs to be performed on the result. The seven signals from stage E3 are: The guard (G) and round (R) bits output on path 425 as a result of the alignment shift performed by shifter 390. AllO output on paths 410 and 415, respectively
nes or AllZeros signals, these signals are
This is the result of checking the bit shifted out at 90. AllOnes means that all bits shifted out are 1
Holds, while AllZeros holds when all bits shifted out are zero. Neither holds if the shifted out bit contains both 1s and 0s. L [2], L [1], and L [0] on path 452
On output, these signals are the lower three bits of the sum output of sum adder 450.

FIG. 10 illustrates the decision logic 150 provided in the control circuit 110 in more detail. It includes a first converter 800 for receiving the above seven signals generated during stage E3 of the pipeline. The first purpose of the first converter 800 is to compensate for any normalization that requires a right shift performed during stage E4 of the pipeline. It is only necessary to provide a right shift of only one and two bits as described above. First converter 800
Output from the intermediate least significant bit (IL) and guard (I
G), rounding (IR) and sticking (IS) bits;
These are input to a second converter 810, whose values are determined based on the following table:

[0058]

[Table 1]

In the above table and hereafter, the term Inv (X)
Is used to represent the inverted value of X, while OR and AND represent logical OR or logical AND functions.

The intermediate rounding bits are further processed in a second converter 810, which converts the MulRound value, all two's complements required in negating the sum output of sum adder 450 (such negation is controlled by a control circuit). (Selected by the ResultNegative signal driven high), and incorporates three valid signals.

The valid signal is true if the alignment operation performed by shifter 390 produces respective rounded bits, and false if the alignment does not generate individual bits. This is specifically shown in the following table by taking a double-precision operation as an example (the output of the product P from the product adder 250 is 1.x
True (that is, 1) when the format is 1x.yyy instead of yyy. GV is true if valid G bits are returned from the alignment shift operation. RV and SV are also true if the valid R and S bits are returned from the aligned shift bit operation. ):

[0062]

[Table 2] The output of the second converter 810 is the final least significant bit (FL),
Guard (FG), round (FR) and stick (FS) bits, which are input to the third converter 830. These last bits are further processed in a third converter 830,
The IEEE 754-1985 rounding formula is FL, FG, FR,
Generate a rounding value (used as the final increment signal input to rounding select multiplexer 510 in stage E4) by applying to the FS and forced update (FI) bits. The output of the third converter is the data path logic rounding logic 140, which is used to round the final result.

As will be appreciated by those skilled in the art, there are two different cases of floating point addition, homo-sign addition and hetero-sign addition. Same sign addition (LSA: like-
In the case of a signed addition, the signs of the input operands are equal for an addition operation and opposite for a subtraction operation. Different sign addition (USA: unlike-si
In the case of gned addition, the sign is opposite for addition and equal for subtraction. The following cases are distinguished by either LSA or USA operation.

As described above with reference to FIGS. 4-9, the determination of the 'smaller' operand or the 'larger' operand is accomplished by comparing the exponents with the operand having the smaller exponent. This is done by showing the other operand as 'larger'. The larger operand is called the augend, while the smaller operand is called the addend.

The second converter 810 considers six cases: Case 1: LSA, small product Case 2: LSA, large product Case 3: USA, small product, the result is positive Case 4 : USA, product is small, result is negative Case 5: USA, product is large, result is positive Case 6: USA, product is large, result is negative

Case 1: LSA, when the product with a small product is MAC, there are two cases based on the MulRound bit. If the operation is not a MAC, MulRound
The bit is 0. For both cases, the FL bit is set to the value of IL.

[0067]

(Equation 1)

The valid signals (GV, RV and SV) are not needed in this case. If not valid, the rounding bit is zero and is correctly incorporated into the rounding expression.

MulRound = 1 This case requires valid signals (GV, RV, and SV).

[0070]

[Table 3]

The S bit is valid (G and R need not be valid; they are zero if not valid).

[0072]

[Table 4]

Case 2: LSA, MulRound bit with large product is incorporated in the AddCarryIn signal passed to sum adder 450 on path 445. MulRou
nd is forcibly set to 0 in the rounding of stage 4 and has no effect.

The fourth rounding bit is: FL = IL FG = IG FR = IR FS = IS FI = 0

Case 3: USA, product is small, result is positive. In this case, the exponents are equal and the mantissa of the addend is greater than the mantissa of the augend, or the exponent of the product is one less than the exponent of the augend. , The mantissa of the product overflows and is actually larger than the augend.

The polarity of the round bit from the product is correct and does not need to be inverted.

The FL, FG, FR, FS, and FI bits are calculated as in Case 1.

Case 4: USA, product is small, result is negative. In this case, the addend rounding bit must be inverted, like the MulRoubd bit.

MulRound = 0 The two's complement bits required when inverting the sum are:
Must be incorporated into the LSB of the inverted rounding bit.

No significant bits are required; if a round bit does not have its corresponding set of significant bits, it is zero and, after inversion, should correctly represent the rounding situation.

[0081]

[Table 5] The FL bit is set to IL.

MulRound = 1 Since the MulRound bit is set, the two's complement bits required to invert the result are offset by the MulRound bit based on the identity: The rounding bits are as follows:

[0083]

(Equation 2)

Case 5: USA, product is large, result is positive. In this case, the number of additions is actually larger than the product and the sum does not need to be inverted.

The FL, FG, FR, FS, and FI bits are calculated as in Case 1. MulRound bit is AddC
Used in the third stage to nullify the arryIn signal. Mu
The lRound bit is cleared before being sent to the fourth stage.

Case 6: USA, product is large, the result is negative, as in case 4; the addend round bit must be inverted. The MulRound bit was used in the third stage to zero out the AddCarryIn signal. The MulRound bit is cleared before being sent to the fourth stage.

The rounding bits are calculated as in Case 4.

Advantages over both the total number of cycles and the total number of instructions for the preferred embodiment without FMAC capability are the following simple DPS "Finit Impulse Response" (FIR) filters: This is specifically shown in the examples. In this example, 8
One coefficient and eight data items are multiplied and summed: Acc = D0 * C0 + D1 * C1 + D2 * C2 + D3 * C3 + D4 * C4 + D5 * C5 + D6 * C6 + D7 * C
7

Eight coefficients, eight data items, and Ac
Assuming that c is in a register and that eight interim registers are available, a conventional processor would perform the following operations: (FMUL and FADD operations have three cycle latency and Assume that it has one cycle throughput.)

[0090]

[Table 6]

Assuming a latency of one cycle and three cycles for each operation, the first thirteen operations should execute thirteen cycles in order without any dependency. Operation 14
Stops for one cycle to wait for the result of operation 12 to be completed, and requires two cycles. The operation 15 does not stop because the operation 13 can complete writing to T0 while the operation 14 is stopped, while the final accumulation operation 16 waits for the Acc value to be loaded from the operation 15. Stop for two cycles. 16 + 1 total cycles
+ 2 + 2, that is, 21 cycles for 16 operations.

FMAC in the FPU 26 of the Preferred Embodiment
Using operations, the following operations produce the same result:
(FMAC, FMUL, and FADD operations have 4 cycle latency and 1 cycle throughput.)

[0093]

[Table 7]

In this example, the first eight operations are executed sequentially in eight cycles without stopping. Operation 9 takes 1 to wait for operation 6 to complete writing to T1.
Stop during the cycle. Operation 10 also stops for one cycle, while final operation 11 stops for three cycles to wait for operation 10 to complete writing to T3.
The total number of cycles is 11 + 1 + 1 + 3 + 3, that is, 19 cycles for 11 operations.

The first advantage of the FMAC operation over the DSP function can be seen when the FIR operation is expanded to the depth of the pipeline. For example, if the same eight data points and eight coefficients are grouped into four sets and a partial FIR operation is performed on the four data points, the following calculations can be performed without stopping:

[0096]

(Equation 3)

The following F in the FPU 26 of the preferred embodiment:
The MAC operation should execute these expressions without having to stop:

[0098]

[Table 8]

This sequence is repeated without stopping again for the previously given eight data and eight coefficient operations. The throughput in the above example is a multiplication-accumulation operation by one every cycle, and as a result, the number of effective cycles is eight in the example of eight data and eight coefficients. Conventional processors using the same loop unrolling technique require 16 operations for 8 data and 8 coefficient problems, but each operation simply requires one multiplication and one addition, and each cycle takes one cycle. Because it is necessary. 8 conventional processors
Although requiring instructions, the FPU 26 of the preferred embodiment requires only four.

Having described certain embodiments of the invention,
It will be apparent that the invention is not so limited and that many modifications and additions can be made within the scope of the invention. For example, while the preferred embodiment has been described with reference to a CPU having a physically separate coprocessor, this is not a requirement. For example, a floating point unit could be included in the main processor. Furthermore, the features of the following related claims could be variously combined with the features of the independent claims without departing from the scope of the invention.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating components of a data processing apparatus according to a preferred embodiment of the present invention.

FIG. 2 shows an FPU according to a preferred embodiment of the present invention.
FIG. 2 is a block diagram illustrating components of a coprocessor.

FIG. 3 is a block diagram illustrating the data path component blocks of FIG. 2 in further detail.

FIG. 4 is a block diagram illustrating the components of the data path logic used to process the mantissa in accordance with a preferred embodiment of the present invention, showing the mantissa processing in stage E1 of the pipeline.

FIG. 5 is a block diagram illustrating the components of the data path logic used to process the mantissa in accordance with a preferred embodiment of the present invention, illustrating the mantissa processing in stage E2 of the pipeline.

FIG. 6 is a block diagram illustrating the components of the data path logic used to process the mantissa in accordance with a preferred embodiment of the present invention, showing the mantissa processing in stage E3 of the pipeline.

FIG. 7 is a block diagram illustrating components of data path logic used to process mantissas according to a preferred embodiment of the present invention, showing mantissa processing in stage E4 of the pipeline.

FIG. 8 is a block diagram illustrating components of data path logic used to process exponents in accordance with a preferred embodiment of the present invention, illustrating exponent processing within stage E1 of the pipeline.

FIG. 9 is a block diagram illustrating the components of the data path logic used to process the exponent in accordance with a preferred embodiment of the present invention, the stages E1 through E in the pipeline;
4 shows the flow of exponential processing.

FIG. 10 illustrates decision logic used in a preferred embodiment of the present invention to determine a rounding value to be applied to the result of a floating point operation.

[Explanation of symbols]

 22 Data Processing System 24 Main Processor 26 Floating Point Unit (FPU) Coprocessor 28 Cache Memory 30 Main Memory 32 Input / Output System 34 Main Bus 36 Coprocessor Bus 100 Data Path Logic 110 Control Circuit 120 Multiplier 130 Adder 140 Rounding Logic 150 Decision logic 160 Data path component block 170 Register file 180 Coprocessor interface 200 Multiplier 210, 220, 230, 240 Register 250 Product adder 260 Adhesive adder 270 Adhesive bit generator 320 Addend multiplexer 330 Addend multiplexer 350, 360 Register 370 Inverter 380 Multiplexer 390 Alignment shifter 450 Sum adder 457 Alignment shifter 460 Inverter 465 Multiplex Kusa 500 Updater 510 Rounding Select Multiplexer 520 Normalizer 600 Product Exponent Adder 610 Exponent Selector Multiplexer 620 Inverter 630 Adder 670,680,690 Register 700 Exponent Adjustment Adder 710 Multiplexer 720 Exponent Updater 730 Final Exponent Selector 800 First converter 810 Second converter 830 Third converter

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor David Tarence Masenii United States Texas, Austin, Buckthorn Drive 10706

Claims (16)

[Claims] 1. A data processing device for performing a multiply / accumulate operation A + (B * C) in response to a single instruction identifying said multiply / accumulate operation, comprising: multiplying values B and C; A multiplier configured to generate a non-rounded multiplied result and further generate first data required to determine the rounding; and add the unrounded multiplied result to the value A. An adder configured to generate an unrounded multiply-accumulate result and further to generate second data required to determine the rounding; and Determine one or more rounding values required to produce a final multiply-accumulate result equivalent to separately executing the embedded multiply instruction followed by a separate add instruction with rounding incorporated. Decision logic for; And a rounding logic for providing one or more rounded values to generate a final multiply / accumulate operation result. 2. The data processing apparatus according to claim 1, wherein the decision logic generates a final multiply-accumulate result.
The data processing apparatus, wherein the data processing apparatus is configured to apply a non-rounded multiply-accumulate result to rounding logic to generate a single rounded value. 3. The data processing apparatus of claim 1, wherein the first data generated by the multiplier includes a guard and a sticky bit, and the decision logic determines a multiplier round value from the first data. The data processing device, comprising: 4. The data processing device according to claim 3, wherein the first data further includes one or more least significant bits of a multiplication result. 5. The data processing apparatus according to claim 3, wherein the decision logic further comprises a second logic for determining one or more round values from the multiplier round value and the second data. The data processing device described above. 6. The data processing apparatus according to claim 1, wherein the adder includes an alignment shifter for aligning a smaller one of the multiplication result and the value A before performing the addition. A detection unit for detecting whether the shifted out bits are all ones or all zeros.
The data processing device. 7. The data processing apparatus according to claim 6, wherein the second data generated by the adder includes a guard and a round bit, an output of the detection unit, and a least significant bit of an unrounded multiplication and accumulation result. The data processing device includes a group. 8. The data processing apparatus according to claim 1, wherein the multiplier includes a multiplication unit for generating the partial result in a carry-save format, and a product adder for generating the multiplication result. The data processing device. 9. The data processing apparatus according to claim 8, wherein the multiplier further adds together a group of least significant bits of a group of partial products generated by the multiplying unit, A guard and sticky bit generator for generating guard and sticky bits from the output of the data processing apparatus. 10. The data processing device of claim 1, wherein the unrounded multiply-accumulate result includes a mantissa and an exponent, the data processing device further includes an updater for incrementing the mantissa, and the rounding logic is A data multiplexer comprising: a multiplexer for outputting either a mantissa or an incremented mantissa as a final mantissa of a final multiplication accumulation result depending on one of one or a plurality of rounded values generated by the decision logic. apparatus. 11. The data processing apparatus according to claim 10, wherein said one rounded value is input to a multiplexer to indicate whether a mantissa or an incremented mantissa is to be output as a final mantissa. The data processing device including a final update signal. 12. The data processing apparatus according to claim 11, wherein the rounding logic further includes exponent update logic for incrementing the exponent when the result of incrementing the mantissa overflows, and the incremented mantissa is used as the final mantissa. The data processing device, wherein the data processing device is selected as a mantissa. 13. The data processing apparatus according to claim 1, wherein the decision logic includes a first converter, the first converter receiving the second data generated by the adder, and the second data being rounded by the adder. Said data processing apparatus for compensating for a right shift normalization applied to unmultiplied accumulation results. 14. The data processing apparatus of claim 13, wherein the decision logic is configured to determine a multiplier round value from the first data, and wherein the decision logic further determines the multiplier round value. The data processing apparatus further comprising a second converter applied to an output of the converter circuit. 15. The data processing apparatus according to claim 14, wherein the decision logic further comprises a third converter which applies a predetermined rounding formula to the signal output from the second converter. The data processing device for generating one or more rounded values. 16. A method for performing a multiply / accumulate operation A + (B * C) in response to a single instruction identifying said multiply / accumulate operation, comprising: multiplying values B and C and rounding. Generating an unrounded multiplication result and generating first data required for a rounding decision;
To generate an unrounded multiply-accumulate result and generate second data required for the rounding decision; using the first and second data to execute a multiplication instruction incorporating rounding; Determining one or more rounding values required to produce a final multiply-accumulate result equivalent to individually executing individual add instructions with embedded rounding; and one or more rounding values Generating a final multiplication / accumulation result.