JP2000010814A - Chip with debugging capability - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor the execution of a program in real time over a wide range by making a chip include a debug bus which can be connected to another identical chip so that while a MONITOR mode and a DUT mode are set to complementary modes, signals enabling a chip and another chip to be operated in parallel are transferred. SOLUTION: When a power source is turned on, not only a debug chip 110C in a DUT mode, but also MONITOR-mode chips 110A to 110B are reset with an energized RESET signal. In this case, when the RESET signal is energized, the MONITOR-mode chips 110A to 110B reports the debug bus 140 that an enable signal is generated and the DUT-mode debug chip 110C that the debug bus of its CODEC is enabled. The 2nd synchronization unit of the debug chip 110C in the DUT mode, on the other hand, synchronizes the reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to computer chips and computer devices, and more particularly to computer chips and devices that are perfectly suited for program debugging, and also to debugging systems.

[0002]

BACKGROUND OF THE INVENTION An important step in developing a new computer program is to debug the program to correct program errors. This program debugging runs a program on a computer,
This is done by monitoring different signals that are communicated internally between different circuits of the computer, as well as communicated externally between the computer and the peripherals. Such a circuit includes, for example, a central processing unit (CPU)
A direct memory access (DMA) unit;
There are a main memory and an input / output (I / O) interface circuit. In order to enable debugging of a program while operating a computer, a logic analyzer has been connected by a probe to a circuit board on which a computer circuit is mounted.

In order to speed up memory access, computers generally have a cache memory. This memory is mainly used by the CPU as a high-speed temporary memory, that is, a short access time. This temporary memory only holds the addresses and data of the most frequently used and most recently used main memory. The main part of all accesses of the CPU main memory is processed only by the cache memory, and only the minor part of the access uses the main memory by exchanging data between the main memory and the cache memory. Therefore, in the execution of the program, the CP
Since the exchange of signals between the U and the cache memory mainly takes place, it is preferable to debug the exchange of signals.

However, modern computer architectures tend to integrate as much of the computer circuitry as possible on a single chip. Especially in general, CPU
And the cache memory are integrated on the same chip, while the main memory is usually mounted on the same circuit board and external to the chip. This main memory is typically manufactured from a number of interconnected chips. By integrating into one chip, CP
While debugging only between U and main memory,
It is impossible to monitor the exchange of signals between the CPU and the cache memory.

Some attempts have been made to solve this problem. One conventional solution is to turn off the cache memory during a debugging operation. In this way, all memory accesses are made to the main memory and monitoring becomes possible. However, this means that the possibility of monitoring the program in a true situation is lost and all execution rates are reduced. In such a situation, there are several types of error-like movements that are unknown. Handling caches is an important part of program operation.

Another prior solution is to produce a special version of a normal chip, the so-called bondout chip, which has an extra chip connected to the chip's internal bus. This solution is expensive because special chips have to be manufactured in parallel with normal chips. Furthermore, this method reduces the clock frequency, especially due to the extension of the leader lines. Therefore, real-time debugging cannot be performed, and a predetermined bug that causes an error when executed in real time cannot be detected.

[0007] Yet another prior art solution is to provide certain registers to enable debug support. These registers, often referred to as breakpoint registers, allow the use of software breakpoints at certain points in program execution. At these breakpoints, the current address and data information is loaded into the breakpoint register to be read by the monitor system. This solution makes it possible to detect whether the execution of the program has safely reached these breakpoints. However, the main disadvantage is that debugging cannot be performed in real time. In addition, what happens between breakpoints cannot be monitored.

[0008]

Therefore, there is a need for a new computer device that allows the computer to operate at full clock rate while also monitoring the signal exchange between the CPU and cache memory integrated on the same chip. It is rare.

It is an object of the present invention to operate a CPU at a full clock rate, ie, debugging in real time, without providing a special version of the chip for debugging, and to program the program more widely than previously possible. The object is to make it possible to monitor the execution.

[0010]

SUMMARY OF THE INVENTION According to the present invention, there is provided an integrated system in which an interconnected CPU and cache system are integrated and at least two different modes of operation, for example, a device test (DUT) mode. This is achieved by a computer chip that can be set to one of a first mode and a second mode that is a MONITOR mode, and at least one synchronization unit. The MONITOR mode and the DUT mode are complementary. The chip includes a debug bus connectable to another identical chip for exchanging signals allowing the chip to operate in parallel with another chip while setting the chip in a complementary mode. These signals include the synchronization signals generated by the synchronization unit.

A computer chip so configured for debug operation can eliminate the excessive costs of manufacturing a special version of the chip for debugging. The combination of the debug bus and the synchronization circuit is MON
This takes into account the fact that a small set of essential signals can be efficiently exchanged for another identical chip set to ITOR mode, ie debug mode. Since these different modes are prepared, it is possible to perform full-rate debugging to obtain full information on program execution.

[0012]

FIG. 1 is a hardware block diagram of a test configuration of a chip having an enhanced debugging capability. This chip in one embodiment of the present invention has all of the basic functions of a "computer on chip" including a central processor, cache, DMA unit, local bus and memory manager. In addition, this chip is in master mode (During device testing (D
UT) mode or some slaves (eg MON
(ITOR) mode. Operation and execution of program code inside a chip that is in DUT mode is manifested using one or more identical chips enabled for MONITOR mode. MONITO
Since the internal state of the DUT mode chip is displayed in the R mode, the DUT mode chip and / or the DU
The task of debugging program code running on a T-mode chip is simplified.

Some identical chips are coupled on a common set of buses. One chip is configured to be in the master mode while the same chip operates in the MONITOR mode. Debugging is performed by causing the chip to enter a master mode, for example, a device under test (DUT) mode, to control the address portion of the system bus. The chip in DUT mode controls the addresses present on the address bus as the address bus master, and thus the memory and device access requests for the system, including all master mode and slave mode chips. All chips in both the slave mode and the master mode are connected to the data portion of the system bus, so that all chips receive and process the same data and program codes through the data portion of the system bus.
Further, all chips include synchronization circuits to ensure synchronous processing of program code and data.

Since the chip in the master mode has a function of outputting address information to the address bus, the address line of the chip in the slave / monitor mode is not required to output the address information to the address bus. Instead, each address line output of the chip in the MONITOR mode is switchably connected to the address lines / pins of the chip in the MONITOR mode to various components or signal lines inside the chip that are not provided with external pin connections. This is used to carry information from inside the chip to the "outside." These components or signal lines include cache, local bus data and address lines, interrupt units and DMA units. Typically, such information is not available, making it difficult to debug the chip and / or the program code running on the chip.

FIG. 1 shows a computer system 98, a monitor 100, a logic analyzer 102, and a computer 1.
4 shows a test configuration comprising a network 04 and a network 106. Computer system 98
DUT mode chip 1 acting as the core of the computing system
10C. The computing system 98 includes a transmitter 120,
It also includes a power-on reset 118, associated system hardware 112, memory 114, and input / output (I / O) unit 116. In this example, the chip 110C configured in the DUT mode and having enhanced debugging capability includes a local bus 130C, a codec (Codec) unit 132C, and a memory control unit 134C. This memory control unit includes a first local bus debug switch 136C. Monitor 100 is MONITOR
Mode, and includes two chips 110A-B with enhanced debugging capabilities. All chips 110A-C
Have similar parts indicated by numbers with subscripts A to C, respectively.

In the illustrated embodiment, a common bus connects the computing system 98 and the monitor 100. These buses include a codec bus / debug bus / encoded event bus 140 and reset and oscillator buses 142A-B.
An asynchronous event bus 164 and a mode selection bus 144
And data / instruction part 1 of system buses 146 to 148
48. The debug chip 110C in the DUT mode receives the data portion 148 of the system bus 146-148 via the data line 152C and the address line 160C.
And the address portion 146, respectively.
The data portion of the system bus is connected via the data lines 152A-B to the chip 11 in the MONITOR mode, respectively.
OA and B are also combined. System bus 146-14
8 is also coupled to system hardware 112, memory 114 and I / O unit 116. The debug chip 110C in the DUT mode and the chips 110A-B in the MONITOR mode are connected via buses 142A-B,
It is also coupled to power-on reset 118 and oscillator 120. Further, the MONITOR mode and DUT mode chips 110A-C are also coupled to mode select bus 144 for setting the operating mode of each chip via mode select mode input pins 150A-C, respectively. DUT mode and MONITO
The R-mode chip is also coupled to asynchronous event bus 164. Finally, debug bus 140 is coupled to all chips 110A-C to synchronize activities including power-on resets, interrupts, wait states, DMA accesses and other asynchronous events.

In contrast to address line 160C of debug chip 110C in DUT mode, debug chip 1
The corresponding address lines 160 of each of 10A-C
AB are instead coupled to logic analyzer 102. It is these signals that are sent to the logic analyzer 102 for display and analysis on the computer 104 that correspond to the local bus activity and / or interrupts of the chip in the debug chip 110C in DUT mode, ie, DMA activity. Line 160A
~ B.

Debug chip 110A with enhanced capabilities
-C each execute the same process 170 that resulted from the program code 180 stored in the memory 114 during operation. In one embodiment of the present invention, all chips 11
0A to 0C boot to the same address in the main memory. However, only the debug chip 110C in the DUT mode is used for the system buses 146-14.
8 has no address bound to the address portion 146. Therefore, it is this chip 110C that acts as the master of the address portion of the system bus. The bus master chip 110C determines which access requests are processed on the address bus, and thus determines what data and / or program code is present in the data portion 148 of the system bus. A typical program sequence provided to each of the chips 110A-C through the data portion of the system bus includes a read or write command to a particular address, which is followed by reading from that particular address by each of the chips,
Or the data to be written follows. Therefore, MON
Each of the ITOR mode chips 110A-B receives the same data and instructions and shadows the activity of the master chip 110C, which is stored in main memory and performs the same operation 170C, for example, in response to program code 180. I do. None of the monitor chips are external memory 1
14 is not written. Writing to the external memory is always performed only by the debug chip 110C in the DUT mode.

To debug the chip itself and / or the program code running on the chip, it is advantageous to access the various components and signal lines inside the chip without pins and monitor these states. is there. Generally, most of the computational activity of this computer chip and other chips, such as logic units, digital signal processors, graphics processors, etc.
Not available with external pins. The illustrated embodiment, for example, a "computer" chip 110A with enhanced debugging capabilities
At ~ C, such activities take place upstream of the memory control units 136A-C known as local buses 130A-C. In the illustrated embodiment, the local bus is a synchronous component, eg, a cache memory and an asynchronous component, eg, a DM.
A and the interrupt unit. Most of the processing in each of the chips can occur on a local bus between its CPU and cache memory. That is, the DMA unit and its activity are not displayed on the system bus.

In general, execution of the program code is associated with instructions received by each of chips 110A-C from data portion 148 of the system bus. The program code causes the central processing unit CPU of each chip to perform logical and algebraic operations, and the program code further comprises
Performing these operations may require reading and writing data to and from memory 114 through the data portion of the system bus. Since each of these chips operates with the same program code and the same sequence, only one chip needs to master the bus, and in the illustrated embodiment chip 110C configured in DUT mode.
Is this chip. System bus 146-14
Eight address portions 146 store read and write requests for that chip, thus determining the contents of the data portion 148 of the bus.

Each chip 110A-C is configured in either a DUT mode or some MONITOR mode by signals on mode input pins 150A-C, respectively. The device is DUT based on the digital sequence corresponding to the binary sequence "000" on the device port.
Mode. Also, the binary sequence "0
The signals corresponding to "01-111" allow the device to be in any of several MONITOR modes. Numerous internal state changes are made in response to each individual mode signal. One of these changes is to connect the debug switches 136A-C of each of the chips. The chip 110C is in the DUT mode. In this case, the debug switch 136C is connected to the local bus 13 via the memory interface unit 110C (see FIG. 3) in the memory control unit 134C.
The address output 160C is coupled to the address portion of 0C. This mode relates to the cache policy and the state of the chip's on-chip cache memory 244C (see FIG. 2) and, where appropriate, to address
Only addresses occurring in the address portion of the local bus are generated on C. Conversely, one or more debug chips configured in monitor mode, for example debug chips 110A-B, are connected to the address portion of the local bus and the data portion of the local bus without filtering by memory control. Associated debug switches 136A-B. The activity of these lines is provided to logic analyzer 102 by the address output lines 160A-B of these chips. These MONI
In each of the TOR mode chips 110A-B, the local bus address line continues to indicate read and write commands by the associated address. MONT
OR mode chip and DUT mode chip 11
The difference from 0C is that in the MONITOR mode chip, the address present on the local address does not reach the address portion 146 of the system bus, and therefore, except for interference, the data available on the data portion 148 of the system bus is lost. It is not controlled. Rather, the data on the data bus is actually a chip 11 configured in master mode or DUT mode.
The data on the data bus is actually determined by the address obtained by 0C. Thus, by mastering the address portion of the system bus and enabling the chip to be configured (and thus determine the contents of the data portion 148 of the system bus), the activity of the MONITOR mode chip is reduced to that of the DUT mode chip. Activities can be shadowed. The following figures and specification describe another function dependent on the mode of the chip. Thus, externalization of interrupt and DMA access states and synchronization of processing of some chips is disclosed.

As will be apparent to those skilled in the art, mode selection can be performed without using dedicated mode selection pins on the chip. In another embodiment of the invention, the configuration of the debug components of the chip can be performed by a data sequence received by the chip at start up or by multiplexing pins present on the chip.

FIG. 2 is a detailed block diagram of a representative chip of the debug chips 110A-C described above with reference to the embodiment of FIG. 1, for example, the chip 110C.
This chip has a clock 232C, a CPU 238C,
A cache system 240C including a cache controller 242C and a cache memory 244C;
A controller 248C, DMA arbitrator 250
C and a DMA unit 246C including an associated DMA I / O buffer 252C. Further, this chip is shown in FIG.
And the following debug components that allow the chip to operate in either the DUT mode or some MONITOR modes, as described above with reference to FIG. These debug components include the interrupt unit 236
C, a first synchronization circuit / unit 234C, a second synchronization circuit / unit 230C, and a codec 132C
And a debug switch 136C. This debug switch sends synchronous and asynchronous processing states externally through the address pins of the chip. It has a control connection coupling each of the debug components to the mode input pin 150C. The configuration of each component changes in response to a mode signal on mode input pin 150C. The mode signal places each part in either the DUT mode or some MONITOR modes.

The chip itself is connected to network interface 200 via bus 280C, to reset unit 118 via reset line 142A, to oscillator 120 via oscillator signal line 142B, and to codec 13 via debug bus 140.
2C and associated sister chip, ie 110A
-B via the address portion 146 and the data portion 148 of the system bus.
O unit 116, and a mode input pin 150C
, And to the mode selection bus 144,
It is shown connected via I / O interface 254C to peripheral DMA devices and ultimately via asynchronous event bus 164 to sister chips 110A-B. In one embodiment of the present invention, the network interface is a network interface bus 28.
8C, and the interface bus is, for example, an IEEE standard 802.3 M.
II bus.

In the chip, a CPU 238C and a cache system 240C are coupled to a local bus 130C. The cache controller 242C can execute any one of a number of cache policies, including write-through and copy bags. In one embodiment of the present invention, the chip provides another feature of on-board DMA unit 246C with an associated I / O buffer 252C, where I / O buffer 252C is compatible with a number of peripheral devices (not shown). External DMA to access between
It is coupled to an I / O interface 254C. Further details of this new DMA unit 246C are described in US patent application Ser.
In a pending U.S. patent application entitled "Method and Computer System for Improved Memory Access by DMA Units" by Bencson, Kenny Runnerup and Par Sander on October 9, 1998. I have. This US patent application is incorporated herein by reference.

The clock 232C is coupled not only to the CPU 238C, but also to the first synchronization unit 234C and the second synchronization unit 230C. First synchronization unit 2
34C accepts an external interrupt signal on signal line 166C and receives signal line 2 from DMA unit 246C.
Via 78C, an input signal can be accepted to reserve a time slot for DMA information on debug bus 140. This first synchronization unit provides an output signal to memory control unit 134C via signal line 274C. Further, the first synchronization unit sends an output signal to CPU 238C over signal line 282C and sends an output signal to codec 132C over signal line 926C. The second synchronization unit 230C is configured to
An asynchronous input signal is received from the O unit 116 via a signal line 164. The output of this second synchronization unit is coupled to the codec and the CPU and to the codec 132C via a DMA signal line 276C.
Unit 246C is connected.

The mode signal on mode input pin 150C determines whether the device will operate in master / DUT mode or MONITOR mode when activated. In the case of the MONITOR mode, the input signal to the mode input pin 150C is the debug switch 136C, the first synchronization unit 234C, and the second synchronization unit 230.
C and the state of the codec 132C are determined.

When the mode signal on mode input pin 150C is set to master / DUT mode, first synchronization unit 234C and second synchronization unit 230C accept asynchronous input signals, eg, interrupt signals and DMA access, and monitor. During a sufficient number of clock cycles to allow synchronization of units 110A-B,
Support the processing of the input signal. This synchronization is shown in FIG.
Can be performed as shown in In the DUT / master mode, debug switch 136C is coupled to the local address bus such that debug switch 136C is isolated from the system address bus portion of the local bus address activity which conventionally only involves writing and reading cache memory 244C. You.

As described above, chips 110A-B are identical to chip 110C shown in FIG. The only difference is the debugging part of these differences, for example codec 13
2A-B first synchronization unit 234A and second synchronization unit 230C, and debug switch 136A-
B is configured not only to synchronize their activity with the activity of debug switch 110C, but also to represent a predetermined internal state of the corresponding chip which normally does not appear externally. The first of these functions, for example the function of synchronizing with the sister chip, is obtained by the first and second synchronization units and the codec.

In the illustrated embodiment, mainly
In the OR mode, there are a number of different states inside the chips 110A-B, which are
Address output 160A-B for performing the process according to F.02
(See FIG. 1). These states include coupling a predetermined one of local data buses 300A-B or local address buses 302A-B to a corresponding debug switch 136A-B. These outputs are output to the corresponding address outputs of the chip, e.g.
Available for A / B (see FIG. 1). Therefore, Master /
While the chip 110C configured in the device test mode operates in the DUT mode as a full featured computing unit, its sister chip configured in the MONITOR mode executes the same program code and the DUT mode configured as the bus master. Debug chip 110
By responding to C in the same manner to asynchronous events, DU
Exposes internal states associated with processing performed on the chip in T mode.

In the present invention, the first chip is configured as a device under test, and this address output controls which memory location to read and write to, and therefore, It is a bus master in terms of which data and instructions are given at the time. A sister chip configured to operate in the MONITOR mode shadows the end data access activity of the chip in the master mode and performs the same processing synchronously therewith. Thus, a test including a minimum additional onboard real estate dedicated to debug functions and a pinout similar to that of a conventional chip without debug functions, except for the mode input pins 150A-C and the pins associated with the debug bus 140. And a single chip suitable for manufacturing can be manufactured.

FIG. 3 shows a detailed embodiment of the memory control units 134A-C shown in FIG. Each of the memory control units is a memory interface unit 110A
To C and the debug switches 136A to 136C. Each of the memory interface units 310A-C is connected to a cache controller 242 through a control bus (not shown).
A to C, CPU 238A to C and DMA unit 24
6A-C (see FIG. 2).
reference). On the local bus side, the control unit is coupled to the address bus portions 300A-C and data bus portions 302A-C of the local bus. On the system bus side, the control unit is coupled to data lines 152A-C and intermediate system address buses 104A-C. Each of the debug switches 136A-C has a mode input pin 1
50A-C. In the illustrated embodiment, the debug switch has an address output 160
AC are coupled directly to the local bus, or indirectly to the local bus via intermediate system address buses 304A-C from memory interface units 310A-C. When directly coupled to the memory control unit, the chip is
-C and the address portions of the cache memories 244A-C act as a DUT computer coupled between the address output lines 160A-C and the address portion of the local bus, as determined by the cache policy enforced by the contents at any time. Alternatively, debug switch 136C may be configured to monitor all activity on local data buses 300A-C, local address buses 302A-C or signal lines. In another embodiment of the present invention, through internal event lines 306A-C,
For example, the status of the CPU or the cache controller can be monitored (see FIG. 3). These outputs are obtained directly through the corresponding address output lines 160A-C.

As will be apparent to those skilled in the art, the apparatus disclosed herein exposes the internal state of a complex integrated circuit computing chip by incorporating mode selectable debug switching and synchronization functions on the chip. . This enhanced chip does not need to have a local bus. Instead, the debug switch need only connect the input of the switch to internal signal lines and / or components on the chip that require monitoring. The output of the debug switch is connected to the address line of the chip. In one embodiment of the present invention, the synchronization circuit can include something as simple as a common clock. This can be practical if, for example, the chip does not handle asynchronous events. In another embodiment of the invention where the chip handles asynchronous events, the synchronization circuit shown and described in FIG. 9 is appropriate. The synchronizer is connected to a debug bus with a multiplexing function to reduce the number of asynchronous signal inputs and pins on the chip. Finally, both the debug switch and the synchronization circuit are themselves DUs.
It may respond to a mode signal at a mode pin on the chip to be in the T state or one of several MONITOR states. The switches can be used to debug many types of chips and the program code intended for use on this chip. These chips are digital signal processors, graphics processors, video processors, signal processors, pattern processors, programmable logic devices, field programmable devices, microcontrollers ...
Etc., but is not limited thereto. M
By coupling several chips in the ONITOR mode to chips in the DUT mode, the MONITOR mode chip outputs the internal processing state of the DUT mode chip on its address line while indicating the processing that occurs on the DUT mode chip. be able to. MONT
By setting each of the chips in the OR mode to a different monitor mode, two or more internal states of the DUT mode chip can be obtained simultaneously. The internal state can be evaluated in detail by connecting the address line of the MONITOR mode chip to the logic analyzer.

Referring now to FIG. 4, debug bus 14
0 includes only 5 paths. BCLK, one of these five paths, is an input / output (I / O)
The system bus 146 through the bus connected to the unit
148, a second synchronization circuit 230 for transmitting an external asynchronous signal from an I / O unit such as a DMA request signal or synchronization information on a wait signal.
Used by C. The external asynchronous signal is supplied to the second synchronization circuit 230C and the monitor 1 by the I / O unit 116.
Sent to 00. The external interrupt request generated by the I / O unit 116 is
Sent to 4C.

The other four paths BS0 to BS3 are connected to the CUT from the debug chip 110C in the DUT mode to the monitor 100.
Used for transmitting PU and DMA status information.
Further, these debug bus paths BS0 to BS3 are used for the above-mentioned synchronization between the monitor 100 and the DUT mode debug chip 110C during the system reset operation when the corresponding code is generated from the first synchronization circuit 234C.

Therefore, digitally, a total of 16 different 4
Bit words or codes are available. The lower one corresponding to the ten DMA channels used in this embodiment
0 codes, that is, logically 0-9 codes are DM
Used for transmitting A status. This information is
It tells you whether to accept the A channel, when to read, and how many bytes are left to receive if needed. The data is received in the form of a block, in this example, a 4-byte block.
0 is required depending on the time for transmitting the DMA status information. Therefore, if the data remaining to be received from the I / O unit is 8 bytes or less and is the end of an I / O unit signal of data, that information must be transmitted to the monitor 100. This status information is not only transmitted from the arbitrator 250C through the debug bus 140 to the DMA controller 248B, but also through the DMA signal line 276C.
It is also sent to the controller 248C.

The codes 10 to 15 are used for the CPU interrupt status generated by the first synchronization circuit 234C as follows. 10 IRQ with external vector number, no NMI 11 IRQ and NMI with external vector number 12 No IRO, no NMI 13 NMI, no IRQ 14 IRO with internal vector number, no NMI 15 with internal vector number IRQ and NMI

[0038] IRQ means an interrupt request, and NMI means non-maskable interrupt. When the DMA unit 246C is trying to use the debug bus 140, the DMA unit 246C uses the first synchronization circuit 234C so that the monitor 100 does not unbalance the handling of the interrupt in the debug chip 110C in the DUT mode. The signal is transmitted to. By this signal, the first synchronization circuit 234C
Holds the interrupt status. Only after the debug bus 140 is released by the DMA unit 246C is the CPU 238C, 238A-B of the debug chip 110C and the monitor 100 in the DUT mode.
The new interrupt status information is sent to.

The on-board DMA unit 246C is a DU
Synchronized in T's buffer 252C and prioritized in arbitrator 250C. The result of this synchronization and arbitration is DMA controller 248
C, and further to the DMA control units 248A-B via the codec 132C, the debug bus 140 and the codecs 132A-B. Accordingly, the control portion of the operation of the on-board DMA is mirrored in the MONITOR mode chips 110A-B. On-board DM
The data portion of A is processed by issuing all DMA data through the external memory data bus. This data is then available for MONITOR mode chips.

Regardless of the cache system 240C integrated on the chip, while the debug chip 110C in DUT mode is operating, to provide a logic analyzer with complete data, address and asynchronous event information, Since the present debugging systems 98 to 100 are configured, it is possible to improve memory access by the memory control unit 134C as described later.

FIG. 5 is a detailed hardware block diagram of the interface between the memory control unit and the main memory of the enhanced debug chip shown in FIGS. In one embodiment of the present invention, the main memory generally includes several DRAMs, a dynamic random access memory. Each DRAM 550A-C has two parts of addresses (where the lower part is the column address 5).
54, the upper portion 552 being a row address) and having a memory area 556 arranged in a matrix. In the preferred embodiment, memory control units 134A-C perform further improved memory accesses, taking advantage of the fact that subsequent memory accesses are frequently related to subsequent addresses. Therefore, the memory control unit 134C has the main memory 11
4 separate row address registers 500A-C and a comparison unit 502A for each of the four DRAM circuits 550A-C.
To C are provided. The address buffers 504A to 504C of the memory control unit 134C for holding the full main memory address are divided into two parts, and each part can be separately boarded to the main memory. For a subsequent main memory access, the row address of the subsequent main memory address is the same as for the previous access, but only the column address portion 504B need be loaded. This saves time as compared to loading the entire address each time, ie loading the row address first and then the column address. To determine if the row address is the same as the previous address, the compare unit compares the row address portion 504A with the contents of the row address register of the currently active DRAM. If they match, only the column address portion 504B is input. If they do not match, both the row address and the column address are input, and the register is updated at the same time. These two buffer portions 504A-B
Are multiplexed on the system buses 146 to 148 by the debug switches 136A to 136C of the memory control units 134A to 134C.

FIG. 6 is a block diagram illustrating the interface between the enhanced debug chip and the low speed peripheral devices shown in FIGS. In particular, the external re-execution unit 700 can be used for the low-speed peripheral unit 710, mainly for older units. If the data transmission time is too long, the system bus 1
46 to 148 are occupied, which can cause a problem in that another unit is subject to time critical access. Hereinafter, a re-execution unit 7 referred to as a re-execution unit
00 assists the CPU 238C during read and write operations in such low speed peripheral units. For example, assume that data is read from the peripheral unit 710.

From the start of CPU access, the re-execution unit 700 buffers address information in the address buffer 116B, sets a timeout,
A re-execution routine for transmitting a re-execution request to the UP 238C is started. This causes CUP 238C to release the bus and continue with other tasks that allow other bus masters in debug chip 110C, eg, DMA unit 246C, to access. On the other hand, the re-execution unit 7
00 communicates with peripheral units. After that, the CPU 238
Either the timeout has elapsed or the timeout has not elapsed when C performs the read operation again. If the time-out has elapsed, the CPU 238C continues the read operation.
00 sends another re-execution request to the CPU 238C.
When data must be written to the peripheral unit 710, the corresponding address and data buffer 116B
Perform the corresponding steps including buffering the addresses and data in ~ A. System bus 146-1
While the 48 is released to another task, data writing is continued by the re-execution unit 700. DU
The signals sent from the CPU from the T-mode debug chip 110C to the re-execution unit 700 are a chip select signal, a read signal, and a write signal.

With the mirroring of program execution on the monitor 100, interrupt handling is a problem that must be handled to obtain proper synchronization and timing. This problem occurs especially when several interrupts have to be processed simultaneously.

Thus, referring now to FIG. 7, according to another embodiment of the present invention, a dynamic priority processing method is used. FIG. 7 shows a representative unit corresponding to each of the interrupt units 236A-C (see FIG. 2). For example, the chip 110C is active in the interrupt unit only for devices in the DUT mode. In the illustrated embodiment, this interrupt unit accepts an asynchronous input signal from I / O unit 116 via signal line 166C (see FIG. 2). These interrupt signals can be obtained before the interrupt masking or after the interrupt masking and processing to the external memory data bus via the signal line 274C by the DUT chip, so that the CPU 238C in the DUT mode is used.
Is available to the chip CPUs 238A-B in the monitor mode when reading the interrupt signal. Prioritized output 850C of interrupt unit 236C
Pass through a first synchronization unit 234C, the output of which is provided as an input signal to codec 132C (see FIG. 2). Each of the chips 110A-C includes the same interrupt unit 236A-C, but only the DUT mode chip 110C is active.

Several individual interrupt request signals are received via interrupt line 166C. These lines are the first mask registers 802 and A
A first array of ND gates connects to the individual interrupt masks shown schematically. Accordingly, each of the individual interrupt signals is sent to the input of a respective AND gate 802A-M of the first array, and the mask register 802 is connected to the other input of each of the AND gates 802A-M. Each OR gate 804
The inputs of A to N are connected to several interrupt signal lines 166C and the outputs of the corresponding AND gates. Thus, these interrupt signals are combined into one signal for signal line 166C. The output signals of the OR gates 804A-N are arranged similarly to the individual masks and associated AND gates 802A-M.
Second mask register 806 and AND gate 806A
.. N can be masked by the group mask indicated by the second array.

The output terminals of the second array of AND gates 806A-N are connected to n input terminals of OR gate 808, and the output terminal of OR gate 808 is connected to synchronization circuit 234C.
Through the CP of the debug chip 110C in the DUT mode
It is connected to a U238C and a codec 132C, where the status is coded and sent to the monitor 100.

To detect and isolate received interrupt signals and allow prioritization between these signals, allow readout at different desired levels. Preferably, at least the output signals of the second array of AND gates 804A-N are read out by priority logic and encoded into vector numbers. This vector number is different for different combinations of interrupt signals. The vector numbers are output on the system buses 146 to 148. Therefore, this vector number is used for the debug chip 11 in the DUT mode.
Available for both OC and monitor 100. Therefore, this vector number is generated by the debug chip 110C in the DUT mode, but is similarly used by both the debug chip 110C in the DUT mode and the monitor 100. These interrupt signals are transmitted through the first synchronization circuit 234C. This vector number is used by the CPU as the index number of the lookup table that holds the interrupt vector. Mostly one device interrupt signal, ie only one unit 260C, 264
There is only a device interrupt from C and it is clear which interrupt vector to fetch. If there is more than one simultaneous interrupt signal, the vector numbers correspond to a priority routine that determines the priority of the interrupt signals. Thus, different interrupt signals are processed in that order.

Therefore, in most cases where there is only one interrupt signal, a fast interrupt process is performed, and a time-consuming priority determination method is required only when there are a plurality of interrupt signals from two or more units. Based processing is performed. In order to determine exactly what interrupt signals are present from the unit to be processed, it is of course possible to detect signal lines on either the input or the output of the individual masks 802A-N. In addition, when an interrupt request reaches the CPU, this signal is not only generated internally, but also
O-devices can be generated externally, and interrupt signals that cannot be masked can also occur.

FIG. 8 is a hardware block diagram showing details of the first and second synchronization units of the MONITOR mode chip 110B and the DUT mode debug chip 110C shown in FIG. These units are D
Synchronization of internal and external asynchronous events between a debug chip in UT mode and a debug chip in MONITOR mode is generally addressed. As described above, each chip includes the same hardware configured in a manner that depends on the mode of the chip as measured by the input signals on mode input pins 150B-C.

A partial block diagram of two debug chips 110B-C is shown, showing first and second synchronization units of both chips. The synchronization unit of the first debug chip is the mode input pin 150B of the chip.
A MONITOR mode corresponding to the state of the chip 110B set by the above mode signal,
The synchronization unit of the second debug chip is in the DUT mode corresponding to the state of chip 110C set by the mode signal on mode input pin 150C of the chip.

Structurally, the synchronizers on both chips include the same components, but as noted above, the coupling between these components can vary depending on the mode settings for the chips.
For this reason, DUT mode and MONITO
Each of the synchronizers in both R modes will be described. The component with the suffix B is in the chip 110B in the MONITOR mode, and the component with the suffix C is in the chip 110C in the DUT mode.

Each of the second synchronization circuits 230B-C includes a latch 960B-C, a change detection unit 958B-C,
And synchronizers 950B-C. First synchronization unit 2
Each of the latches 902B-C and the synchronizer 90
0B-C and interrupt units 236B-C. The figure shows the associated codecs 132B-C, clocks 232B-C and corresponding connections.

Second Synchronization Unit The second synchronization unit employs one of two configurations responsive to a mode select signal on mode input pin 150. In a first configuration related to the DUT mode, the second synchronization unit 230C
Are the monitor mode chip and the DUT mode chip 110B ~
C detects an asynchronous signal on the asynchronous signal bus linking both of them. The second synchronization unit synchronizes the signal with the DUT clock 232 and latches this signal. Next, the second synchronization unit determines whether there is a no-change time after receiving the asynchronous signal, and outputs an enable signal to the sister chip 100B after the no-change time has occurred. Unlatch the signal to be released to the internal components of. 2nd corresponding to DUT mode
In the configuration, the second synchronization unit 23
OB detects an asynchronous signal on the asynchronous signal bus, synchronizes this signal with the MONITOR clock 232B, and latches this signal. Next, the second synchronization unit, upon receiving the enabling signal from the sister chip 110C, unlatches the chip release signal to the internal components of the chip for processing. As will be apparent to those skilled in the art, the fixed delay, DUT mode and MO
Variable delay time in NITOR mode, synchronization information as well as MON generated by DUT mode chip
There are a number of methods and apparatus for synchronizing latches that include a delay in response to receiving a latch enabling signal sent to an ITOR mode chip.

The configuration of the second synchronization units 230B to 230C is as follows. Both synchronization units have inputs from an asynchronous bus 164 via signal lines 164B-C (see FIG. 1) coupled to synchronizers 950B-C of each unit. On this bus, internal asynchronous events such as external DMA accesses and wait states are received. In both synchronization units, the outputs of the synchronizers 950B-C are connected via signal lines 974B-C to respective ones of the inputs of the change detection units 958B-C and the latch units 960B-C. In a debug chip in DUT mode, the output of change detection unit 958C is coupled to the enable input of latch 960C and to the BCLK line of debug bus 140. For the debug chip 110B in MONITOR mode, the change detection unit 958B is inactive and the latch 960B instead receives its enable input signal via the BCLK line.

In operation, the second synchronization units 230B-C
Of the DUT mode change detection unit 9
Coordinated by 58C. Both units 230B-C receive asynchronous DMA or wait state signals on asynchronous bus 164 over respective signal lines 164B-C. This signal is output to the clock 232B of each chip by the corresponding synchronizers 950B-C.
~ C. In an embodiment of the present invention, the synchronizer comprises one or more flip-flops. DU
When the change detection unit 958C of the T-mode debug chip 110C detects a change time during which inactivity continues, it outputs an enable signal to the enable inputs of the latches 960B-C of the second synchronization unit of both chips. . The signal for latch 960B arrives via the BCLK line on debug bus 140. Thus, synchronization is achieved by triggering latch units 960C-B with a common signal generated by change unit 958C. Each latch 96
Output signals 284B-C of 0B-C are output from CPUs 238B-C.
C and the memory control units 134B-C of the respective chips 110B-C. Synchronization of the chip during power-on and wait states is performed by the asynchronous bus 16.
DUT mode chip and MON via connection to 4
Bus power-on resets and wait states are introduced to these chips via asynchronous bus 164, processed by both second synchronization units of the ITOR mode chips. It should be noted that the synchronizers described so far do not synchronize the first chip clock 232B and the second chip clock 232C, and these clocks can in fact be offset from each other. Instead, even if you can stagger the same clock cycle,
The synchronizer delays the execution of external asynchronous signals and allows their processing on the same clock cycle on all chips.

First Synchronization Unit The first synchronization unit employs one of two configurations responsive to a mode select signal on mode input pin 150. In a first configuration related to the DUT mode, the first synchronization unit 234C
Detects one or more asynchronous signals and converts these signals to the DUT
Synchronize with the clock 234C, determine their priority in the interrupt register, latch them, and send the synchronization information regarding the asynchronous signal to the codec of the sister chip 110B via the codec 132C, and after an appropriate delay time, Release the latched signal to the internal components of the chip for processing. In a second configuration corresponding to the MONITOR mode, the first synchronization unit receives synchronization information from the codec 132B, latches the information, and after an appropriate delay time, outputs the signal latched simultaneously with the first latch. Release to internal parts of chip for processing. As will be apparent to those skilled in the art, fixed delay, DUT mode and MONITOR
Not only variable delay time in mode, synchronization information,
There are a number of methods and apparatus for synchronizing latches that include a delay in response to receiving a latch enable signal generated by a DUT mode chip and sent to a MONITOR mode chip.

The configuration of the first synchronization units 234B-C is as follows. The synchronization unit 234C accepts input signals from an external interrupt line 166 of the I / O unit 116 via a signal line 166C (see FIG. 1) coupled to the interrupt unit 236C. These interrupt signals are prioritized in interrupt unit 236C and synchronized in synchronization unit 900C. Next, the synchronization information is transmitted to the bus 1 via the codec 132C in the DUT mode.
It is sent through 40 to the monitor mode chips 110A-B. The output of the synchronizer is coupled to latches 902B-C through signal lines 942B-C and to signal line 92B-C.
6B-C, are coupled to codecs 132B-C.

In the debug chip 110C in the DUT mode, the input signal to the latch 902C is provided by the synchronizer 900C from the interrupt unit 236C.
In contrast, in the MONITOR mode debug chip 110B, the synchronizer 900B and interrupt unit 236B are disabled. Latch 902
B receives the input signal from codec 132B via signal line 928B. This signal itself is transmitted from the codec 110C to the codec 11C via the debug bus 140.
This results from the coded interrupt information sent to OB. The codec 110C has a signal line 92
The information is generated from the second synchronization unit 234C via 6C. In the embodiment of the present invention, the DMA unit 24
6C is connected to the debug bus 140 via a signal line 278C.
A time slot for the above DMA information can be reserved. When synchronization unit 900C receives the reserve information on line 278C, it holds the current interrupt status on line 942C until DMA unit 246C releases its reserve signal. The MONITOR mode chip holds its current interrupt status output signal 928B for as long as the codec 132B receives a coded event associated with the DMA on the debug bus 142. Therefore, changes on interrupt signals 282B and 282C are synchronized to the same clock cycle. Latch 902
BC denote the synchronized interrupt signals on signal lines 282B-C as debug chips 110B in MONITOR mode and debug chips 110C in DUT mode.
To the corresponding one of the CPUs 238B to 238C. Therefore, since these output signals are the same in content and timing, synchronous processing of the interrupt signal in both chips is possible.

Accordingly, the first synchronization units 234B-C
And the second synchronization units 230B-C share similar functional features. In DUT mode, any of the synchronization units detects an asynchronous event and synchronizes it with the DUT clock. The provision of this synchronized asynchronous event to the CPU 238, DMA unit 136 and memory control unit 134 of each chip is controlled by the DUT mode chip. The change detection unit 958C of the DUT mode chip controls when to enable the second synchronizer latches 960B-C.

The first synchronization units 234B-C of each of the MONITOR mode and DUT mode chips 110B-C share operational functions similar to the second synchronization units 230B-C, for example, synchronization and latch functions. I do. As will be apparent to those skilled in the art, these synchronization and latch functions can be implemented using a variety of electrical circuits, including storage and transfer circuits and simple hold circuits, but these electrical circuits can be implemented only in these circuits. It is not limited.

The first and second synchronization units in a DUT mode device operate independently in parallel. The time slot reservation for DMA information on debug bus 140 is handled entirely within the first synchronization unit.

Encoded Event Bus All signals are encoded and multiplexed on the encoded event debug bus 140. Coding and multiplexing are performed by codec 132C in DUT mode, and decoding and demultiplexing are performed by codecs 132A-B in monitor mode. This debug system works as follows. When the power is turned on, not only the debug chip 110c in the DUT mode but also the MONITOR mode chips 110A and 110B are reset by the activated RESET signal. In one embodiment of the present invention, when the RESET signal is activated, the MONITOR mode chips 110A-B generate an enable signal on the debug bus 140, causing the DUT mode debug chip 110C to enable the debug bus 140C for that codec. Tell On the other hand, the second synchronization unit 230C of the debug chip 110C in the DUT mode synchronizes the reset signal RESET. This latter function is different from the above and may be performed by a dedicated synchronization unit not shown. next,
When RESET is de-energized, monitor 100 turns off the enable signal. Thereafter, the debug chip 110C in the DUT mode monitors the synchronized reset signal by the monitor 10C.
0, the monitor 100 then sends its internal clock and DU
The clock of the debug chip 110C in the T mode is synchronized. In one embodiment of the present invention, the internal clock can be generated by multiplying the basic frequency of 20 MHz to 200 MHz by a clock multiplying means not explicitly shown in the internal clock. This multiplying means can include a PLL circuit.

Logic Analyzer Information extracted by logic analyzer 102 from MONITOR mode chips 110A-B, such as local bus data, local bus address, as well as asynchronous events, DMA accesses and interrupts, can be easily read by computer 104, for example. (See FIG. 1). In one embodiment of the present invention, the logic analyzer may include a network connection that allows the analyzer to be monitored remotely over a network. In addition, the workstation may be used as a web server to provide information or a web browser to display on network 106. Further, such a structure allows the general-purpose computer 104 to be used over a network to control the entire debugging method. Thus, the computer is used to provide different stimuli to the debug chip 110C in DUT mode to test different portions of the program being debugged. With the preferred solution of such an analyzer system,
The advantage is that a relatively simple and inexpensive logic analyzer can be used as compared with a normal logic analyzer. The reason for this is that the main part of the data processing has been switched from the logic analyzer 102 to the computer 104. The use of suitable general software for data processing and for displaying results allows easy and efficient use of a general purpose computer for debugging operations.

With reference to the preferred embodiment of the present invention,
While the invention has been illustrated and described in detail, those skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.
Now consider these examples.

Instead of incorporating a memory unit into a circuit board, a memory unit is not provided on the circuit board, but rather a memory unit that can be connected externally is used, and no memory is provided except for a cache memory on a chip. It is also possible.

Another modification is to provide one chip in monitor mode, or more than two chips, depending on which different output signal it is desired to provide to the analyzer device.

Further, in addition to the address and data signals, other signals, for example, a status signal of the CPU or internal states of the CPU, the DMA unit, etc., can be output to the logic analyzer.

In still another embodiment, the DMA unit can be provided outside the chip instead of being integrated on the chip.

The present application refers to “computer chips and devices with enhanced debugging capabilities” as the title of the invention of 199.
Swedish Patent Application No. 98, filed May 13, 2008
Claims priority based on 01678-5.

[Brief description of the drawings]

FIG. 1 is a hardware block diagram of a test configuration using a chip having debugging capability.

FIG. 2 is a detailed hardware block diagram of the chip shown in FIG. 1;

FIG. 3 is an extended hardware block diagram of a local bus switch portion of the debug chip shown in FIGS.

FIG. 4 shows signal lines of the debug bus 140 shown in FIG.

FIG. 5 is a detailed hardware block diagram of an interface between a memory control unit and a main memory of the debug chip shown in FIGS.

FIG. 6 is a schematic block diagram showing an interface between the debug chip shown in FIGS. 1-2 and a low-speed peripheral device.

FIG. 7 is a schematic block diagram showing an interrupt process in the debug chip shown in FIGS.

FIG. 8 shows a synchronization unit of the debug chip shown in FIG.

[Explanation of symbols]

 98 Computer system 100 Monitor 102 Logic analyzer 104 Computer 106 Network 110C Chip 108 Power-on reset 120 Oscillator 112 System hardware 114 Memory 116 Input / output (I / O) unit 118 Power-on reset 130C Local bus 130C 132C Codec unit 134C Memory control unit 136C 1st local bus debug switch

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Per Sandel Sweden Lund, Lebingegatan 3

Claims (21)

[Claims] 1. A computer chip, wherein at least one synchronized unit and an interconnected CPU and cache system are integrated on top of one another, wherein the chip has one of at least two different modes of operation. Mode can be set, and the first mode is DU
A second mode is a MONITOR mode, wherein the MONITOR mode and the DUT mode are complementary, and the chips and another identical chip are in a complementary mode while the chips are in parallel. A computer chip comprising a debug bus connectable to another and the same chip so as to be able to send a signal enabling it to operate, said signal comprising a synchronization signal generated by said synchronization unit. 2. The system of claim 2, further comprising a memory controller connected to a memory bus including an address bus portion and a data bus portion, wherein the monitor mode includes at least two different test modes, and wherein the memory controller is configured for each different test mode. The computer chip of claim 1, including a mode setting circuit that allows different types of data to be output on the address bus portion. 3. The mode setting circuit includes a multiplexing circuit, an output terminal of the multiplexing circuit is connected to an address bus of a memory bus, and a first input terminal of the multiplexing circuit is used for in-chip communication. The second input terminal is connected to a data bus portion provided in the communication means, and the multiplexing circuit is connected to an address bus portion provided in the communication means. 3. The computer according to claim 2, wherein the first input terminal is connected to the output terminal when in the first mode, and the second input terminal is connected to the output terminal when in the second mode of the test mode. Chips. 4. The computer chip of claim 1, wherein said signals communicated on a debug bus further include CPU and DMA unit status information. 5. The computer chip of claim 1, wherein the synchronization signal includes a signal carrying synchronization information for an external asynchronous signal received by the chip and a signal carrying a synchronization signal for an interrupt. 6. A main chip on which at least one synchronization unit, a CPU, a cache system, a DMA unit, and a memory controller, all of which are interconnected, are integrated. Configurable to one of two different modes of operation, the first mode being a DUT mode,
The second mode is the MONITOR mode.
The ITOR mode and the DUT mode are complementary,
Debug connectable to another computer device containing the same main chip to send a signal that can operate a computer device and another computer device in parallel while the main chip is in a complementary mode A computing device further comprising a port. 7. A CPU including a first computer device and a second computer device, each of which includes a main chip, the main chip being at least one synchronization unit and all interconnected CPUs.
And a cache system, a DMA unit, and a memory controller including a main chip integrated thereon, each chip being configurable to one of at least two different operating modes, wherein the first mode is: DU
T operating mode, the second mode is a MONITOR mode, the MONITOR mode and the DUT operating mode are complementary, each computer device further includes a debug port, and the debug port allows the first computer and the second computer to communicate with each other. The computer is interconnected,
The main chip of the first computer is set to the DUT mode, and the main chip of the second computer is set to MONITO.
A first computer including a first memory bus derived from a memory controller of the first computer device, wherein a memory controller of a second computer device is configured to be in an R mode, wherein a first memory bus is derived from a memory controller of the first computer device; A debug system connected at least partially to the first memory through a two memory bus. 8. The system according to claim 7, further comprising a logical analyzer connected to an address bus portion of said second memory bus.
Debug system as described. 9. The debugging system according to claim 8, wherein said logical analyzer has a network interface connectable to a web server of an operator's computer. 10. The second computer is identical to another chip and includes at least one other chip set in a MONITOR mode, wherein the logical analyzer is derived from another memory controller of the another chip. Connected to the address bus portion of the memory,
9. The debugging system according to claim 8, wherein the ONITOR mode includes at least two different test modes, wherein the at least two MONITOR mode chips are set to different test modes, and output different information to respective address bus portions. 11. A debug circuit for incorporation into an integrated circuit chip including internal components interconnected to perform processing on a chip and address pins, data pins and clock pins for interfacing with the chip. Wherein the debug circuit includes a debug switch having an input terminal, an output terminal, and a control connection, wherein the input terminal is coupled to a predetermined component of the internal component, and the output terminal is connected to an address pin. The control connection is coupled to a mode select pin for interfacing with the chip, and one of the inputs is connected to the output so that the debug switch can monitor processing on the chip at the address pins. A debug circuit responsive to the mode signal on the mode select pin to couple. 12. A synchronizing circuit having an input, an output and a control connection, wherein the control connection is coupled to the mode select pin, the input is coupled to an asynchronous signal source, and the output is An end coupled to at least one of the internal components, and responsive to a first mode select signal at a mode select pin such that the synchronization circuit adopts a first configuration; Latching the asynchronous signal from a signal source, outputting an enable signal to a debug bus during a time when there is no signal change at an input terminal, and releasing the asynchronous signal to an internal component of a chip for processing. 12. The debug circuit according to claim 11, wherein said asynchronous signal is unlatched. 13. A synchronizing circuit having an input, an output, and a control connection, wherein the control connection is coupled to the mode select pin, the input is coupled to an asynchronous signal source, and the output is An end coupled to at least one of the internal components, and responsive to a second mode select signal at a mode select pin such that the synchronization circuit employs a second configuration; Latching the asynchronous signal from a signal source, responsive to an enable signal on a debug bus, and unlatching the asynchronous signal to release the asynchronous signal to internal components of the chip for processing. 13. The debugging circuit according to claim 12, wherein: 14. A synchronizing circuit having an input, an output, and a control connection, wherein the control connection is coupled to the mode select pin, the input is coupled to an asynchronous signal source, and the output is An end coupled to at least one of the internal components, and responsive to a first mode select signal at a mode select pin such that the synchronization circuit adopts a first configuration; Latching the asynchronous signal from the signal source, outputting a coded signal corresponding to the asynchronous signal on the debug bus, and releasing the asynchronous signal to internal components of the chip for processing. Unlatch the signal,
The debug circuit according to claim 11. 15. A synchronization circuit having an input, an output, and a control connection, wherein the control connection is coupled to the mode select pin, the input is coupled to an asynchronous signal source, and the output is An end is coupled to at least one of the internal components, and is responsive to a second mode select signal such that the synchronization circuit employs a second configuration, wherein the second configuration includes a debugger. Receiving the coded signal of the bus,
Decoding the coded signal, latching the decoded signal, and after a predetermined delay time, unlatching the decoded signal to release the decoded signal to internal components of the chip for processing. 15. The debug circuit according to claim 14, wherein: 16. The internal components on the integrated circuit chip include data, digital signals, graphic signals, video signals,
The debug chip of claim 11, wherein the debug chip performs at least one of a group of processing consisting of an audio signal, a pattern recognition signal, and programmable logic. 17. A processor, a cache memory,
An integrated circuit comprising a memory controller unit and a local bus coupling the processor, the cache memory and the memory controller unit to each other to perform processing on a chip and address pins, a data pin and a clock pin for interfacing with the chip. A debug circuit for incorporation into a circuit chip, comprising: a debug switch having an input terminal, an output terminal, and a control connection, wherein the input terminal has an address of the memory controller unit, a data portion of the local bus, and an address of the local bus. And the output terminal is connected to an address pin, the control connection is connected to a mode selection pin for interfacing with the chip, and the debug switch is connected to a mode signal on the mode selection pin. To A debug circuit responsive and coupling one of the inputs to the output to monitor processing on the chip at the address pins. 18. A test device for monitoring an internal state of a chip during execution of a program code, comprising: an addressable memory having an address pin and a data pin, the addressable memory being suitable for storing the program code. An internal component including the same first chip and a second chip, each of which performs processing thereon, and internal components, and pins for interfacing with each chip, including address pins and data pins; A debug switch for coupling one of two input terminals to the address pin, wherein the address pin of the first chip is coupled to an address generating component of the internal components via the debug switch; So that the address pins of the chip monitor the processing of other internal components
Another of the internal components is coupled via the debug switch, including an address portion and a data portion, wherein the address portion is coupled to the address pins of the first chip and the addressable memory. A test bus further comprising a system bus having a data portion coupled to the first chip, the second chip, and data pins of the addressable memory. 19. The test apparatus according to claim 18, further comprising means for synchronizing execution of the program code on the first chip with execution of the program code on the second chip. 20. The test apparatus according to claim 18, further comprising means for monitoring the address pins of the second chip and monitoring processing related to another part of the internal component. 21. The debug switch corresponding to the first chip and the second chip couples the address pins of the corresponding chips of the first chip and the second chip to the address generating component of the internal component. Responsive to a first mode signal on a mode select pin, coupling the address pin of the second chip to another of the internal components, and monitoring processing on the chip at the address pin. 19. The test device of claim 18, responsive to a second mode signal on the mode select pin.