JP2000010527A - Liquid display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device having excellent display quality by preventing respective pixels from receiving the influence of previous pixels or next pixels in spite of a variation in the electrical characteristics of TFTs constituting a signal line driving circuit. SOLUTION: The signal line driving circuit in this device has a signal line driving circuit 2 formed on the same substrate as the substrate of a pixel array section 1 and an external driving circuit 4 formed on another substrate. The signal line driving circuit 2 has a shift register 22 for controlling the gate voltage of respective analog switches 21 and a differentiating circuit 23 connected to the respective output terminals of the shift register 22. A video bus line L1 for supplying video signals is connected to the one-side ends of the respective analog switches 21. The respective analog switches 21 turn on and off according to the shift pulses outputted from the shift register 22. The timing to form the pulses of a narrow width by differentiating the output of the shift register 22 by the differentiating circuit 23 and to supply the video signals to the video bus line L1 by feeding these pulses back to the external driving circuit 4 is set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a signal line in a liquid crystal display device, and particularly to a case where at least a part of a signal line driving circuit is formed on the same substrate as a pixel array portion.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device includes a pixel array section in which a TFT (Thin Film Transistor) for displaying a pixel is arranged near each intersection of a signal line and a scanning line, and a signal line. It has a signal line driving circuit for driving and a scanning line driving circuit for driving each scanning line.

[0003] In recent years, in order to reduce manufacturing costs, examples of forming at least a part of a signal line driving circuit or a scanning line driving circuit on the same transparent insulating substrate as a pixel array section have been increasing.

One of the driving methods of the signal line driving circuit is as follows.
There is known a driving method in which an analog switch is connected to a video bus line for supplying a video signal, and the analog switch is turned on / off according to a shift pulse output from a shift register.

To improve the display quality, it is necessary to match the output timing of the shift pulse output from the shift register with the timing of the video signal on the video bus line.

[0006]

Ideally, it is desirable to switch the video signal in synchronization with the fall of the shift pulse. However, each TFT in the signal line driving circuit
Are not necessarily the same, and the timing of the shift pulse and the timing of the video signal are likely to be shifted. When such a timing shift occurs, the switching operation of the analog switch and the timing at which the corresponding video signal is supplied to the analog switch greatly deviate from each other, and the video signal to be written to the previous pixel or the next pixel is written to each pixel. As a result, a ghost is generated, and the display quality is remarkably deteriorated.

[0007] The present invention has been made in view of such a point, and an object thereof is to provide a liquid crystal display device having excellent display quality.

[0008]

According to a first aspect of the present invention, a plurality of signal lines for supplying a video signal to each of a plurality of pixel display units and a shift pulse are sequentially transmitted. A shift register for transferring and outputting in parallel, a plurality of differentiating circuits connected to respective outputs of the shift register, and converting image data input from the outside into parallel analog signals in synchronization with the shift pulse and converting each of the signal lines And a timing setting circuit that sets the input timing of the image data to the serial-parallel conversion circuit based on each output of the plurality of differentiating circuits.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display device according to the present invention will be specifically described with reference to the drawings. FIG.
1 is a block diagram showing a configuration of a main part of an embodiment of a liquid crystal display device according to the present invention. FIG. 2 is a schematic block diagram showing an entire configuration of the liquid crystal display device of FIG. As shown in FIG. 2, the liquid crystal display device according to the present embodiment has a pixel array unit 1 in which signal lines S1 to Sn and scanning lines G1 to Gn are arranged vertically and horizontally.
And a signal line driving circuit 2 for driving each signal line, a scanning line driving circuit 3 for driving each scanning line, and an external driving circuit 4 for controlling the signal line driving circuit 2 and the scanning line driving circuit 3.

The pixel array section 1 has a pixel TFT 5 formed near each intersection of a signal line and a scanning line.
A scanning line is connected to the gate electrode of the FT 5, a signal line is connected to one of the source electrode and the drain electrode, and a liquid crystal capacitance 51 and an auxiliary capacitance 52 are connected to the other.

The signal line driving circuit 2 and the scanning line driving circuit 3
The external drive circuit 4 is formed on the same transparent insulating substrate as the pixel array unit 1, and the external drive circuit 4 is formed on a different substrate from the pixel array unit 1. The transistors (TFTs) in the signal line driving circuit 2 and the scanning line driving circuit 3 are formed by a process similar to that of the pixel TFT 5.

The signal line driving circuit 2 includes an analog switch 21 provided for each signal line,
1 and a differentiating circuit 23 connected to each output terminal of the shift register 22.
And

A video bus line L1 for supplying a video signal is connected to one end of each analog switch 21. Each analog switch 21 turns on and off according to a shift pulse output from the shift register 22.

The shift register 22, as shown in FIG. 3, shows a combination of clocked inverters 31-34 and inverters IV1 and IV2. The shift register 22 receives the + clock CK, the −clock / CK, and the start pulse from the external drive circuit 4. The clocked inverters 31 to 34 in the shift register 22
The operation is performed based on + clock CK and −clock / CK having opposite logics to each other. The shift register 22 starts the shift operation when the start pulse is input.

Each differentiating circuit 23 differentiates a signal output from a corresponding output terminal of the shift register 22. FIG.
As shown in FIG.
1 and Q2 and a capacitor C1. Transistor Q
1 is grounded, and the output of the shift register 22 is supplied to the gate electrode of the transistor Q2 via the capacitor C1.

The transistor Q2 shown in FIG. 3 performs an amplifying operation. When a shift pulse is output from the shift register 22, the output of the differentiating circuit 23 has a sharp rising edge and a gentle falling edge as shown in FIG. It becomes a signal waveform.

The output terminals of the differentiating circuits 23 are connected to each other and input to the external driving circuit 4, as shown in FIG. Since the timing of the shift pulse output from the shift register 22 differs for each output terminal, the waveform of the signal input to the external drive circuit 4 is a waveform in which a plurality of differential signals shown in FIG. Become.

FIG. 4 is a circuit diagram showing a detailed configuration of the external drive circuit 4, and FIG. 5 is a timing chart showing signal waveforms of various parts in the external drive circuit 4. As shown in FIG. 4, the external drive circuit 4 includes a resistor R1 and a two-stage cascaded inverter IV.
3, IV4, diodes D1 and D2 cascaded between a power supply terminal VDD2 and a ground terminal, an image memory 41 for storing digital signals corresponding to video signals, and an image memory 41.
And a D / A converter 42 for converting a digital signal read from the D / A converter into an analog video signal.

The output of the differentiating circuit 23 is connected to the inverter IV in FIG.
3 and IV4, a narrow square wave pulse is obtained as shown by the waveform b in FIG. The timing of this pulse is synchronized with the timing of the shift pulse output from the shift register 22 in FIG.

More specifically, after the shift pulse is output and the corresponding analog switch 21 is turned on, the corresponding video signal is supplied to the video bus line L1.
A diode D is connected to the output terminals of inverters IV3 and IV4.
1 and D2, the output voltage level of the inverter IV4 is set to a voltage between the power supply voltage VDD2 and the ground voltage.

The image memory 41 reads out a digital signal corresponding to the video signal and supplies it to the D / A converter 42 in accordance with the timing of the output pulse of the inverter IV4. D
The / A converter 42 converts a digital signal into an analog video signal and supplies it to the video bus line L1. In addition,
The image memory 41 corresponds to a timing setting circuit.

As described above, in the present embodiment, the output of the shift register 22 is differentiated by the differentiating circuit 23 to generate a narrow square wave pulse, and this pulse is fed back to the external drive circuit 4 so that the video bus line L1 Since the timing for supplying the video signal to the TFT is set, the timing of the video signal and the timing of the shift pulse can be matched even if the electrical characteristics of the TFTs constituting the signal line driving circuit 2 vary. The pixel is not affected by the previous pixel or the next pixel, and the display quality can be improved.

[0023]

As described above in detail, according to the present invention, the timing for supplying the video signal to each of the signal lines is set based on the differential signal of the shift pulse output from the shift register. Therefore, even if the electrical characteristics of the TFTs constituting the signal line driving circuit including the shift register and the like vary, the output timing of the shift pulse can be matched with the timing of the video signal.
The display quality of the liquid crystal display device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a schematic block diagram showing the entire configuration of the liquid crystal display device of FIG. 1;

FIG. 3 is a circuit diagram showing a detailed configuration of a shift register and a differentiating circuit.

FIG. 4 is a circuit diagram showing a detailed configuration of an external drive circuit.

FIG. 5 is a timing chart showing signal waveforms at various parts in the external drive circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pixel array part 2 Signal line drive circuit 3 Scan line drive circuit 4 External drive circuit 5 Pixel TFT 21 Analog switch 22 Shift register 23 Differentiator 31-34 Clocked inverter IV1, IV2 Inverter

Continuing from the front page (72) Inventor Kazuo Nakamura 1-9-2 Hara-cho, Fukaya-shi, Saitama F-term in Toshiba Fukaya Electronics Factory (reference) 2H093 NA16 NC13 NC16 NC21 NC22 NC23 NC29 NC34 ND15 ND34 5C006 AF51 AF72 AF82 BB16 BC13 BC20 BF03 BF11 FA16

Claims (5)

[Claims] 1. A plurality of signal lines for supplying a video signal to each of pixel display units arranged in a row, a shift register for sequentially transferring shift pulses and outputting in parallel, and a plurality of shift lines connected to respective outputs of the shift register. A serial-parallel conversion circuit that converts image data input from the outside into a parallel analog signal in synchronization with the shift pulse and outputs the parallel analog signal to each signal line, based on each output of the plurality of differentiation circuits And a timing setting circuit for setting an input timing of image data to the serial-parallel conversion circuit. 2. A serial / parallel conversion circuit, comprising: a D / A conversion circuit that converts the image data into an analog video signal and outputs the analog video signal to a video bus; and converts the analog signal on the video bus into an input timing of the shift pulse. The liquid crystal display device according to claim 1, further comprising a plurality of analog switches that sample and output the parallel analog signals to each signal line. 3. The timing setting circuit has a memory for storing the image data, and sets a read timing of the image data stored in the memory based on outputs of a plurality of differentiating circuits. The liquid crystal display device according to claim 1, wherein: 4. The method according to claim 1, wherein the shift register and the plurality of differentiating circuits are formed on the same substrate as the pixel display unit, and the timing setting circuit is formed on a substrate different from the pixel display unit. The liquid crystal display device according to claim 1. 5. The liquid crystal display device according to claim 1, wherein the output of the differentiating circuit is connected to a common bus, and is input to the timing setting circuit via the common bus.