JP2000009813A - Method and device for preparing test pattern of logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for preparing the test pattern of a logic circuit capable of obtaining a high rate of failure detection with a compact test pattern. SOLUTION: The device for preparing the test pattern of a logic circuit is provided with a means 112 to set the difference between the number of times that a gate input signal line should be selected (the product of the probability of selecting the gate input signal line and the number of times that the gate becomes an object of justification operation and that an input signal line for which a signal value 0 or 1 is allotted is selected) and the number of times that the gate input signal line is actually selected as bias, a means 116 to obtain the probability of selecting the gate input signal line, and a mans 140 to select the gate input signal line to set 0 and 1 according to the selection provability in justification processing used for preparing the test pattern of a logic circuit. Random selection according to the selection probability (2) and selection by a random target value on a controllability scale may be adopted (3) as well as selection by the probability of selecting the gate input signal line (1) as selection criteria.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for creating a test pattern for a logic circuit, and more particularly to a logic circuit for obtaining a high fault detection rate with a small number of test patterns by a test pattern generation algorithm including a justification process. The present invention relates to a test pattern creation method and a creation device.

[0002]

2. Description of the Related Art A test pattern to be applied to a logic circuit is required to check whether or not a fault exists in a logic circuit and, if so, what kind of fault it is.
To create a test pattern, first, circuit information such as a logical function of a circuit to be tested, a logical function of a circuit element, and a connection between elements is captured. Next, what kind of failure is detected is determined. In order to increase the efficiency of test pattern generation and the efficiency of the test itself, for a logically equivalent fault, a representative fault is determined, and an equivalent fault analysis is performed to reduce the number of faults for which a test pattern is to be generated. A test pattern for detecting the analyzed representative fault is generated. For the generated test pattern, a failure simulation is executed, and a failure detection rate indicating which% of the initially assumed failures has been detected is determined. When the detected failure detection rate is low, the test pattern generation and the failure simulation are repeated for the failure that cannot be detected, and when a predetermined failure detection rate is reached, the generated test pattern is registered as a failure dictionary, and the actual logic is registered. Prepare for circuit failure test.

[0003] As a test pattern generation algorithm, for example, there is a D algorithm. When a test pattern is applied to a logic circuit, a path through which an error propagates due to a failure is called an activated path. Activating multiple pathways simultaneously is called multi-path activation. In the D algorithm, a value that becomes 1 (0) in a normal state and 0 (1) in a failure state is defined as D (D ′), and a cube operation including this value is used,
Activate multiple paths passing through the fault location to generate a test pattern.

The justification process in the D algorithm or the like is an operation of allocating a signal value combination according to an output value to a gate input signal line for a gate that requires a signal value of 0 or 1 to be set to an input signal line. is there.

When the output signal value of the AND gate is 1 or O
When the output signal value of the R gate is 0 or the like, the combination of signal values of the gate input signal line is not all 1 or all 0.

However, when the output signal value of the AND gate is 0, it is sufficient to assign 0 to only one of the gate input signal lines. , There is a choice. Also, OR
When the output signal value of the gate is 1, the gate input signal line to which 1 is assigned has room for selection.

The most common selection method is the controllability measure of the gate input signal line (0 controllability measure for AND gates and NAND gates, 1 controllability measure for OR gates and NOR gates). Is a method of assigning 0 or 1 to the best gate input signal line, that is, the gate input signal line with the easiest signal value setting. The calculation rule of the controllability scale will be described later with reference to the drawings.

The D algorithm was developed in 1967 by IEEE Transact.
ions on Electronic Computers: Vol.EC-16, No.5, p
p.567-579, `` Programmed Algorithms to Compute Tes
ts toDetect and Distinguish between Failures in Lo
gic Circuites "and in Computer Design and Testing by Hideo Fujiwara (Kogyo Tosho, 1990).

As another selection method, it is conceivable to sequentially change the gate input signal lines to which 0 or 1 is assigned in the manner of a so-called cyclic back trace.

[0010] The cyclic back trace is described in 1993 IEEE Tran.
sactions on Computer−Aided Design of Integrated
Circuites and Systems: Vol.12, No.7, pp.1040-1049, I
rithPomeranz, Lacshmi N. Reddy, and Sudhakar M. Re
ddy `` COMPACTEST: A Methodto Generate Compact Test
Sets for Combinational Circuits.

[0011]

When a gate input signal line to which 0 or 1 is assigned is selected on the basis of the controllability scale, setting of 0 or 1 is difficult for a gate input signal line whose signal value is difficult to set. Less demanding,
Test pattern generation time is short, but the generated test set is compact (the number of test patterns is small)
do not become.

On the other hand, if the gate input signal lines to which 0 or 1 are assigned are changed in order in the same manner as in the cyclic back trace, a compact test set is created, but the gate input signal lines for which setting of signal values is difficult are difficult. Since the setting of 0 or 1 is required, the test pattern generation time increases.

An object of the present invention is to provide a method and an apparatus for creating a test pattern of a logic circuit which can obtain a high fault coverage with a compact test pattern.

[0014]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for creating a test pattern of a logic circuit including a justification process, wherein a selection probability of a gate input signal line is calculated and the process proceeds. If it becomes necessary to select a gate input signal line, a test pattern creation method for a logic circuit that selects a gate input signal line based on the selection probability is proposed.

According to another aspect of the present invention, there is provided an apparatus for generating a test pattern for a logic circuit including a justification process, comprising: a selection probability calculation unit for calculating a selection probability of a gate input signal line; In the case where it becomes necessary to select a gate input signal line, a test pattern creation device for a logic circuit including a gate input signal line selection unit for selecting a gate input signal line by a procedure using a selection probability is proposed. .

In order to achieve the above object, the present invention further provides a logic circuit test pattern creating apparatus including a justification process, wherein a selection probability calculation section for calculating a selection probability of a gate input signal line, A gate input signal line selection unit for selecting a line, wherein the gate input signal line selection unit selects the best gate input signal line evaluated by the evaluation value of the gate input signal line, and the gate input signal line is selected. In such a case, while the evaluation value is changed in a direction in which the gate input line is not easily selected, when the evaluation value is changed in a direction in which the gate input line is easily selected, a unit that changes only the value according to the selection probability is used. We propose a test pattern creation device for a certain logic circuit.

In order to achieve the above object, the present invention provides a logic circuit test pattern creating apparatus including a justification process, comprising: a selection probability calculation unit for calculating a selection probability of a gate input signal line; A gate input signal line selecting unit for selecting, when the gate input signal line selecting unit assigns a predetermined signal value to a part of the gate input signal line by the justification process, evaluates the gate input signal line The present invention proposes a logic circuit test pattern generation device which is a means for selecting a gate input signal line having the best evaluation based on a value and changing an evaluation value so that only a value corresponding to a selection probability is easily selected.

According to another aspect of the present invention, there is provided a test pattern creating apparatus for a logic circuit including a justification process, comprising: a selection probability calculation unit for calculating a selection probability of a gate input signal line; A gate input signal line selection unit for selecting a line, wherein the gate input signal line selection unit
When a predetermined signal value is assigned to a part of the gate input signal line by the justification process, the gate input signal line evaluated best by the evaluation value of the gate input signal line is selected, and the evaluation value is input to the gate input signal line. This is a means for setting an index by comparing the number of times a signal line is selected and the number of times the signal line is actually selected, and a test of a logic circuit in which the number of times the selected number of times is calculated based on the selection probability. We propose a pattern creation device.

In order to achieve the above object, the present invention further provides a logic circuit test pattern creating apparatus including a justification process, wherein a selection probability calculation unit for calculating a selection probability of a gate input signal line; A gate input signal line selection unit for selecting a line, wherein the gate input signal line selection unit assigns a predetermined signal value to a part of the gate input signal line by the justification process, based on the selection probability. A logic circuit test pattern creation device which is a means for randomly selecting a gate input signal line.

Any of the test pattern generating apparatuses for a logic circuit may include a controllability scale calculation unit that calculates a controllability scale of the gate input signal line. In this case, the selection probability calculation unit includes a controllability control unit. It is a means to calculate the selection probability based on the scale.

According to the present invention, in order to achieve the above object, a controllability scale calculator for calculating a controllability scale of a gate input signal line in a logic circuit test pattern preparation device including a justification process, A gate input signal line selection unit for selecting an input signal line, wherein the gate input signal line selection unit assigns a predetermined signal value to a part of the gate input signal line by a justification process; Proposes an apparatus for generating a test pattern for a logic circuit, which is a means for selecting a gate input signal line based on the target value of the controllability scale calculated by the above and the controllability scale calculated by the controllability scale calculation unit. .

According to the present invention, the input signal line having a small controllability scale is selected over the input signal line having a large controllability scale while maintaining the variety of selection of the gate input signal lines according to the following policy. Make it easy to be.

(1) A selection probability calculation unit for calculating a selection probability of a gate input signal line and a gate input signal line selection unit for selecting a gate input signal line are provided. The gate input signal line evaluated best by the evaluation value of the line is selected, and when the gate input signal line is selected, the evaluation value is changed to a direction in which the gate input line is hardly selected. On the other hand, when the evaluation value is changed in a direction in which the gate input line is easily selected, only the value corresponding to the selection probability is changed. The selection probability of the gate input signal line is calculated based on the controllability measure of the gate input signal line calculated by the controllability measure calculation unit.

(2) A selection probability calculation unit for calculating the selection probability of the gate input signal line, and a gate input signal line selection unit for selecting the gate input signal line are provided, and the gate input signal line selection unit operates according to the selection probability. The gate input signal line is randomly selected. The selection probability of the gate input signal line is calculated based on the controllability measure of the gate input signal line.

(3) A controllability scale calculator for calculating a controllability scale of the gate input signal line and a gate input signal line selector for selecting the gate input signal line are provided. And selecting a gate input signal line based on the target value of the controllability scale calculated by the random algorithm and the controllability scale.

According to these principles of the present invention, a gate input signal line having a small controllability scale is made higher than a gate input signal line having a large controllability scale while maintaining the variety of selection of gate input signal lines. Is also easier to select. As a result, a compact test set can be created at high speed.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to FIGS.
An embodiment of a method and an apparatus for creating a test pattern of a logic circuit according to the present invention will be described. In the following description,
The processing target is a failure of the output edge of the logic circuit, and only the processing related to the justification processing of the D algorithm is handled. Only an example of test pattern generation of the failure of the output edge of the logic circuit is shown. If used, it is possible to generate a test pattern that can accurately detect a fault at an arbitrary position in a logic circuit.

Embodiment 1 FIG. 1 is a block diagram showing an outline of a hardware configuration of a test pattern generation device for a logic circuit according to the present invention. This test pattern generation device includes an input unit 202, an output unit 206, and a main processor 210. The main processor 210 includes an input / output interface 212, a CPU 214, and a memory 216.

FIG. 2 is a block diagram showing a functional configuration of an embodiment of a logic circuit test pattern generating apparatus according to the present invention. This test pattern generation device includes an input unit 10
2, an output unit 106, and a test pattern generation unit 110. The test pattern generating unit 110 includes a bias initial setting unit 112, a controllability scale calculating unit 114, a selection probability calculating unit 116, a target fault selecting unit 118, a signal value / unjustified gate set initial setting unit 122, Test pattern generation end determination unit 125 and gate selection unit 130
A gate input signal line selection necessity determination unit 135, a gate input signal line selection unit 140, and a signal value allocation unit 180
And an unjustified gate set updating unit 185 and a test pattern storage unit 190.

The test pattern generation unit 110 of FIG. 2 is stored as software in the memory 216 of FIG. 1, and the input unit 102 and the output unit 106 of FIG. 2 correspond to the input unit 202 and the output unit of FIG. 206.

FIG. 3 is a diagram showing rules for calculating the controllability scale. C0 is the 0 controllability scale, and C1
Is one controllability measure. For a gate with three or more inputs, the calculation rule of the controllability scale is the same, only the number of terms increases. C0 for circuit input edge
After setting = C1 = 1, by applying the rule of FIG. 3 in order from the input side, the controllability scale of each signal line can be calculated.

FIG. 4 is a chart for explaining a system of signal values used in the D algorithm. In the D algorithm, five signal values of 0, 1, D, D ', and X are used. Among these, the four signal values other than X can be regarded as the following pairs, respectively. 0 in the D algorithm
Represents 0 in a circuit without a fault and 0 in a circuit with a fault. 1 represents 1 in a circuit without a fault and 1 in a circuit with a fault. D represents 1 (normal component) in a circuit having no failure and 0 (failure component) in a circuit having a failure. D 'represents 0 in a fault-free circuit and 1 in a faulty circuit.

FIG. 5 is a flowchart showing a processing procedure of the test pattern generation device of FIG.

In step 312, the bias initial setting section 112 initializes the bias of all input signal lines of all gates to zero. The bias is a difference between the appropriate number of times the gate input signal line is selected and the number of times the gate input signal line is actually selected. Here, the appropriate number of times of selection is the product of the selection probability of the gate input signal line and the number of times that the gate has selected the input signal line to be assigned a signal value 0 or 1 as a target of the justification operation. is there. For example, a gate has been selected for an input signal line to which a signal value of 0 or 1 has been selected as a target of the justification operation three times in the past, and the selection probability of an input signal line having that gate has been selected at 0.3. It was 1
If only one time, the bias of the input signal line is 1-0.3
× 3 = 0.1. The selection probability of the gate input signal line is
It is calculated by a selection probability calculation unit 116 described later. The bias indicates whether the number of selections of the gate input signal line is excessive or insufficient,
A positive value indicates that the number of selections is too large, and a negative value indicates that the number is too small.

In step 314, the controllability scale calculator 114 calculates Goldstein's controllability scale. After setting the 0 controllability scale C0 = 1 and the controllability scale C1 = 1 for the circuit input edge, the rules in FIG. 3 are applied in order from the gate on the input side.

In step 316, the selection probability calculation unit 11
6 calculates the selection probability of the input signal line of the AND / NAND / OR / NOR gate.

In step 318, the target fault selector 118 determines whether a target fault, that is, a fault for which a test pattern is to be generated, can be selected.
If it can be selected, the process proceeds to step 320; otherwise, the process ends.

In step 320, the target fault selection section 118 selects a target fault. Circuit test pattern generation means that obtaining a set of test patterns that can detect all faults for which test pattern generation is to be performed is a repetition of the operation of picking up one fault and creating a test pattern for it. And the target fault is a fault picked up as a target of test pattern generation.

In step 322, the signal value / unjustified gate set initial setting unit 122 initializes the circuit signal value and the unjustified gate set. The signal value of all signal lines is X, and the set of unjustified gates is only one gate that outputs a fault point. Here, an unjustified gate is a gate that requires a signal value of 0 or 1 to be set to an input signal line, and is defined as a gate that satisfies all of the following conditions. (1) The output signal value is one of 0, 1, D, and D '. (2) The input signal values are all 0, 1, or X. (3) At least one of the input signal values is X.

(4) The input signal value X is successfully rewritten to 0 or 1 and a gate operation is performed, and a result different from the normal component of the output signal value is obtained (when the normal component of the output signal value is 0, 1 or 1). To get 0).

In step 325, the test pattern generation end determining unit 125 determines whether the test pattern generation for the current target fault is to be ended. If the unjustified gate set is an empty set, it is determined that test pattern generation has been completed, and the process proceeds to step 390; otherwise, the process proceeds to step 330.

In step 330, the gate selection unit 130
However, from the set of unjustified gates, one gate having the worst controllability measure of the output signal line (the most difficult to set the signal value) is selected.

In step 335, the gate input signal line selection necessity judging section 135 judges the necessity of gate input signal line selection. If the combination of the selected gate and its output value is any of the following, 0 or 1 is assigned to only one of the gate input signal lines, so selection is determined to be necessary, and Otherwise, it is determined that selection is unnecessary. (1) The selected gate is an AND gate, and the normal component of the output signal value is 0. (2) The selected gate is a NAND gate, and the normal component of the output signal value is 1. (3) The selected gate is an OR gate, and the normal component of the output signal value is 1. (4) The selected gate is a NOR gate, and the normal component of the output signal value is 0.

In step 340, the gate input signal line selector 140 selects a gate input signal line to which a signal value 0 or 1 is assigned.

In step 380, the signal value allocating unit 1
80 assigns the signal values shown in FIG.

In step 385, the unjustified gate set updating unit 185 updates the unjustified gate set, and returns to step 325.

In step 390, the test pattern storage section 190 stores the test pattern, and
Return to

Next, in FIG. 5, step 316 of calculating the selection probability and step 340 of selecting the gate input signal line will be described in more detail.

FIG. 7 is a flowchart showing details of the processing procedure of step 316 in FIG. 5 in which the selection probability calculation section 116 calculates the selection probability.

In step 405, it is determined whether there is an AND / NAND / OR / NOR gate for which the selection probability of the input signal line has not been calculated. If there is such a gate, the process proceeds to step 410; To end.

In step 410, one AND / NAND / OR / NOR gate for which the selection probability of the input signal line has not been calculated is taken out.

In step 415, the evaluation value of each input signal line (the reciprocal of the kth power of the 0 controllability scale for the AND gate and the NAND gate, and the 1 controllability scale of the OR control gate and the NOR gate). (Reciprocal of k-th power, where k is a positive number)
Is calculated.

In step 420, the evaluation values of the input signal lines are normalized (the sum is set to 1), and the result is used as the selection probability of each input signal line.

In step 425, the process returns to step 405.

The larger the selection probability calculation parameter k, the better the controllability scale (easy to set the signal value). The larger the selection probability of the input signal line, and the worse the controllability scale (the more difficult the signal value to set). ) The selection probability of the input signal line is reduced, and the process approaches to the process of assigning 0 or 1 to the gate input signal line in which the signal value is most easily set. Therefore, although the test pattern generation time is short, the generated test set is not very compact. On the other hand, k is small
The input signal line having a better controllability scale and the input signal line having a poorer controllability scale have a smaller selection probability (closer to 0), and the process approaches the process of sequentially changing the gate input signal lines to which 0 or 1 is assigned.
Thus, a compact test set is created,
The test pattern generation time increases. Thus, the selection probability calculation parameter k is a parameter that governs the characteristics of the algorithm.

FIG. 8 shows a gate input signal line selection section 140.
Selects the gate input signal line in step 340 of FIG.
6 is a flowchart showing details of the processing procedure of FIG.

In step 505, the selection probability is subtracted from the biases of all the input signal lines of the target gate (the gate selected by the gate selection unit 130).

At step 510, the input signal line having the smallest bias is selected from the input signal lines to which the signal value X is assigned.

In step 515, 1 is added to the bias of the selected input signal line.

Hereinafter, a specific example of test pattern generation according to the present embodiment will be described with k = 1.5.

FIG. 9 is a diagram showing an example of a failure in a logic circuit. In this case, it is assumed that the test pattern generation target faults are only the stuck-at-0 faults of the output signal lines of the gates C, D, and E, and are selected in this order.

In step 312, the biases of all input signal lines of all gates are initialized to zero. At step 314,
Compute Goldstein's controllability measure (FIG. 3).

At step 316, gates A, B, C, D, and E
Of the input signal line is calculated.

FIG. 10 is a diagram showing the controllability scale and selection probability of each gate input line. In order from the left, a gate, an input signal line, its 1 controllability scale, 0 controllability scale, and selection probability are shown.

In steps 318 and 320, it is assumed that the 0 stuck-at fault of the output signal line of the gate C is selected as the target fault. Accordingly, the signal value of the output signal line of the gate C is set to D (representing 1 for a fault-free circuit and representing 0 for a faulty circuit).

At step 322, the signal values of all the signal lines are X
And the unjustified gate set is calculated as {C}.

If it is determined in step 325 that "test pattern generation is to be continued" and if gate C is selected in step 330, it is determined in step 335 that "selection of gate input signal line is unnecessary".

Proceeding to step 380, the output signal line of the gate B and the signal value of the circuit input edge e are respectively set to 1, and in step 385, the set of unjustified gates is updated to {B}. Return to

If it is determined in step 325 that "test pattern generation is to be continued" and if gate B is selected in step 330, it is determined in step 335 that "selection of gate input signal line is necessary" and gate input signal The process for selecting a line is started.

FIG. 11 is a diagram showing the transition of the process of selecting the input signal line of the gate B. In order from the left, the target failure, the input signal line of the gate B, the selection probability, and step 5
5 shows the bias in step 05, the selection of the input signal line in step 510, and the bias in step 515. Since the 1 controllability scales of the circuit input edges a and b and the output signal line of the gate A are 1, 1, and 3, respectively, the selection probability ratio is 1: 1: 0.192.

In step 505, the initial value of the bias 0
Is subtracted from the selection probability of the input signal line.

In step 510, the circuit input edge a having the smallest bias is selected, and in step 515,
One is added to the bias of the circuit input edge a.

At step 380, the circuit input edges a,
b and the signal value of the output signal line of the gate A are 1,
X, X are set, and in step 385, the unjustified gate set is updated to an empty set.

At step 325, it is determined that “test pattern generation has been completed”, and at step 390, the test pattern (1, X, X, X, 1, X, X) is stored.
Return to

In steps 318 and 320, it is assumed that the 0 stuck-at fault of the output signal line of the gate D is selected as the target fault. Accordingly, the signal value of the output signal line of the gate D is set to D.

At step 322, the signal values of all the signal lines are X
And the set of unjustified gates is calculated as {D}. If it is determined in step 325 that “test pattern generation continues” and if gate D is selected in step 330, it is determined in step 335 that “selection of gate input signal line is unnecessary”. Proceeding to step 380, the signal value of the output signal line of the gate B and the signal value of the circuit input edge f are each set to 1, and in step 385, the set of unjustified gates is updated to {B}, and step 325 Return to

If it is determined in step 325 that "test pattern generation is to be continued" and if gate B is selected in step 330, it is determined in step 335 that "selection of gate input signal line is necessary". The process starts to select a gate input signal line.

In step 505, the selection probability of the input signal line is subtracted from the bias.

In step 510, the circuit input edge b having the smallest bias is selected. In step 515,
One is added to the bias of the circuit input edge b.

At step 380, circuit input edges a and b
And the signal value of the output signal line of the gate A is X,
In step 385, the unjustified gate set is updated to an empty set.

At step 325, it is determined that “test pattern generation is completed”, and at step 390, the test pattern (X,
(1, X, X, X, 1, X) are stored, and the process returns to step 318.

In steps 318 and 320, it is assumed that the stuck-at-0 fault of the output signal line of gate E has been selected as the target fault. Accordingly, the signal value of the output signal line of the gate E is set to D.

At step 322, the signal values of all signal lines are
X is set, and the unjustified gate set is calculated as {E}. In step 325, "continue test pattern generation"
If it is determined that the gate E is selected in step 330, it is determined in step 335 that "selection of a gate input signal line is unnecessary". Proceeding to step 380,
The signal value of the output signal line of the gate B and the signal value of the circuit input edge g are respectively set to 1, and in step 385, the unjustified gate set is updated to {B}, and step 325
Return to

If it is determined in step 325 that "test pattern generation is to be continued" and gate B is selected in step 330, it is determined in step 335 that "selection of gate input signal line is necessary" and the gate input signal shown in FIG. The process for selecting a line is started.

In step 505, the selection probability of the input signal line is subtracted from the bias. In step 510,
The circuit input edge a having the smallest bias is selected, and in step 515, 1 is added to the bias of the circuit input edge a. In step 380, the signal value of the circuit input edge a is set to 1, and in step 385, the unjustified gate set is updated to an empty set. At step 325, it is determined that “test pattern generation is completed”, and at step 390, the test pattern (1, X, X, X, X, X, 1) is stored. In step 318, the process is terminated because the target failure cannot be selected.

The test pattern thus created is
It is used to determine whether a fault exists in the circuit to be processed and, if so, what kind of fault it is. What is necessary is just to input a test pattern to a circuit to be processed and observe the output with a device called a tester.

<< Embodiment 2 >> FIG. 12 is a block diagram showing a configuration of an embodiment 2 of a logic circuit test pattern generation device according to the present invention. In the second embodiment, the bias initial setting unit 112 and the gate input signal line selection unit 140 are deleted from the configuration of the first embodiment in FIG.
0 is added. Gate input signal line selector 15
0 randomly selects the input signal line of the target gate according to the selection probability calculated by the selection probability calculation unit 116.

Hereinafter, the gate input signal lines to be selected are GI (1), GI (2),..., GI (n), and the selection probabilities are p (1), p (2), , P (n) will be described as a selection method. A uniform random number having a value of 0 or more and less than 1 is generated, and a gate input signal line GI (m) for the minimum m that satisfies Equation 1 is selected.

[0089]

(Equation 1)

However, if the signal value of the selected gate input signal line is X, the selection is invalidated and the selection is performed again. In the present invention, the calculation of the bias is unnecessary.

Note that in Examples 1 and 2,
The selection probability calculation parameter k does not necessarily need to be uniform for all gates. For example, for a gate closer to the circuit input edge (counting a distance of 1 as it passes through the gate), decrease k (closer to 0), and for a gate far from the circuit input edge, increase k. Is also good.

<< Embodiment 3 >> FIG. 13 is a block diagram showing a configuration of an embodiment 3 of a logic circuit test pattern generation device according to the present invention. The third embodiment is different from the configuration of FIG. 12 in that the selection probability calculation unit 116 and the gate input signal line selection unit 150 are deleted, and the gate input signal line selection unit 160 is added.

FIG. 14 shows a gate input signal line selection section 160
5 is a flowchart for explaining the processing procedure of FIG.

In step 602, the target value of the controllability scale is set to zero.

In step 603, a uniform random number taking a value of 0 or more and less than 1 is generated.

In step 604, it is determined whether or not the random value is greater than or equal to the discrete exponential distribution generation parameter t (0 <t <1). If the random number is greater than t, step 6
06, and if it is equal to or less than t, the process proceeds to step 608. In step 606, 1 is added to the target value, and step 603 is executed.
Return to In step 608, among the input signal lines of the target gate to which the signal value X is assigned, the controllability scale (0 for the AND gate and the NAND gate).
The controllability measure, one controllability measure in the case of an OR gate and a NOR gate), selects one of the closest to the target value. The processing up to step 606 is processing for generating a discrete exponential distribution.

FIG. 15 is a table showing the probability distribution of the target value of the controllability scale calculated when t = 0.3. The probability decreases as the target value increases.

The larger the discrete exponential distribution generation parameter t (closer to 1), the lower the probability that the target value of the controllability scale will take a large value, and the gate input signal line whose signal value is easiest to set. Approaching the process of assigning 0 or 1. Therefore, although the test pattern generation time is short, the generated test set is not very compact.

On the other hand, the smaller the value of t (closer to 0), the higher the probability that the target value of the controllability scale takes a large value, and approaches the process of sequentially changing the gate input signal lines to which 0 or 1 is assigned. Therefore, a compact test set is created, but the test pattern generation time increases.

As described above, the discrete exponential distribution generation parameter t is a parameter that governs the characteristics of the algorithm.

An example of test pattern generation according to the third embodiment will be described below.

FIG. 16 is a diagram showing an example of a logic circuit and its failure. It is also assumed that the test pattern generation target faults are only the stuck-at-0 faults of the output signal lines of the gates C, D, and E, and are selected in this order.

In step 312, the biases of all input signal lines of all gates are initialized to zero. At step 314,
As shown in FIG. 17, Goldstein's controllability scale is calculated.

In steps 318 and 320, it is assumed that a 1 stuck-at fault on the output signal line of gate D has been selected as a target fault. Accordingly, the signal value of the output signal line of the gate D is set to D '(0 for a circuit without a fault and 1 for a circuit with a fault).

At step 322, the signal values of all the signal lines are X
And the set of unjustified gates is calculated as {D}.

If it is determined in step 325 that "test pattern generation is to be continued" and gate D is selected in step 330, it is determined in step 335 that "selection of gate input signal line is unnecessary".

At step 380, the output signal line of the gate C and the signal value of the circuit input edge e are respectively set to 0. At step 385, the unjustified gate set is updated to {C}, and the process returns to step 325.

If it is determined in step 325 that "test pattern generation is to be continued" and gate C is selected in step 330, it is determined in step 335 that "selection of gate input signal line is necessary" and gate input signal line is selected. To enter the process.

FIG. 18 is a diagram showing a processing result of selecting an input signal line of the gate C according to the present invention. From left to right
It shows the target fault, the target value of the controllability measure, and the input signal line selected. Step 603 to step 60
Assuming that the process has passed through step 6 only once and then proceeds to step 608, the target value of the controllability scale becomes 1. Step 60
At 8, the circuit input edge b is selected as having the 0 controllability measure closest to the target value.

In step 380, the signal value of the circuit input edge b is set to 0, and in step 385, the invalidated gate set is updated to an empty set. At step 325, it is determined that "test pattern generation is completed", and at step 390, the test pattern (X, 0, X, X, 0, X, X) is stored.
Return to 18.

In steps 318 and 320, it is assumed that the 1 stuck-at fault of the output signal line of the gate E has been selected as the target fault. Accordingly, the signal value of the output signal line of the gate E is set to D '.

At step 322, the signal values of all the signal lines are X
And the unjustified gate set is calculated as {E}. If it is determined in step 325 that “continue test pattern generation” and gate E is selected in step 330, it is determined in step 335 that “selection of gate input signal line is unnecessary”. Proceeding to step 380, the output signal line of the gate C and the signal value of the circuit input edge f are each set to 0, and the unjustified gate set is updated to {C} in step 385, and the process returns to step 325.

If it is determined in step 325 that "test pattern generation is to be continued" and gate C is selected in step 330, it is determined in step 335 that "selection of gate input signal line is necessary" and gate input signal line is selected. To enter the process.

If the target value of the controllability scale becomes 2 as a result of passing twice from step 603 to step 606, the output signal line of the gate A is selected in step 608.

In step 380, the signal value of the output signal line of the gate A is set to 0. In step 385, the set of unjustified gates is updated to {A}, and the process returns to step 325.

If it is determined in step 325 that "test pattern generation is to be continued" and gate A is selected in step 330, it is determined in step 335 that "selection of gate input signal line is unnecessary".

At step 380, the signal value of the circuit input edge a is set to 1, and at step 385, the invalidated gate set is updated to an empty set.

In step 325, it is determined that “test pattern generation is completed”, and in step 390, the test pattern
(1, X, X, X, X, 0, X) is stored, and the process returns to step 318.

In steps 318 and 320, it is assumed that the 1 stuck-at fault of the output signal line of the gate F is selected as the target fault. Accordingly, the signal value of the output signal line of the gate F is set to D '.

At step 322, the signal values of all the signal lines are X
Is set, and the unjustified gate set is calculated as {F}. If it is determined in step 325 that “test pattern generation continues” and if gate F is selected in step 330, it is determined in step 335 that “selection of gate input signal line is unnecessary”.

In step 380, the output signal line of the gate C and the signal value of the circuit input edge g are each set to 0. In step 385, the set of unjustified gates is updated to {C}, and the process returns to step 325. .

If it is determined in step 325 that "test pattern generation is to be continued" and if gate C is selected in step 330, it is determined in step 335 that "selection of gate input signal line is necessary" and gate input signal The process for selecting a line is started. When the process reaches step 603 for the first time, the process proceeds to step 608. If the target value of the controllability scale becomes 0, the circuit input edge b is selected at step 608.

At step 380, the signal value of the circuit input edge b is set to 0, and at step 385, the invalidated gate set is updated to an empty set. At step 325, it is determined that “test pattern generation is completed”, and step 390 is performed.
Then, the test pattern (X, 0, X, X, X, X, 0) is stored. In step 318, since the target failure cannot be selected, the process ends.

In the present invention, the probability distribution of the target value of the controllability scale does not necessarily need to be uniform for all gates. For example, for a gate close to the circuit input edge (counting distance 1 each time the gate passes), the discrete exponential distribution generation parameter t is reduced (close to 0) and the target value of the controllability scale is reduced. The probability of taking a large value may be increased, and for gates far from the circuit input edge, t may be increased (closer to 1) to decrease the probability that the target value of the controllability measure will take a large value.

It is not always necessary to apply each of the above methods uniformly to all gates. For example, the first embodiment may be applied to a certain gate, and the embodiment may be applied to another gate. Also, the distance from the circuit input edge
For gates above a certain threshold (counted as distance 1 each time they pass through a gate), the controllability scale is good without diversifying the selection of gate input signal lines (the signal value setting is A (easy) gate input signal line may be selected.

In the above embodiment, the signal value system is 0, 1,
Although a five-value system composed of D, D ', and X is used, the invention described in this specification can be applied to other signal value systems.

Each means of the present invention may be realized as software, or may be realized using a dedicated hardware circuit.

[0128]

According to the present invention, a gate input signal line having a small controllability scale is selected more than a gate input signal line having a large controllability scale while maintaining the variety of selection of gate input signal lines. It is easy to be. As a result, a method and an apparatus for creating a test pattern of a logic circuit that can create a compact test set at high speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a hardware configuration of a test pattern generation device for a logic circuit according to the present invention.

FIG. 2 is a block diagram showing a functional configuration of an embodiment of a test pattern generation device for a logic circuit according to the present invention.

FIG. 3 is a diagram showing calculation rules of a controllability scale.

FIG. 4 is a table illustrating a system of signal values used in a D algorithm.

FIG. 5 is a flowchart illustrating a processing procedure of the test pattern generation device of FIG. 2;

FIG. 6 is a diagram illustrating signal values assigned by a signal value assignment unit.

FIG. 7 is a flowchart illustrating details of a processing procedure in which a selection probability calculation unit calculates a selection probability.

FIG. 8 is a flowchart illustrating details of a processing procedure in which a gate input signal line selection unit selects a gate input signal line.

FIG. 9 is a diagram illustrating an example of a failure in a logic circuit.

FIG. 10 is a diagram showing a controllability scale and a selection probability of each gate input line.

FIG. 11 is a diagram showing a transition of a process of selecting an input signal line of a gate B.

FIG. 12 is a block diagram illustrating a configuration of a test pattern generation device for a logic circuit according to a second embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a test pattern generation device for a logic circuit according to a third embodiment of the present invention.

FIG. 14 is a flowchart illustrating a processing procedure of a gate input signal line selection unit.

FIG. 15 is a chart showing a probability distribution of a target value of the controllability scale calculated when t = 0.3.

FIG. 16 is a diagram illustrating an example of a logic circuit and its failure.

FIG. 17 is a diagram illustrating an example of a calculation result of a Goldstein controllability scale.

FIG. 18 is a diagram showing a processing result of selecting an input signal line of a gate C.

[Explanation of symbols]

 Reference Signs List 102 input unit 106 output unit 110 test pattern generation unit 112 bias initial setting unit 114 controllability scale calculation unit 116 selection probability calculation unit 118 target fault selection unit 122 signal value / unjustified gate set initial setting unit 125 test pattern generation end Judgment unit 130 Gate selection unit 135 Gate input signal line selection necessity judgment unit 140 Gate input signal line selection unit 180 Signal value assignment unit 185 Unjustified gate set update unit 190 Test pattern storage unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazufumi Hikone 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi Ltd. 2G032 AA01 AG10 5B046 AA08 BA03 BA09 CA04

Claims (8)

[Claims] In a method for generating a test pattern of a logic circuit including a justification process, a selection probability of a gate input signal line is calculated, and when it is necessary to select a gate input signal line during the process, A method for creating a test pattern for a logic circuit, comprising selecting a gate input signal line based on a selection probability. 2. An apparatus for generating a test pattern for a logic circuit including a justification process, wherein a selection probability calculation unit for calculating a selection probability of a gate input signal line and a gate input signal line need to be selected during processing. A gate input signal line selection unit for selecting a gate input signal line by a procedure using the selection probability. 3. An apparatus for generating a test pattern of a logic circuit including a justification process, comprising: a selection probability calculation unit for calculating a selection probability of a gate input signal line; and a gate input signal line selection unit for selecting a gate input signal line. The gate input signal line selection unit selects the best gate input signal line evaluated by the evaluation value of the gate input signal line, and when the gate input signal line is selected, the evaluation value is determined by the gate input line. In a case where the evaluation value is changed in a direction in which the gate input line is easily selected while the evaluation value is changed in a direction in which the gate input line is easily selected, the evaluation value is changed only by a value corresponding to the selection probability. Test pattern creation device. 4. An apparatus for generating a test pattern for a logic circuit including a justification process, comprising: a selection probability calculation unit for calculating a selection probability of a gate input signal line; and a gate input signal line selection unit for selecting a gate input signal line. In the case where the gate input signal line selection unit assigns a predetermined signal value to a part of the gate input signal line by the justification processing, the gate input signal line is evaluated best by the evaluation value of the gate input signal line. A test pattern creation device for a logic circuit, comprising: means for selecting a signal line and changing the evaluation value so that only a value corresponding to the selection probability is easily selected. 5. A test pattern creation apparatus for a logic circuit including a justification process, comprising: a selection probability calculation unit for calculating a selection probability of a gate input signal line; and a gate input signal line selection unit for selecting a gate input signal line. In the case where the gate input signal line selection unit assigns a predetermined signal value to a part of the gate input signal line by the justification processing, the gate input signal line is evaluated best by the evaluation value of the gate input signal line. A signal line is selected, and the evaluation value is used as an index comparing the appropriate number of times that the gate input signal line is selected with the number of times that the gate input signal line is actually selected. An apparatus for generating a test pattern for a logic circuit, wherein the number of times is calculated based on the selection probability. 6. An apparatus for generating a test pattern for a logic circuit including a justification process, comprising: a selection probability calculation unit for calculating a selection probability of a gate input signal line; and a gate input signal line selection unit for selecting a gate input signal line. When the gate input signal line selection unit allocates a predetermined signal value to a part of the gate input signal line by the justification process, the gate input signal line selection unit randomly selects the gate input signal line based on the selection probability. An apparatus for creating a test pattern for a logic circuit. 7. The test pattern creation device for a logic circuit according to claim 3, further comprising a controllability scale calculation unit that calculates a controllability scale of a gate input signal line, wherein the selection is performed. A test pattern creation device for a logic circuit, wherein the probability calculation unit is means for calculating a selection probability based on the controllability measure. 8. An apparatus for creating a test pattern of a logic circuit including a justification process, comprising: a controllability scale calculation unit for calculating a controllability scale of a gate input signal line; and a gate input signal line for selecting a gate input signal line. A selection unit, wherein the gate input signal line selection unit assigns a predetermined signal value to a part of the gate input signal line by the justification process, and the controllability scale calculated by a random algorithm. And a means for selecting a gate input signal line based on the target value of (1) and the controllability scale calculated by the controllability scale calculation unit.