JP2000004359A - Distributed pwn gradation processor and printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly realize gradation processing of high density and high gradation by realizing dot dither, which forms plural dots in one threshold pattern and multi-leveling due to PWM(laser pulse width modulation) which distributes gradation among plural dots. SOLUTION: A difference value Δn=ni-nc between an input gradation value ni and a threshold nc is reduced into the range of 0 to Δh, and low-order (s) bit of Δh is eliminated through round-off or round-up processing. On the other hand, a threshold array is produced from an expansion threshold pattern, which is obtained by combining threshold patterns Δh×K, Δh×K+1,..., Δh×K+2'(s-1), whose threshold interval is a power (2's) number of 2 of Δh.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image output apparatus for printing an image as a set of dots (pixels), such as a printer and a facsimile. In particular, laser pulse width modulation (Pull
This is an invention for an apparatus that performs image processing for expressing continuous gradation by combining a plurality of pixels with se Width Modulation (PWM).

[0002]

2. Description of the Related Art Conventionally, raster devices of one pixel and two gradations (binary) used in digital printers and the like are provided with intermediate gradation expression means known as a dither method or an error diffusion method.
A method of artificially supplementing the intermediate gradation has been used in many cases.

In the dither method, in particular, a gradation processing method called a dot concentration type dither method using a threshold pattern as shown in FIG. 3b of JP-A-61-125264 has been often used. In this method, a plurality of dot arrays are used to simulate a halftone dot whose diameter changes according to an input gradation. This method has an advantage that noise mixed in a reproduced image by gradation processing is not noticeable. Further, as shown in FIG. 17a of Japanese Patent Application Laid-Open No. 61-125264, this method simulates a plurality of halftone dots which are composed of one threshold pattern with a plurality of clusters and sequentially expanded in each cluster. By using a method, that is, a so-called sub-matrix method, it is possible to achieve both the density of halftone dots and the number of gradations to some extent.

[0004] A similar gradation process can be seen in Fig. 21 (B) of Japanese Patent Publication No. 6-85558. In particular, Japanese Patent Publication No. 6-85558 further binarizes the output of one pixel by pulse width modulation of an output laser called PWM. In this processing method, a ternary output level is determined by using together another set of threshold values shown in FIG. 21 (A) corresponding to FIG. 21 (B).

[0005]

These schemes are designed to achieve both the number of gradations and the resolution.
er inch) laser printers do not always have sufficient characteristics. To reproduce an image about gravure printing,
A halftone density of 175 lpi and 256 gradations are required. Here, the unit lpi is a dot density per inch (lines per inch) called “line number”. lpi
Is distinguished from the resolution dpi of the printer engine itself.

With a printer of about 600 dpi binary, it is impossible to form a halftone dot of such a gradation density. However, the number of gray levels that can be visually perceived depends on the spatial frequency, and a high number of gray levels is not required for high-frequency components.

[0007] Roetling's "Visual performance and ima
ge coding (SPIE / OSA (1976)) ", the spatial frequency f (cy
The discriminable gradation number Gn with respect to cles / degree) is modeled by Gn = 1010 (exp (−0.138f)) (1−exp (−0.1f)) + 1 (1)

FIG. 21 is a diagram showing the visual characteristics of the number of distinguishable tones corresponding to the resolution of the printer based on this equation. The solid line is the number of identifiable gradations for the spatial frequency according to the equation (1). The broken line indicates the number of gradations that can be performed by an n-value 600 dpi printer. However, in FIG. 21, the spatial frequency is converted into the halftone frequency at the observation distance of 30 cm and at the observation distance of 40 cm and displayed. At an observation distance of 30 cm, 1 (cycle / degree)
Corresponds to about 10 (lpi).

In FIG. 21, the portion where the broken line exceeds the solid line indicates that sufficient gradation can be obtained for the spatial frequency. Therefore, according to this figure, with a 600 dpi printer,
It can be seen that in order to obtain a sufficiently smooth gradation, at least one dot needs to be converted to quinary or quinary.

On the other hand, in order to form a halftone dot of 175 lpi or more with a 600 dpi printer, one halftone dot needs to be constituted by a set of 3 × 3 or less dots. The number of gradations in this case is 9
Even with a printer having a value, 3 × 3 × 9 + 1 = 82 gradations, and the number of gradations in the low frequency range is insufficient. Therefore, it is impossible to obtain sufficient gradation by only the clustering method (sub-matrix method). Also, increasing the number of PWM divisions so as to obtain the gradation by using only the PWM requires a higher-frequency control circuit for the same printing speed, which is an obstacle to speeding up or mounting cost. .

For this reason, it is necessary to use both the clustering method as disclosed in the above-mentioned JP-A-61-125264 and the PWM.

In the case where a ninth value is formed by a method of providing a threshold array corresponding to each of the density levels of 1/3 and 2/3 of the dot density as disclosed in Japanese Patent Publication No. 6-85558, This causes a problem that the array and the comparison circuit become large.

[0013] The increase in the circuit configuration scale and the required memory by such a method not only leads to an increase in cost but also to an increase in the development burden in the case where processing is made into a dedicated LSI (ASIC).

An object of the present invention is to provide a gradation processing circuit which can achieve both halftone dot clustering and PWM which can be easily realized in an ASIC with a small amount of memory and a simple processing circuit. The purpose of the present invention is to realize a simple gradation process.

[0015]

In order to solve the above problem, based on an input gradation value and a value of a lower bit of a threshold value,
Dispersion P that increases the PWM level dispersively among multiple dots
A gradation processing device is constituted by the WM circuit.

[0016]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a gradation processing apparatus according to the present invention.
6 shows the flow of image processing in a 600 dpi color laser printer. Image data 1 to be printed is stored in the input buffer 2 as RGB data for one page. Since the printer engine 13 performs development for each surface (each color) of the YMCK, the processing after the input buffer 2 in FIG. 1 is repeated four times for four YMCK surfaces for one color image.

First, the four-color separating means 5 initializes the inside as necessary so as to calculate Yellow from RGB dot sequential data. In response to this, the γ correction means 7 loads a correction value corresponding to Yellow from the γ correction value table 8 into an internal reference table. Further, the dither circuit 10 loads a threshold array corresponding to Yellow and size data of the array from the table 11 and initializes the inside. This threshold array is shown in FIG.
Is an array of values expressed by 8 bits from 0 to 255 or less, as in the threshold array 27 of FIG.

Thus, RG sent from the input buffer 2
The B data is subjected to color correction by the color correction means 3, conversion to Yellow data by the four-color separation means 5, and gradation correction by the γ correction means 7, and then the printer engine 13 as a PWM signal 12 by the gradation processing device 9. Output to

When processing for one Yellow page is completed, 4
The color separation unit 5, the γ correction unit 7, and the dither circuit 10 reload necessary parameters for Magenta and initialize them, and send a PWM signal 12 for one page of Magenta to the printer engine 13 by the same processing.

Similarly, processing for Cyan and Black is performed.
Switching between these color planes is performed in synchronization with the vertical synchronization signal of the printer engine. At this time, the threshold value array may be set so as to be changeable for each color plane.

Next, an example of the gradation processing device 9 will be described with reference to FIGS.
Shown in In these examples, the input gradation value (input pixel gradation value) to the gradation processing device 9 is 256 gradations (8 bits), and the number of divisions of 1 dot by PWM is 16 (4 bits) in 17 steps (0 to 0). 16). In this embodiment, the input gradation value is realized by 8 bits, but it is needless to say that the input gradation value may be input by another number of bits.

[0023] In the process of the first half, including NAND circuit 17 of FIG. 2, at first, the subtraction circuit 14, a grayscale range a dither threshold input signal n _i
obtaining the difference Δn = n _i -n _c of the n _c. If Δn <0,
By the underflow signal of the subtraction circuit 14, N
The output from the AND circuit 17 is all bits 0. If 0 ≦ Δn, the comparison circuit 15 compares this Δn with a threshold interval Δh that is set in advance in the register 19 and is the upper limit of the difference value. When Δn ≧ Δh, the output of the comparison circuit 15 is
It is set to 1 and all 6 bits are set to 1 (= full) by the OR circuit 16 and output via the NAND circuit 17 regardless of the input gradation value. And
In other cases (when 0 ≦ Δn <Δh), the 6-bit input gradation value to the OR circuit 16 is output from the NAND circuit 17 as it is, and 8 bits
Is reduced to a value of 6 bits 0 to Δh (and all bits = 1).

In the subsequent stage of the NAND circuit 17, the selection circuit 24 outputs 4 bits from the 6-bit signal line output from the NAND circuit 17,
The value s previously determined in the register 20 by Δh
= 0 to 3 are selected as follows.

If s = 0, cut off the upper 2 bits and select the lower 4 bits. If s = 1, upper 1 bit and lower 1 bi
Truncate and select middle 4 bits. If s = 2, lower 2
Truncate the bits and select the upper 4 bits. When s = 3, the lower 3 bits are discarded and the upper 4 bits are added with 1 bit 0 signal.
choose.

This operation is equivalent to shifting the 6-bit output value of the NAND circuit 17 to the right by s bits and discarding overflow bits. Therefore, hereinafter, s is referred to as a bit shift amount. This processing is equivalent to dividing the output value of the NAND circuit 17 by the power of 2 to the s power and cutting off the remainder to obtain the number of bits corresponding to the number of divisions of the PWM. In this sense, FIG. 2 is a “round-down circuit”.

The bit shift amount s according to Δh is specifically determined as follows. When 1 ≦ Δh <16 (= 2 ⁴ ),
s is selected in the range of 0 to 3; when 16 ≦ Δh <32 (= 2 ⁵ ), it is selected in the range of s = 1 to 3; when 32 ≦ Δh <64 (= 2 ⁶ ), s = 2 or 3.

The PWM level correction circuit 21 further converts the PWM gradation value according to a value preset in a PWM conversion table 22 as a reference table, using the signal reduced to 4 bits in these processes as an index. PWM generation circuit 23 that performs multi-level gradation control of the final actual output level value by PWM
Output to FIG. 4 shows that the PWM division number is 16 and the input gradation value is 0.
PWM conversion table 22 for 8 stages of .about.6 and f
Here is an example.

In FIG. 4, the correction is performed so that the relative density 60 relative to the relative value of the laser pulse division time for one dot by PWM is substantially linear. For the reason described later, the input grayscale value 6 and the input grayscale value f (all bits = 1) correspond to the same maximum level value.

In the above description, of the difference Δn, the upper 2 bits of the 8 bits excluding the underflow signal are truncated before being input to the OR circuit 16. However, the truncated position on the circuit of the upper 2 bits is particularly It does not matter. In the embodiment of FIG. 2, Δh is set to a value smaller than 64 (6 bits), and the NAND circuit 17
Output is 6 bits, but of course the 6 bit limit is not essential. For example, if the output of the NAND circuit 17 is 8
The processing is performed with the bits unchanged, and the selection circuit 24 cuts off the upper 4 bits (s = 0), the upper 3 bits and the lower 1 bit (s =
1) It is easy to implement as a circuit for selecting any of upper 2 bits and lower 2 bits truncated (s = 2), upper 1 bit and lower 3 bits truncated (s = 3), and lower 4 bits truncated (s = 4). . In this case, the bit shift amount s is 0 to 4
Therefore, the signal line which is the selection signal from the register 20 requires 3 bits.

The embodiment shown in FIG. 3 is different from the truncation process of FIG. 2 only in that a round-up process is performed. In FIG. 3, adders 18a, 18b and 18
c, the lower bits to be truncated when s = 1 to 3
The OR value is added to the remaining upper 4 bits output to the PWM level correction circuit 21. As a result, FIG.
The output value of the NAND circuit 17 is set to 2 according to the value of the bit shift amount s.
, And operates as a “round-up circuit” where the remainder is rounded up.

FIG. 5 is a flowchart showing the above processing. The processing is performed on a page basis for each color plane. First, in an initialization step 100 prior to page processing, a threshold interval Δh
From the register 19 and the bit shift amount s from the register 20. The bit shift amount s is a value sufficient to reduce Δh to 4 bits, which is the number of divisions by PWM,
Although it is a value determined in advance corresponding to Δh, it can be automatically determined from Δh according to the example of the initialization step 100 in FIG. In the initialization step 100, a PWM conversion table 2 for converting the PWM output value p into the actual output level value p '
Load 2 as well.

In step 101, the input pixel value _ni and the threshold value n _c
Is loaded, and the difference Δn is calculated in step 102. Threshold n _c in step 101, the dither circuit 10 of FIG. 1, the threshold array 27 or as shown in FIG. 8 to be described later, sequentially in synchronism with the input pixel value n _i on the basis of the simplified threshold array 28 Is entered.

In step 103, Δn and Δh are compared. Then, if the PWM output value p is Δn <0, p = 0, Δ
If n ≧ Δh, p = f (hexadecimal), if 0 ≦ Δn <Δh, p =
(Δn / 2 ^ s). (2 ^ s represents 2 to the power of s) where Δn
Is divided by 2 ^ s, and the remainder is rounded down by the round down circuit of FIG. 2 and rounded up by the round up circuit of FIG.

In step 104, using the PWM output value p as an index, the PWM level correction circuit 21 uses a PWM conversion table.
According to 22, a final PWM output level value p 'is obtained.

Finally, at step 105, the PWM output level p '
Output to the printer engine 13 as a PWM signal subjected to pulse width modulation by the PWM generation circuit 23.

The above processing is repeated between step 101 and the processing of pixels for one page until the processing of the next page or the next color plane is repeated from the beginning until the processing of step 101 is completed.

FIG. 6 shows an example of input / output correspondence by the round-up circuit of FIG. In FIG. 6, the PWM output value p from the selection circuit 24 in the case of Δh = 24 and s = 2 is represented by the input gradation value n _i = 0 to 25
With 5 as a row, 4 × 10 sets of threshold values n _c = {24k, 24k + 1, 24k
+2, 24k + 3} (k = 0, 1, 2,..., 9) as a hexadecimal table. An example of the arrangement of such a set of thresholds is shown in the threshold array 27 of FIG.

In FIG. 6, the output values are 1, 2, 2, except for 0.
3, 4, 5, 6, and 6 (f (full)). These values are, as shown in FIG. 4, the PWM level correction circuit 2 shown in FIG.
According to 1, the PWM output level is corrected according to the PWM conversion table 22 so as to obtain uniform gradation. In particular, 6 and f (hexadecimal) of the output value of the selection circuit 24 correspond to the PWM level correction circuit 2
1 corresponds to the same actual output level value. In this case, the number of PWM stages (the number of stages of the PWM output level excluding 0 and f) is six. As a result, the number of logical output gradations based on the combination of the 40 threshold values in FIG. 6 is 241 (6 × 40 + 1) gradations.

FIG. 7 shows an example of input and output by the truncation circuit (FIG. 2) for the same set of Δh = 24, s = 2 and threshold. In this case, the outputs corresponding to the input gradation values 0 to 4 are all 0. Usually, however, the “jump” of such a highlight portion
Does not significantly affect the output image.

[0041] If necessary by adding a circuit for adding a constant offset value n ₀ = 3 to n _i input unit of FIG. 2, is readily realized that the round-up circuit equivalent output corresponding (Figure 5) it can. Alternatively, by providing the output of the γ correction means 7 at the preceding stage with an offset of n ₀ = 3 from the beginning, equivalent input / output correspondence can be realized more easily.

Conversely, Δn = n _i by the round-up circuit of FIG.
Relationship -n _c and PWM output value p, by adding an offset of n ₀ = 1 the input gradation value _{n i, Δn + n 0 =} n i + n 0 -n
_The processing is substantially equivalent to a round-down circuit that does not depend on the lower s = 2 bits of _c .

As described above, in the embodiment shown in FIGS.
The output value p is a value Δn + obtained by appropriately offsetting the difference value Δn.
It is determined independently of the lower sbit of n ₀ . That is, the truncation processing of the lower bits for the difference value between the input gradation value and the threshold value is the essence of the processing implemented in FIGS.

FIG. 8 shows a method of constructing a threshold array for realizing the distributed processing of the PWM in combination with the gradation processing device 9 shown in FIGS. As in the previous example, Δh = 24,
Let s = 2.

First, let K be the basic threshold pattern 25, and form an extended threshold pattern 26 consisting of four threshold patterns generated from K as K × Δh, K × Δh + 1, K × Δh + 2, and K × Δh + 3.

Next, the threshold array 27 shown in FIG. 8 is obtained by filling this extended threshold pattern 26 into a rectangular area that is periodically closed in both rows and columns. Although the dither circuit 10 generates a threshold value n _c by repeatedly using the threshold array 27 periodically, the threshold array 27 showed over two lines in the figure by arrow A position (sixth column)
And shifts to the left, stacking 10 steps downward. Therefore, instead of the entire threshold array 27, a simplified threshold array 28 consisting of the upper two rows is replaced with an initial column address of 6 for each two rows of the input image in synchronization with the horizontal synchronization signal of the printer engine 13.
Iterative use while shifting column by column can further save memory on implementation.

FIG. 9 shows a threshold array 27 having such a configuration.
3 shows the effect of the distributed processing of PWM obtained by the gradation processing device 9 of FIG. For the extended threshold pattern 26, simply combine PWM and clustering as in the conventional example.
When the dispersion processing is not performed, the image output for n _i = 7 becomes a rough halftone image with a lot of noise, with the irregularities of the dots and the irregularities of the dot diameters emphasized as shown in FIG. 9B. On the other hand, when the PWM distributed processing is performed by the gradation processing device 9, a uniform and smooth network in which the intermediate gradation by PWM cyclically increases in four regions as shown in FIG. It becomes a point image.

The threshold array 27 in the above description outputs a halftone dot grid which forms an angle of about 18.4 degrees with respect to the horizontal direction with respect to a uniform halftone value, as indicated by a circle in FIG. . The angle formed by the halftone grid with respect to the horizontal direction is called the screen angle. In normal color printing, different screen angles are used for each color plane in order to stabilize reproduced colors.

FIG. 10 is a table showing examples of basic threshold patterns K, threshold intervals Δh, and bit shift amounts s corresponding to various screen angles θ. The values in the table have a relationship of Δh = 2 ^ s × (number of PWM stages) (total number of gradations) = (number of cells) × Δh + 1.

As described above, the bit shift amount s has a degree of freedom in setting. Generally, the gradation characteristics by PWM differ depending on the printer engine. Therefore, for a printer engine with sufficient gradation characteristics by PWM, a smaller value of s can obtain a uniform and high-density image. However, when the gradation characteristic by PWM is not sufficient and the number of gradations actually corresponding to the number of pulse divisions as a signal is small, a larger value of s provides higher gradation. .

In the case of color printing, Cyan is shown in FIG.
When the threshold patterns of FIG. 10A are assigned to FIG. 10A, Yellow are assigned to the threshold patterns of FIG. 10B, and Black are assigned the threshold patterns of FIG. Magenta and Cya
The pattern assigned to n may be reversed.

The configuration method of the extended threshold pattern and the threshold array using these basic threshold patterns K is almost the same as the configuration method of the above-described threshold array 27 shown in FIG. In particular, in the case where the bit shift amount s is different, FIG.
Figure 1 shows an extended threshold pattern and a simplified threshold array corresponding to
FIG. 12 shows an extended threshold pattern and a simplified threshold array corresponding to s = 3 in FIG. In these figures, the thresholds on the extended threshold pattern corresponding to the threshold value 0 of the basic threshold pattern are indicated by circles in order to make the arrangement characteristics easy to see. As in the case of FIG. 8, in order to obtain a threshold array from the simplified threshold arrays 42 and 45 in these figures, the simplified threshold array is repeated while shifting the column at the position indicated by the arrow A in the figure. good.

FIG. 13 is substantially the same as the round-up circuit of FIG.
This is another implementation example of the gradation processing device 9 that can obtain the PWM dispersion effect. In this embodiment, since data is divided into several bits for processing, the above "round-up circuit" and "round-down circuit" are called "bit division circuits". FIG. 14 shows the concept of the flow of processing by the bit division circuit.

In this embodiment, the number of PWM gradations of 1 dot is set to 0 to 4
(The number of PWM divisions is 4), and the PWM is distributed between the four dots as follows.

[0055] Further, although the data related to the normal image is handled in 8bit units, for simplicity, the upper 2bit threshold n _c
Is ignored from the beginning and treated as 6 bits. Of course, a configuration in which 2 bits at other positions such as lower 2 bits are ignored is also possible. When the lower 2 bits are ignored, the threshold value described below may be read by shifting the threshold value by 2 bits, that is, quadrupling the threshold value.

[0056] First, gamma gradation value n _i of the input pixel of the corrected 8bit correction unit 7, the upper bit block index 4bit in order from b _i, followed 2bit the PWM level value N _p, rotate the remaining lower 2bit The wiring of the input pixel is divided so as to have the index k _i . Further, the threshold value n _c of 6bit is loaded from the dither circuit 10 threshold, from the higher bit 4
Divide the threshold wiring so that the bit is the block index b _c and the lower 2 bits are the rotation index k _c
(FIG. 14, step 111).

The comparison circuit 50 _{calculates the} block indices b _i and b _c
Comparison of the size, the PWM level value N _p, is corrected in the following rules. If b _i > b _c (step 112), N _p is forcibly applied.
= 4 (step 113). If b _i <b _c (step 114)
Is forced to be N _p = 0 (step 115). If b _i = b _c, the rotation index k _i is compared with k _c by the comparison circuit 51 (step 116), and 1 is added to the PWM level value N _p only when k _i > k _c (step 116). Step 117). Otherwise, no modification of N _p is made.

At this time, in order to switch the processing when b _i = b _c , in the example of FIG. 13, the output is switched by the comparison circuit 50. The comparison circuit 50 outputs the truth value of b _i = b _{c and} the truth value of b _i > b _c in positive logic. Selecting means 53, as a selection signal boolean of b _i = b _c, in the case of b _i = b _c is the adding circuit 5
2 is selected, and if b _i ≠ b _c, a value obtained by shifting the boolean value of b _i > b _c by 2 bits (ie, quadrupling) is selected. Finally PWM
Level correction circuit 21 converts the PWM output value N _p to PWM level value p '(step 118).

FIG. 15 is a table showing the PWM output values according to this embodiment. Figure 15 shows a diagram with 40 different thresholds.
A set of thresholds such as 16 threshold patterns 56 is assumed.

The above description is an implementation example corresponding to a PWM division number of 4. However, a circuit corresponding to a PWM division number of 8 can be configured with substantially the same circuit. In this case, the way of bit division of the corresponding bit division circuit (FIG. 13) is changed as shown in parentheses in FIG. That is, the gradation value n _i of the input pixels, PWM block index 4bit in order from the upper bit b _i, a subsequent 3bit
The wiring of the input pixel is divided so that the level value N _p and the remaining lower 1 bit become the rotation index k _i . Also,
Threshold n _c from dither circuit 10 is loaded threshold 5bi
t, and 4 bits from the upper bits are block indices b _c ,
Lower 1bit to divide the wiring threshold so rotation index k _c.

FIG. 16 shows a method of forming a threshold pattern suitable for the bit division circuit of FIG. The configuration method of the extended threshold pattern 56 corresponding to the PWM division number 4 (2 bits) is the same as that of FIG. 8, the basic threshold pattern 55 is K, the threshold interval Δh = 4, and K is K × Δh, K × Δh + 1. , K × Δh + 2, K ×
It is composed of four threshold patterns generated by Δh + 3. The configuration method of the extended threshold pattern 57 corresponding to the PWM division number 8 (3 bits) is the same as that in FIG. A threshold array and a simplified threshold array can be obtained from the extended threshold pattern as in the case of FIG.

In the case of the threshold pattern 56, the total number of gradations = (the number of cells) × (the number of divided PWM) + 1 = 40 × 4 + 1 = 161, and the range of input gradation values that can be supported is n _i = 0 to 160 Up to 161 gradations. Therefore, as can be seen from FIG. 15, the PWM output values for input tone values exceeding 160 all have the maximum value of 4. However, as shown in FIG. The correction is easily performed by suppressing the correction value to a value not _{exceeding the} total number of gradations _nmax .

FIG. 17 shows a graph suitable for various basic threshold patterns.
An example of the PWM division number and Δh is shown. In the case of bit classification circuit,
Unlike the case of the round-up circuit and the round-down circuit, the relationship with the total number of gradations is as follows: (total number of gradations) = (number of cells) × Δh × (number of divided PWM) +1.

The number of PWM divisions 4 in the gradation processing apparatus of FIG.
The difference between the case when the a PWM division number 8, the number of bit division gradation value n _i and the threshold n _c of the input pixel (bit width) are different only. Therefore, as shown in FIG. 19, dividing circuits 58 and 59 are provided before the comparing circuits 50 and 51, respectively, and the number of PWM divisions can be switched by changing the bit width of the bit division by the selection signal 56. I can do it.

In the example shown in FIG. 19, each of the signal lines P1 to P5
P1 = P4 = 4bit, P2 = 3bit, P3 = P5 = 2bit b
has it width. The selection signal 56 is a signal for setting in advance a register (not shown) for each color plane and determining the number of divisions of P1, P2, and P3. In this embodiment, the selection signal is set to two types (1 bit) of 0 and 1, and the PWM division number is set to 8 or 4.

[0066] When the selection signal 56 is 0, divider 59 the upper 3bit lower 4bit gradation value n _i of the input pixel P2, lower 1bit of dividing the lower 1bit the upper 1bit of P3 (P3 is 0). Further, division circuit 58 uppermost 3bit threshold n _c of 8bit
Divide the middle 4 bits into P4 and the lower 1 bits into P5
(The lower 1 bit of P5 is 0). By dividing in this way, a circuit equivalent to the case of the PWM division number 8 in FIG. 13 is obtained.

When the selection signal 56 is 1, the dividing circuit
59 the upper 2bit lower 4bit gradation value n _i of the input pixel to the upper 2bit of P2 (lower 1bit of P2 is 0), and outputs to the comparison circuit 51 divides the lower 2bit to P3. Dividing circuit 58, a middle 4bit to P4 threshold n _c of 8bit ignoring uppermost 3bit, lower 2
The bit is divided into P5 and output to the comparison circuit 15. When the value input to the selection signal 56 is 1, a comparison circuit is used in the addition circuit 52.
The output from 51 is doubled (= 1 bit shifted) and added to P2. By doing so, the PWM division number 4 in FIG.
It becomes a circuit equivalent to the case of.

FIG. 20 is a configuration diagram of a color laser printer 30 including a controller board 31 on which the gradation processing device 9 of any of the above embodiments is mounted. Controller board
31 is indicated by a broken line because it is mounted vertically on the bottom of the printer in parallel with the mechanism. The gradation processing apparatus of the present invention develops an input image signal in real time in synchronization with a horizontal synchronization signal and a vertical synchronization signal for controlling the photosensitive belt 32 and the laser optical device 33, and electrostatically charges the photosensitive belt on the photosensitive belt. Form a latent image.

In the above embodiment, color printing is described as an example.
Needless to say, it can be applied to (monochrome) printing. Further, in this embodiment, 4 bits are input to the PWM level correction circuit 21 in order to set the number of divisions of PWM to 16, but
If the number of divisions of the PWM is set to another value, the number of sbit bits to be cut off changes according to the value.

[0070]

According to the present invention, the distributed processing of the PWM compatible with the clustered halftone dither with the screen angle is realized by a small-scale circuit configuration. This allows
It is easy to implement high-resolution, high-gradation and stable gradation processing on an ASIC.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of data processing including the present invention.

FIG. 2 is a diagram illustrating an example of a gradation processing device (a round-off circuit) according to the present invention.

FIG. 3 is a diagram showing an example of a gradation processing device (round-up circuit) of the present invention.

FIG. 4 is an explanatory diagram of PWM level correction.

FIG. 5 is a diagram illustrating an operation flow of the gradation processing device.

FIG. 6 is a diagram illustrating an example of input / output correspondence by a round-up circuit.

FIG. 7 is a diagram showing an example of input / output correspondence by a truncation circuit.

FIG. 8 is a diagram illustrating a configuration method of a threshold array from a basic threshold pattern.

FIG. 9 is a diagram showing an explanatory diagram of the effect of the present invention.

FIG. 10 is a diagram showing an example of a basic threshold pattern for realizing other screen angles.

FIG. 11 is a configuration example of a simplified threshold array from other basic threshold patterns.

FIG. 12 is a configuration example of a simplified threshold array from other basic threshold patterns.

FIG. 13 is a diagram showing an example of a gradation processing device (bit division circuit) of the present invention.

FIG. 14 is a diagram showing an operation flow by a bit division circuit.

FIG. 15 is a diagram showing an example of input / output correspondence by a bit division circuit.

FIG. 16 is a diagram illustrating a configuration example of an extended threshold array corresponding to a bit division circuit;

FIG. 17 is a diagram of the total number of gradations for each basic threshold pattern in the bit division circuit.

FIG. 18 is a diagram illustrating an example of γ correction in which the total number of gradations is set as an upper limit.

FIG. 19 is a diagram illustrating an example of a bit division circuit that makes a bit division variable.

FIG. 20 is a diagram showing an example of a color laser printer equipped with the gradation processing device of the present invention.

FIG. 21 is a diagram showing gradation discrimination characteristics of human eyes.

[Explanation of symbols]

1 ... supply means, 2 ... paper sheets, 4 ... separation means, 7 ... transport means,
8 reverse section, 9 first reading section, 90 second reading section, 11 first stacking means, 12 bottom plate, S1 to S12 sectioned area, 13 first sorting means, 14 Display means, 15 destination code, 16 second accumulation means, 17 second distribution means, 18 thickness detection means, 60 first distribution control section, 61
... second distribution control unit, 62 ... first storage unit, 63 ... preparation means, 64 ... second storage unit, 65 ... third storage unit, 66 ... control means, 67 ... separation means control means, 68 ... supply means control means,
69 ... display control means, 70 ... bottom plate control section, 71 ... sorting information input means, 72 ... display means.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayuki Kanda 456 Nakai-cho, Nakai-cho, Ashigara-gun, Kanagawa Prefecture Within Hitachi Information Technology Co., Ltd. (72) Inventor Toshiaki Nakamura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Atsushi Onose 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Eiji Yoshino 1-1-1, Higashitaga-cho, Hitachi City, Ibaraki Pref. BB19 BB44 BC01 BC17 2C362 CA03 CA09 5C077 LL17 LL18 MP08 NN04 NN08 NN17 PP15 PP20 PP33 PP 38 PP47 PQ08 PQ12 PQ20 PQ22 PQ23 RR10 RR11 RR13 TT03

Claims (11)

[Claims] And 1. A PWM generating circuit to perform gradation control by the laser pulse width modulation (PWM), and a threshold value table for storing the threshold value n _c, the input gradation value n _i of tbit (t ≧ 8) The in the gradation processing unit for converting the PWM gradation value by the difference value [Delta] n = n _i -n _c of the input tone value n _i and the threshold value n _c, matches the threshold interval Δh of the upper limit value of the difference value A register, and when 0 ≦ Δn ≦ Δh, the lower order s of the difference value Δn
A gradation processing device in which a value obtained by rounding down (0 <s <4) bits or a value obtained by rounding up lower s bits to the remaining higher (ts) bits is used as a PWM gradation value. 2. The gradation processing device according to claim 1, further comprising a lookup table for further converting said PWM gradation value. 3. A threshold array is provided, and 8 bits per pixel (= 256 steps)
The gradation value n _i of the input pixels, by sequential comparison with the threshold value n _c of the threshold matrix, the gradation processing unit for converting the output tone values representable with fewer bit width, the output tone value Are appropriate constants n ₀ and s = 1, 2, 3, 4
A gradation processing device which is determined independently of the lower sbit of (n _i -n _c + n ₀ ) for any of the values of Comprising a 4. A threshold array, the gradation value n _i of the input pixels of one pixel 8bit (= 256 steps), by successive comparison with the threshold value n _c of the threshold array, the output minimum pixel, multi A printer which performs stepwise output tone value control, wherein the output tone value is set to an appropriate constant n ₀ and s = 1, 2, 3, 4
Is determined independently of the lower sbit of (n _i -n _c + n ₀ ). 5. An output image corresponding to an increase in input gradation is 2 s.
5. The printer according to claim 4, wherein the printer is a halftone grid that increases the gradation cyclically between the halftone dots. 6. The printer according to claim 4, wherein multicolor printing of at least two or more colors is performed for each color plane, wherein the threshold value array and the value of s can be changed for each color plane. 7. A PWM generation circuit that performs multi-level gradation control by laser pulse width modulation (PWM), comparison means for comparing a gradation value of an input pixel with a threshold, and a threshold table for storing the threshold. A gradation processing device for converting the gradation value of the input pixel into a PWM gradation value of an output pixel by the comparing means, wherein the PWM circuit includes a specific bit of the gradation value of the input pixel and A gradation processing device that adds dither to a PWM gradation value based on a comparison result of a threshold with a specific bit. 8. The upper P1 bit value and upper P1 bit value of the gradation value of the input pixel divided into upper P1 bit, middle P2 bit and lower P3 bit.
Means for selecting as an intermediate gradation value of PWM by the value of the P2 bit when the upper P4 bit of the threshold value divided into 4 bits and lower P5 bits is equal, and a lower value of the gradation value of the input pixel.
8. The gradation processing apparatus according to claim 7, further comprising: means for comparing a P3 bit with a lower-order P5 bit of the threshold to determine how to add dither to an intermediate gradation value of the PWM. 9. The number of bits of each bit is P1 = P4 = 4, P2 =
2, P3 = P5 = 2, or P1 = P4 = 4, P2 = 3, P3 = P5 =
9. The gradation processing device according to claim 8, wherein the gradation processing device is variable while maintaining a relationship of 1, or P1 + P2 + P3 = 8, P4 = P1, and P5 = P3. 10. A PWM circuit for performing gradation control by laser pulse width modulation (PWM), comparing means for comparing a value of an input pixel with a threshold, a threshold array for storing the threshold, and an input by the comparing means. Means for converting a tone value of a pixel into a tone value of an output pixel, wherein the comparing means comprises a first group, a second group, and a third group. The value of the third group in the gradation value of the pixel is compared with the value of the fifth group in the threshold value divided into the fourth group and the fifth group, and the value of the second group is changed based on the comparison result. Means for determining an intermediate density output level by PWM. 11. A laser printer comprising a PWM circuit for performing gradation control by modulation (PWM) of a laser pulse width, wherein a gradation value of an output pixel by the PWM with respect to a uniform input is:
A laser printer in which the number of lower two bits or the lower one bit of the gradation value of an input pixel increases while sequentially circulating between four or two pixels in response to an increase in the value.