JP2000004001A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory and manufacturing method thereof, comprising first and 2p contact holes in which the phenomenon of a connecting wiring material in the first contact holes pierce a barrier metal layer diffusing to into impurity diffused regions is suppressed. SOLUTION: An insulation film is used, composed of an Si nitride film formed by the low pressure CVD method as an intermediate insulation film 107 which is inserted between insulation films 106, 108 having first and second contact holes 161, 162 and used for a mask in etching the second contact holes 162, and an Si nitride film formed by the plasma CVD method. Since the plasma CVD method conducts processes at about 200-300 deg.C, it does not destroy the barrier metal layer in the first contact holes and does not activate the diffusion of connection wirings of W, etc. A TEOS film made by low-pressure CVD method has good affinity with a Ti or Pt film, and when this TEOS film is deposited on the intermediate insulation film, a capacitor is formed which is stable having stable electrical characteristics, without damaging its electrical characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device such as a nonvolatile ferroelectric memory having a capacitor using a ferroelectric as a dielectric film.

[0002]

2. Description of the Related Art In a ferroelectric film, electric polarization once generated when an electric field is applied remains even when the electric field is not applied, and an electric field having a certain strength or more in a direction opposite to the electric field. Has the characteristic that the direction of polarization is inverted when is applied. Focusing on the polarization characteristics of the ferroelectric film in which the direction of polarization is reversed, a technology has been developed to realize a nonvolatile ferroelectric memory using a ferroelectric for the dielectric film of the information storage capacitor of the memory cell. ing. Non-volatile memory using ferroelectricity of ferroelectric film (hereinafter referred to as FRAM (Ferro
electric Random Access Memory) is a non-contact card (RF-
Application to ID (Radio Frequency-Identification) is expected. This non-volatile memory is compatible with existing SRA
M (Static RAM), Flash memory, DRAM (Dyn
There is something that is significant if you replace it with amic RAM).

[0003] In these ferroelectric film, as the ferroelectric, PZT (Pb (Zr, Ti0 3), PLZT
((Pb, La) (Zr , Ti) 0 3), PLT ((P
b, La) SrBi ₂ Ta _{20 which} is a ferroelectric containing Pb such as TiO ₃ ) or a layered compound containing Bi
₉ (Y1) is known. At present, FRAM often uses a method in which two transistors and two capacitances are made into one cell (hereinafter, referred to as 2T / 2C cell). Of course, 1T / 1C cell FRAM for high integration
Is also conducting research and development. This 2T / 2C cell is 2
Voltages are applied to the individual capacitors in a combination of high and low, and writing and reading are performed by extracting a signal voltage corresponding to the high and low voltages on the capacitors to a data pair line.
Stable due to complete operation. As for ferroelectric film materials, there are many problems to be solved such as stabilization of film quality in production and imprint phenomenon and fatigue characteristics as material characteristics.

FIG. 12 is a sectional view of a conventional FRAM having a capacitor having a ferroelectric film having ferroelectric characteristics. Semiconductor substrate 1 made of a p-type silicon semiconductor or the like
Is formed with an element isolation region 2 made of SiO ₂ by a LOCOS (Local Oxidization of Silicon) method. An n-type impurity diffusion region 3 used as a source / drain region is formed on the surface of the semiconductor substrate 1. A gate electrode 5 is formed above the source / drain region via a gate oxide film (SiO ₂ ) 4. The gate electrode 5 is made of, for example, a polysilicon film and a tungsten silicide film on the polysilicon film, and the upper surface is protected by a silicon nitride film. The semiconductor substrate 1 has a BPSG (Born Ph.D.) used as an intermediate insulating film formed by a low pressure CVD method so as to cover the gate electrode 5.
Ospharus Silicate Glass) film. The first insulating film 6 is made of CMP (Chemica
It is polished and planarized by lMechanical Polishing). The first insulating film 6 has first contact holes 61 and 6.
1 'is formed. Since the planarized first insulating film 6 has a thickness of about 790 to 890 nm, the height of the contact holes is the same. Each contact hole has a bottom surface in the impurity diffusion region 3 of the semiconductor substrate 1. The connection wirings 71, 71 'are buried in the contact holes 61, 61'.

The wirings 71, 71 'are formed of a Ti film formed on the side walls of the first contact holes 61, 61' and a T film thereon.
It is composed of a barrier metal layer made of an iN film and a tungsten (W) film on a TiN film. The source / drain region 3, the gate oxide film, and the gate electrode constitute a transistor Q. First contact holes 61, 61 '
An intermediate insulating film 7 is formed as a protective film on the first insulating film 6 to suppress the oxidation of the tungsten film embedded in the first insulating film 6. The intermediate insulating film 7 has a reduced pressure CV having a thickness of about 150 nm.
It is composed of a silicon nitride film (Si ₃ N ₄ , formed by the method D, which has the same chemical formula as described above, but is actually described as SiN because its atomic ratio slightly changes). CVD
The (Chemical Vapor Deposition) method is a method of forming a thin film on a semiconductor substrate using thermal energy, plasma discharge, or the like. The low-pressure CVD method is a means for forming a film under reduced pressure in a reaction chamber.
The deposition is performed under the condition that the film forming speed is 0.8 to 1.5 nm / min. The plasma CVD method is a means for generating plasma of a low-pressure reaction gas in a reaction chamber and forming a thin film on a wafer by plasma decomposition. The reaction is performed at about 200 to 300 ° C.

On the intermediate insulating film 7, a ferroelectric capacitor C is formed. Capacitor C is an intermediate insulating film 7
, And a lower electrode 91 connected to a plate line (PL),
A dielectric film 92 made of a ferroelectric material having ferroelectric characteristics and an upper electrode 93 are sequentially stacked. The lower electrode is composed of a Ti film in contact with the intermediate insulating film 7 and a Pt film formed on the Ti film. The ferroelectric film 92 is made of, for example, a PZT film. The upper electrode 93 is made of a Pt film. A second insulating film 8 is formed on intermediate insulating film 7 so as to cover capacitor C. The second insulating film 8 is made of a TEOS film (abbreviated as TEOS, an organic oxysilane Si (OC ₂ H).
₅ ) SiO ₂ film formed by thermally decomposing ₄ ), and has a thickness of about 950 nm. Second insulating film 8
Is polished and flattened by CMP or the like. The second insulating film 8 and the intermediate insulating film 7 are etched, and the second contact holes 62 and 62 'are formed by this etching. The planarized second insulating film 8 has a thickness of 95
Since it is 0 nm, the heights of the second contact holes 62 and 62 'are the same. These second contact holes 6
2 and 62 'are first contact holes 61 and 6 respectively.
The wirings 72, 72 'connected to and embedded in 1' are also connected to the wirings 71, 71 '. Wiring 72, 72 '
Is composed of a barrier metal layer composed of a Ti film and a TiN film formed thereon on the side walls of the second contact holes 62 and 62 ', and a tungsten film formed thereon.

On the second insulating film 8, wirings 10, 10 'are formed. A Ti film, a TiN film,
An Al film and a TiN film are sequentially deposited and patterned to form a lower barrier metal layer (Ti film / TiN film) / Al
Wirings 10 and 10 'composed of a film / upper barrier metal layer (TiN film) are formed. This wiring 10, 10 '
Is a first layer aluminum wiring on the semiconductor substrate 1. The second insulating film 8 is formed so as to cover the wirings 10 and 10 '.
The third insulating film 9 is formed thereon. The third insulating film 9 is made of a TEOS film and has a thickness of about 1240 nm. The third insulating film 9 is polished by CMP or the like and flattened. The third insulating film 9 is etched, and the wiring 10 and the
Third contact holes 11, 11 'reaching the upper surface of 10' are formed. The thickness of the planarized third insulating film 9 is 1240 nm, and the thickness of the wirings 10 and 10 ′ is 520 nm.
nm, the third contact holes 11, 11 '
Has a height of about 720 nm. The wirings 12, 12 'embedded in the third contact holes 11, 11' are:
Each is connected to the connection wiring 72, 72 '. The connection wirings 12, 12 'are connected to the third contact holes 11, 11'.
It is composed of a tungsten film embedded in the substrate.

[0010] Wirings 13 and 13 ′ are formed on the third insulating film 9. A Ti film, a TiN film,
An Al film and a TiN film are sequentially deposited and patterned to form a lower barrier metal layer (Ti film / TiN film) / Al
Wirings 13, 13 'composed of a film / upper barrier metal layer (TiN film) are formed. This wiring 13, 13 '
Is a second layer aluminum wiring on the semiconductor substrate 1. The third insulating film 9 is formed so as to cover the wirings 13 and 13 '.
Is covered with a protective insulating film 14 such as a silicon nitride film formed by a plasma CVD method. Wiring 1
3 is connected to the upper electrode 93 of the capacitor C,
3 'is connected to the bit line (BT). FIG.
It is a circuit diagram of a conventional FRAM cell on a semiconductor substrate.

[0009]

As described above, a dense and oxidation-resistant silicon nitride film (SiN) is usually formed on the surface of the first contact hole to suppress oxidation of the surface of the tungsten. Then, a TEOS film is deposited thereon as an interlayer insulating film. When forming the second contact hole on the first contact hole, TEO
Reactive ion etching of S film (RIE: Reactive Ion
Etching) vertically. At that time,
The selectivity between the TEOS film and the silicon nitride film should be 10 or more. Then, the RIE is terminated at the interface between the TEOS film and the silicon nitride film or in the silicon nitride film. Next, the silicon nitride film on the tungsten film in the contact hole is etched by RIE, and the etching is terminated at the tungsten film interface to form a second contact hole.

Here, if a silicon nitride film (SiN) deposited by a low-pressure CVD method is used as an etching mask for forming the second contact hole, a high temperature (70
At a bottom corner of the first contact hole, tungsten penetrates through the barrier metal layer (Ti film / TiN film) and diffuses into the impurity diffusion region formed in the semiconductor substrate. This adversely affects the electrical characteristics of the transistor. Further, if RIE is performed in a state where misalignment of the reticle has occurred in the PEP of the second contact hole, there occurs a problem that the etching of the second contact hole proceeds to the semiconductor substrate. The present invention has been made under such circumstances, and the first and second phenomena in which the connection wiring material in the first contact hole penetrates through the barrier metal layer and diffuses into the impurity diffusion region is suppressed. And a method of manufacturing a semiconductor memory device having a contact hole, wherein a capacitor formed between the insulating films having the first and second contact holes is stably disposed between the insulating films. provide.

[0011]

SUMMARY OF THE INVENTION The present invention provides first and second embodiments.
Is inserted between the insulating films in which the contact holes are formed.
Characterized in that an insulating film composed of a silicon nitride film formed by a low pressure CVD method and a silicon nitride film formed by a plasma CVD method is used as an intermediate insulating film used as a mask when etching the contact hole of (1). I do. Further, when the lower electrode of the capacitor formed on the intermediate insulating film is composed of a titanium (Ti) film and a platinum (Pt) film formed on the titanium (Ti) film, the lower electrode is formed between the titanium film and the intermediate insulating film. A TEOS film formed by a low-pressure CVD method is provided. Since the plasma CVD process is performed at a low temperature (about 200 to 300 ° C.), the barrier metal layer formed in the first contact hole is not broken, and the diffusion of connection wiring such as tungsten is activated. There is no. In addition, decompression CV
The TEOS film formed by the D method has good compatibility with a titanium film or a platinum film. Therefore, when such a TEOS film is deposited on the intermediate insulating film, the capacitor is stabilized and the electric characteristics are stabilized without impairing the electric characteristics. The formed capacitor is formed.

That is, the semiconductor memory device of the present invention provides a semiconductor substrate, a switching transistor formed on the semiconductor substrate, having a drain or a source connected to a bit line, and the semiconductor transistor so as to cover the switching transistor. A first insulating film formed on the substrate, an intermediate insulating film formed on the first insulating film, and a source or drain of the switching transistor formed on the intermediate insulating film; A charge storage capacitor including a first electrode, a second electrode in contact with the intermediate insulating film and connected to a plate line, and a dielectric film; and the intermediate insulating film so as to cover the charge storage capacitor. A second insulating film formed on the first insulating film, and a first insulating film formed on the first insulating film.
Contact hole and a second hole formed in the second insulating film.
And a wiring for electrically connecting the drain or source and the first electrode through the contact hole of (a). The intermediate insulating film is formed by a silicon nitride film formed by a low pressure CVD method and a plasma CVD method. And a silicon nitride film.

The capacitor may use a dielectric film made of a ferroelectric material having ferroelectric characteristics. The intermediate insulating film is sandwiched between first and second silicon nitride films formed by a low pressure CVD method and a third silicon nitride film formed by a plasma CVD method. May be configured.
A plurality of different types of silicon nitride films can be easily and continuously stacked only by appropriately changing the conditions in the CVD reaction chamber.
The intermediate insulating film may have a thickness of 135 nm to 165 nm, and the total thickness of the first and second silicon nitride films may be 10 nm to 20 nm. The side wall of the first contact hole is formed perpendicular to the first insulating film, and the side wall of the second contact hole is formed in a tapered shape with respect to the second insulating film. Alternatively, the opening may have an area larger than the bottom surface. When the second contact hole is formed, a contact hole that penetrates the second insulating film and reaches the semiconductor substrate by etching is not formed.

A portion of the first insulating film which is in contact with the lower surface of the intermediate insulating film is a TE formed by a plasma CVD method.
The other parts may be made of a BPSG film. In the case of using CMP when burying the connection wiring in the first contact hole, the BPSG film having a high polishing rate is not polished too much, and the gate electrode buried in the first insulating film is not damaged. A TEOS film formed by a low pressure CVD method may be interposed between the capacitor and the intermediate insulating film. Since the TEOS film can deposit a lower electrode of a capacitor using a ferroelectric film with good orientation, a ferroelectric film can be grown on this lower electrode with good orientation. The second electrode of the capacitor may include a titanium film and a platinum film formed thereon, and the titanium film may be formed in contact with the TEOS film formed by the low-pressure CVD method. .
The TEOS film formed by the low-pressure CVD method has a thickness of 135 nm to 165 nm.
It may have a thickness of 200 nm. The first electrode of the capacitor is formed on the ferroelectric film, and the ferroelectric film is formed on the first electrode and on the ferroelectric film on which the first electrode is not formed. A protective film made of the same material as the dielectric film may be formed. Since the ferroelectric film is used as a protective film covering the upper electrode, the ferroelectric film is formed with good orientation.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, a step of forming a switch transistor having a drain or a source connected to a bit line on a semiconductor substrate; Forming a first insulating film thereon, etching the first insulating film to form a first contact hole reaching a drain or a source of the semiconductor substrate, and forming a first contact hole in the first contact hole. Burying a connection wiring in the first contact hole; forming an intermediate insulation film on the first insulation film so as to cover the connection wiring in the first contact hole; Forming a charge storage capacitor including an electrode, a second electrode, and a dielectric film sandwiched between the electrodes; and forming the intermediate capacitor so as to cover the charge storage capacitor. Forming a second insulating film on the film; and etching the second insulating film and the intermediate insulating film to form a second contact hole reaching the connection wiring in the first contact hole. And a step of burying a connection wiring in the second contact hole; and a connection wiring in the first and second contact holes, wherein the drain is formed through the first contact hole and the second contact hole. Or forming a wiring for electrically connecting the source and the first electrode, wherein the intermediate insulating film comprises:
It is characterized by comprising a silicon nitride film formed by a low pressure CVD method and a silicon nitride film formed by a plasma CVD method.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. 1, 6 to 10. FIG. 1 is a sectional view of a nonvolatile ferroelectric memory (FRAM). MOS transistor Q is formed on p-type silicon semiconductor substrate 100. MOS transistor Q has a source / drain region 103 composed of an n-type impurity diffusion region, a gate oxide film 10
4, the gate electrode 105 and the like. Gate electrode 1
05 is connected to a word line (WL). On the MOS transistor Q, an interlayer insulating film (first insulating film) 106
Are formed. The first insulating film 106 is formed by low pressure CVD.
It is composed of a BPSG film formed by a method. p
L is applied to the semiconductor substrate 100 made of a silicon semiconductor or the like.
Element isolation region 1 composed of SiO ₂ by OCOS
02 is formed. In a surface region of the semiconductor substrate 100, an n-type impurity diffusion region 103 used as a source / drain region is formed. A gate electrode 105 is formed above the source / drain region via a gate oxide film (SiO ₂ ) 104. Gate electrode 105
Comprises, for example, a polysilicon film and a tungsten silicide film on the polysilicon film, and the upper surface of the silicide film is protected by a silicon nitride film.

The semiconductor substrate 100 is covered with a first insulating film (interlayer insulating film) 106 made of a BPSG film formed by a low pressure CVD method so as to cover the gate electrode 105. The first insulating film 106 is polished and flattened by CMP. The first insulating film 106 has a first
Contact holes 161 and 161 'are formed. First,
BP using a mixed gas consisting of CHF ₃ + O ₂ + CO
The surface of the SG film is etched by RIE, and then O ₂ and C
First contact holes 161 and 16 having vertical sidewalls are further subjected to trench etching at a portion opened by RIE etching with a mixed gas with F ₄ (flow rate ratio of 1 or more).
1 'is formed. The planarized first insulating film 106
For example, since the film thickness is about 790 to 890 nm, the first
The contact holes 161 and 161 'have the same height. Each contact hole has its bottom surface arranged in the impurity diffusion region 103 of the semiconductor substrate 100. The first contact holes 161 and 161 ′ have connection wirings 17.
1, 171 'are embedded. Connection wiring 171, 1
Reference numeral 71 'includes a barrier metal layer formed of a Ti film and a TiN film formed on the side walls of the first contact holes 161 and 161', and a tungsten (W) film on the TiN film. The source / drain region 103, the gate oxide film 104, and the gate electrode 105 constitute a transistor C.

The connection wiring includes a Ti film having a thickness of about 40 nm on the first insulating film 106 including the inside of the first contact hole.
A TiN film having a thickness of about 60 nm is sequentially deposited by a normal deposition technique such as high melting point long sputtering, and tungsten is deposited thereon in a blanket shape to a thickness of about 620 nm. Then, crystallization treatment is further performed at 300 ° C. × 60 minutes in an N ₂ atmosphere. Then, these laminates are subjected to CMP or CD
The first contact holes 161 and 16 are formed by a method including E (Chemical Dry Etching) and a micro asher process.
The layered structure on the first insulating film 106 other than the material deposited in 1 'is removed, and the surface of the first insulating film 106 is flattened. In order to suppress the oxidation of the tungsten embedded in the first contact holes 161 and 161 ', a film having a thickness of 135 to 165n is formed on the first insulating film 106 as a protective film.
m of the intermediate insulating film 107 is formed. Intermediate insulating film 107
Is composed of a silicon nitride film (PCVD SiN) formed by a plasma CVD method and a silicon nitride film (LPCVD SiN) formed by a low pressure CVD method.

The silicon nitride film formed by the low-pressure CVD method is, for example, dichlorosilane and ammonia at a temperature of 7
Reaction is performed under the conditions of 00 to 780 ° C. and a pressure of 20 to 100 Pa to deposit on the first insulating film. The silicon nitride film formed by the plasma CVD method uses, for example, SiH ₄ —NH ₃ as a reaction gas and has a substrate temperature of 200 to ₃ μm.
About 00 ° C, pressure 0.2 Torr, growth rate 30n
The reaction is performed under the condition of m / min, and is deposited on the insulating film.

Here, the details of the intermediate insulating film will be described with reference to FIGS. FIG. 6 is a cross-sectional view of a semiconductor substrate having an intermediate insulating film formed on a contact hole.
FIG. 3 is a cross-sectional view of a conventional semiconductor substrate having an intermediate insulating film formed on a contact hole. First contact hole 1
61 is formed by the RIE etching and the trench etching as described above, and the bottom thereof enters the impurity diffusion region 103 formed in the semiconductor substrate 100. Most of the first insulating film 106 is composed of the BPSG film 106A, but a portion in contact with the semiconductor substrate 100 is composed of the same oxide film 106B as the gate oxide film.
Therefore, since the etching rates of the BPSG film 106A, the oxide film 106B, and the impurity diffusion region 103 are different, the diameter of the contact hole varies depending on the depth. In the conventional etching method, as shown in FIG. 7, the cross section of the contact hole is wider in the portion of the impurity diffusion region 3, that is, in the vicinity of the bottom than in the portion of the oxide film 6B. In such a state, the barrier metal layer 7 adhered to the side wall and the bottom by sputtering.
1B is not formed near the bottom corner, and the connection wiring 7B is not formed.
The portion of the tungsten film 71 </ b> A directly contacts the semiconductor substrate 1. Therefore, the diffusion of tungsten into the semiconductor substrate 1 was remarkable.

However, in this embodiment, as described above,
Mixed gas of O ₂ and CF ₄ (flow ratio 1 (O ₂ > CF ₄ )
Since silicon is not over-etched by performing the trench etching using the above-described method, a substantially vertical side wall is formed near the bottom of the semiconductor substrate portion.
Therefore, in the side wall of the first insulating film 106, the portion of the BPSG film 106A and the impurity diffusion region 103 is substantially vertical, the portion between the two where the oxide film 106B exists is inclined, and the bottom corner is formed. It becomes round and has a shape having a predetermined radius. With such an internal shape of the contact hole, a barrier metal material to be sputtered is uniformly deposited on the entire side wall, and as a result, the barrier metal layer 171B is formed between the tungsten film 171A and the impurity diffusion region 103 of the semiconductor substrate 100. There is no longer any direct contact between them. In a CVD method for forming a thin film on a semiconductor substrate, a low-pressure CVD method is a means for forming a film in a reaction chamber under a reduced pressure, and the film formation temperature is 700
The plasma CVD method generates plasma of a low-pressure reaction gas in a reaction chamber and forms a thin film on a wafer by plasma decomposition. At about 200 to 300 ° C.

After the connection wiring 171 is buried in the first contact hole 161, an intermediate insulating film 107 is formed on the first insulating film 106. The intermediate insulating film 107 has a three-layer CV
A first layer is a silicon nitride film (LP) having a thickness of about 10 to 20 nm formed by a low pressure CVD method.
(CVD SiN) 107A, the second layer has a thickness of 110 to
A silicon nitride film (PCVDSiN) 107B formed by a plasma CVD method with a thickness of about 130 nm, and a third layer is a silicon nitride film (LPCVDSiN) 107C formed by a low pressure CVD method with a thickness of about 10 to 20 nm.
It is composed of

The description of FIG. 1 will be continued with reference to FIGS. 8 and 9. FIG. 8 is a cross-sectional view of a semiconductor substrate having a capacitor on an intermediate insulating film formed on a contact hole.
FIG. 3 is a plan view showing a capacitor on an intermediate insulating film. A ferroelectric capacitor C is formed on the intermediate insulating film. In this embodiment, a TEOS film 107D is formed on the intermediate insulating film 107 as an intermediate insulating film by a low pressure CVD method. Of course, in the present invention, such an intermediate insulating film 107 is used.
The presence of D is not essential and may not be present. The intermediate insulating film 107D is made of TEOS formed by a low pressure CVD method.
It is made of a film and has a thickness of about 200 nm. In this embodiment, a capacitor is directly mounted on the TEOS film 107D. The capacitor C is composed of a laminated body in which a lower electrode 191 connected to the PL directly in contact with the TEOS film 107D, a dielectric film 192 made of a ferroelectric having ferroelectric properties, and an upper electrode 193 are sequentially deposited.

The lower electrode 191 is formed by, for example, sputtering or the like, and is a Ti film 191B having a thickness of about 20 nm in contact with the intermediate insulating film 107D and a Pt film having a thickness of about 175 nm formed on the Ti film 191B. 191A
It is composed of The ferroelectric film 192 is made of, for example, P
ZT film or strontium bismuth tantalate niobate (SBT: SrBi ₂ (Nb, Ta) ₂ O ₉ ) film, etc.
It is formed using a VD method or the like. The thickness of the ferroelectric film 192 is about 240 nm. The upper electrode 193 has a thickness of 1
It is composed of a Pt film of about 75 nm, and is formed by a sputtering method. The laminates forming these capacitors are sequentially patterned and shaped into a capacitor structure. The upper electrode 193 has a smaller area than the ferroelectric film 192, and the protective film 19 made of the same material as the ferroelectric film is formed on the ferroelectric film 192 so as to cover the upper electrode 193.
4 are formed. Due to the protective film 194, the ferroelectric film 192 exists in a stable state even during or after the manufacture of the ferroelectric film 192. A second insulating film 108 is formed on intermediate insulating films 107 and 107D so as to cover capacitor C. The second insulating film 108 is made of a TEOS film formed by a plasma CVD method,
The thickness is about 1200 nm.

The second insulating film 8 is polished and flattened by CMP or the like. The second insulating film 108 and the intermediate insulating films 107 and 107D are first formed of C ₄ F ₈ + CO + Ar
The opening is formed by performing trench etching on the second insulating film 108 using a mixed gas of
E etching is performed to form the second contact holes 162, 16
Form 2 '. Then, the second contact holes 162, 1
A Ti film having a thickness of 40 nm and a Ti film having a thickness of 60 nm
The N film is coated by high melting point sputtering, and a tungsten film is further deposited on the TiN film to form connection wirings 172, 1
72 'is formed. Since the second insulating film 108 is flattened and has a thickness of about 1200 nm, the heights of the second contact holes 162 and 162 'are the same. These second contact holes 162 and 162 'are connected to the first contact holes 161 and 161', respectively.
The embedded wirings 172, 172 'are also wirings 171, 17
1 '. Wirings 110 and 110 'are formed on the second insulating film 108. Second insulating film 10
8, a Ti film, a TiN film, an Al film and a TiN film are sequentially deposited, and are patterned to form a lower barrier metal layer (T
i film / TiN film) / Al film / upper barrier metal layer (Ti
Wirings 110 and 110 'composed of N film) are formed. The wirings 110 and 110 ′ are the first-layer aluminum wiring (1Al) on the semiconductor substrate 1. Wiring 11
A third insulating film 109 is formed on the second insulating film 108 so as to cover 0 and 110 '. The third insulating film 109 is made of TEOS formed by a plasma CVD method.
It is made of a film, and its thickness is about 1240 nm.

The third insulating film 109 is polished and flattened by CMP or the like. The third insulating film 109 is etched to form third contact holes 111 and 111 'extending from the surface to the upper surfaces of the wirings 110 and 110'. The thickness of the planarized third insulating film 9 is 1240 nm.
Since the thickness of the wirings 110 and 110 'is about 520 nm, the height of the third contact holes 111 and 111' is about 720 nm. Third contact hole 11
Wirings 112, 112 'embedded in 1, 111'
Are connected wiring 1 via wirings 110 and 110 ', respectively.
72, 172 '. Connection wiring 112, 1
Reference numeral 12 'denotes a tungsten film formed in the third contact holes 111 and 111'. Further, wirings 113 and 113 'are formed on the third insulating film 109. A Ti film, a TiN film, an Al film, and a TiN film are sequentially deposited on the third insulating film 109 and are patterned to form a lower barrier metal layer (Ti film / TiN film) / Al film / upper barrier metal layer (TiN film). ) Composed of wiring 11
3, 113 'are formed. These wirings 113, 113 '
Are the second-layer aluminum wirings (2
Al). The third insulating film 109 is covered with a protective insulating film 114 such as a silicon nitride film formed by a plasma CVD method so as to cover the wirings 113 and 113 '. The wiring 113 is connected to the upper electrode 93 of the capacitor C, and the wiring 113 'is connected to the bit line (BL).

When the etching gas for forming the first contact hole is used, the angular shape of the bottom corner edge portion of the contact hole is rounded and R (R) is used.
And the coverage of the barrier metal layer is improved. In addition, by forming a three-layer structure using a silicon nitride film formed by a plasma CVD method in addition to a silicon nitride film formed by a conventional low pressure CVD method, the bottom corner edge of the first contact hole is affected by thermal stress. It is possible to suppress penetration of the tungsten barrier metal layer in the portion.

Here, the step of forming the second contact hole will be described with reference to FIG. Second contact hole 1
62 is etched by RIE.
Since the etching selectivity between the insulating film (TEOS film) 108 and the intermediate insulating film (silicon nitride film) 107 is 10 or more, in the first trench etching, the etching proceeds while forming a reverse taper, and the surface of the intermediate insulating film 107 or Etching ends in that. Next, when this intermediate insulating film is subjected to RIE etching, the etching ends at the tungsten interface on the surface of the first contact hole. Since the second contact hole 162 is etched in a reverse taper shape, the tip of the second contact hole 162 that is etched even if misalignment occurs with the first contact hole abuts any part on the side wall of the first contact hole 161. Therefore, the second contact hole 162 is not dug into the semiconductor substrate 100. Therefore, the second insulating film 108 and the intermediate insulating film 10
If the film thickness control of 7 is sufficiently performed, continuous reactive etching can be easily performed. Further, even when the reticle misalignment between the first contact hole 161 and the second contact hole 162 occurs, the continuous reactive ion etching controls the etching time so as to end in the BPSG film of the first insulating film 106. It is also possible to do.

On a silicon nitride film formed by a low pressure CVD method, a TEOS film (hereinafter referred to as P
TEOS film) and FR
It is assumed that a capacitor is formed by depositing and processing a ferroelectric film of an AM capacitor. After this, the ferroelectric film
Usually, heat treatment is applied to stabilize the crystal structure. The heat treatment includes a heating step performed at 650 ° C. × 60 minutes in an O ₂ atmosphere and a step performed at 650 ° C. × 5 seconds → 850 ° C. × 5 seconds in an O ₂ atmosphere. However, since the difference in thermal expansion between the PTEOS film and the Ti film is large, film peeling occurs at the interface between the PTEOS film and the Ti film, and cloudiness occurs. Further, a lower electrode composed of a Ti film and a Pt film thereon is formed on a silicon nitride film, and a ferroelectric film of an FRAM capacitor is deposited and processed. Thermal stress dislocations occur due to the difference in temperature distribution in the inside. In this embodiment, the thermal expansion causes the LPTEOS film close to the Ti film to be interposed between the lower electrode and the intermediate insulating film, so that peeling or clouding of the film is less likely to occur.

Further, for example, in a heat treatment performed immediately after depositing and processing a ferroelectric film made of PZT, lead contained in the ferroelectric film penetrates the interface between the lower electrode and the LPTEOS film and reacts with oxygen. Lead glass (PbO.SiO ₂ ) is generated, and this lead glass may cause film quality deterioration such as film peeling. Therefore, in this embodiment, the LPT
After the formation of the EOS film, for example, a thermal oxidation step of hydrogen combustion at about 700 ° C. for about 30 minutes is added to improve the film quality of the LPTEOS film and improve the orientation of the lower electrode. This is because the titanium silicide film, which acts to prevent the lead glass from penetrating below the lower electrode, is formed by the LPT.
This is because it is generated at the interface between the EOS film and the Ti film. Since the plasma CVD process is performed at a low temperature, the barrier metal layer formed in the first contact hole is not broken, and the diffusion of connection wiring such as tungsten is not activated. Further, the quality of the film for depositing a Ti film on the TEOS film by the low pressure CVD method is improved, and the electric characteristics of the capacitor are not stably deteriorated. Further, the TEOS film formed by the low pressure CVD method can be formed with good orientation, and the orientation of the Ti film thereon can be improved. it can.

Next, a second embodiment will be described with reference to FIG. This embodiment is characterized by a method of forming a first contact hole of a semiconductor memory device and a connection wiring embedded in the first contact hole. FIG. 11 shows a manufacturing process of a semiconductor substrate showing the first contact hole. It is sectional drawing. The structures of the intermediate insulating film, the second insulating film, the second contact hole, and the like formed on the first contact hole are the same as those of the first embodiment, and therefore the description is omitted. For example, an element isolation region composed of SiO ₂ by LOCOS is formed on a semiconductor substrate 200 made of a p-type silicon semiconductor or the like. In the surface region of the semiconductor substrate 200, an n-type impurity diffusion region 203 used as a source / drain region is formed. A gate electrode is formed above the source / drain region via a gate oxide film (SiO ₂ ). The gate electrode is composed of, for example, a polysilicon film and a tungsten silicide film on the polysilicon film, and the upper surface of the silicide film is protected by a silicon nitride film. The semiconductor substrate 200 is covered with a first insulating film (interlayer insulating film) 206 having a BPSG film by a low pressure CVD method so as to cover the gate electrode. The first insulating film 206 is polished and flattened by CMP. Next, a TEOS film 207 having a thickness of about 100 nm is formed on the first insulating film 206 by a plasma CVD method.

The TEOS film 2 by this plasma CVD method
07 and a first contact hole 26 in the first insulating film 206.
1 is formed. First, a TEOS film by plasma CVD and a BPSG film surface by low pressure CVD are subjected to RIE etching using a mixed gas of CHF ₃ + O ₂ + CO, and then a mixed gas of O ₂ and CF ₄ (flow rate ratio of 1 or more). ), Trench etching is further performed on the portion opened by RIE etching to form a first portion having vertical side walls.
Contact hole 261 is formed. The first contact hole 261 is formed in the impurity diffusion region 203 of the semiconductor substrate 100.
The bottom surface is arranged. Next, the first insulating film 206 including the inside of the first contact hole 261 and the plasma C
A barrier metal layer 271B composed of a Ti film having a thickness of about 40 nm and a TiN film having a thickness of about 60 nm is sequentially deposited on the TEOS film 207 by the VD method by high melting point long sputtering or the like, and a tungsten film having a thickness of about 620 nm is formed thereon. 271A is deposited. Then, these laminates are
Polishing is performed by an MP method or the like to remove unnecessary laminate material. Then, the material deposited in the first contact hole 261 is left, and TEO by the other plasma CVD method is used.
The laminate material on the S film 207 is removed.

Since the TEOS film formed by the plasma CVD method has a sufficiently lower polishing rate than the BPSG film formed by the low pressure CVD method, the BPSG film formed by the low pressure CVD method is polished by over polishing to form, for example, a semiconductor element isolation region. It is possible to suppress a phenomenon that has conventionally occurred well, such as damaging the gate electrode. As described above, the first contact hole 261 is made of a Ti film and a TiN film.
1B and a connection wiring 271 composed of a tungsten film 271A is embedded. Subsequent steps and the formation of an intermediate insulating film, a second insulating film, a second contact hole, and the like formed on the first contact hole are the same as those in the first embodiment, and therefore description thereof is omitted. . Also in this embodiment, a silicon nitride film formed by a low pressure CVD method as an intermediate insulating film inserted between the insulating films in which the first and second contact holes are formed and used as a mask when etching the contact holes. And an insulating film composed of a silicon nitride film formed by a plasma CVD method. Since plasma CVD is performed at a low temperature, the barrier metal layer formed in the first contact hole is not broken, and the diffusion of connection wiring such as tungsten is not activated.

As described above, the present invention relates to the structure of an intermediate insulating film inserted in the middle of a contact hole having a two-stage structure for the purpose of suppressing surface oxidation, so that it can be applied to any semiconductor device such as a memory and a logic. Can be. Particularly, it is optimal to apply the present invention to a semiconductor device having a ferroelectric film having ferroelectric characteristics, such as a nonvolatile ferroelectric memory (FRAM). Hereinafter, the semiconductor memory device described in the first and second embodiments with reference to FIGS.
The operation will be described below. FIG. 2 is a hysteresis characteristic diagram showing an applied voltage / polarization characteristic of the ferroelectric film, and FIG.
FIG. 4 is a graph showing a hysteresis characteristic in an unfavorable state as an FRAM cell.
FIG. 5 is a circuit diagram of the AM cell, and FIG. 5 is a potential change diagram of the plate electrode PL at the time of writing in the FRAM cell. Figure 2 shows PZT
4 shows applied voltage / polarization characteristics of a ferroelectric thin film such as a film. The ferroelectric thin film has a hysteresis characteristic as shown in FIG. Then, a state where no voltage is applied, that is, V = 0
The remanent polarization Pr in the state (V) is “positive” or “negative”
, The data can be stored.

FIG. 3 shows hysteresis characteristics which are not preferable for the ferroelectric memory cell of the FRAM. In other words, there is a problem that the remanent polarization Pr is very small, and as a result, a read margin by the sense amplifier is reduced, and data is easily lost due to external disturbance. The characteristic shown in FIG. 3 is a hysteresis characteristic at a high temperature of 80 ° C. Next, a write operation of a memory cell using a ferroelectric thin film will be described with reference to FIGS.
In a nonvolatile ferroelectric memory using FRAM cells, one memory cell is composed of two MOS transistors Q1 and Q2 and ferroelectric capacitors C1 and C2. 4 (a), that is, the capacitor C1 has an upward polarization (hereinafter referred to as positive polarization) as shown by an upward arrow in the figure, and the capacitor C2 has a downward polarization as shown by an arrow in the figure. Is defined as "1" when a downward polarization (hereinafter referred to as negative polarization) appears in FIG.
That is, a state in which negative polarization appears in the capacitor C1 and positive polarization appears in the capacitor C2 is defined as "0".

("1" Write Operation) Hereinafter, steps for writing "1" to a memory cell will be described. First, 5 V is applied to the bit line BL, and 0 V is applied to the bit line / BL ("/" indicates an inverted signal; the same applies hereinafter). Then, 7 V is applied to the word line WL, and 0 V is applied to the plate electrode PL. In this state, the capacitor C 1
2A, and the capacitor C2 is in the state of FIG. 2B. Subsequently, PL is set to 5V. As a result, the capacitor C1 is in the state shown in FIG. 2B, and the capacitor C2 is in the state shown in FIG. 2C. Subsequently, PL is set to 0V. As a result, the capacitor C1 is in the state shown in FIG. 2A, and the capacitor C2 is in the state shown in FIG. FIG. 5 shows a change in the potential (VPL) of the plate electrode PL during writing. As described above, the state shown in FIG. 4A, that is, the positive polarization appears in the capacitor C1, and the negative polarization appears in the capacitor C2, and "1" writing is realized.

("0" Write Operation) Hereinafter, steps for writing "0" to a memory cell will be described. First, 0 V is applied to the bit line BL, and 5 V is applied to the bit line / BL. Then, 7 V is applied to the word line WL, and 0 V is applied to the plate electrode PL. In this state, the capacitor C1 is in the state shown in FIG. 2B, and the capacitor C2 is in the state shown in FIG. Subsequently, PL is set to 5V. As a result, the capacitor C1 is in the state of FIG. 2C, and the capacitor C2 is in the state of FIG. 2B. Then, PL
To 0V. As a result, the capacitor C1 is connected to d in FIG.
And the capacitor C2 is in the state of FIG. As described above, the state shown in FIG. 4B, that is, the negative polarization appears in the capacitor C1, and the positive polarization appears in the capacitor C2, and "0" writing is realized. The FRAM as described above is used for a non-power-supply ID device such as an RFID because the power consumption is very small.

[0038]

According to the plasma CVD method, since the processing is performed at a low temperature, the barrier metal layer formed in the first contact hole is not broken, and the diffusion of the connection wiring such as tungsten is not activated. In addition, since the TEOS film formed by the low pressure CVD method has good compatibility with the Ti film and the Pt film, when such a TEOS film is deposited on the intermediate insulating film, the capacitor is stabilized and the electric characteristics thereof are not impaired. Therefore, a semiconductor memory device having stable electric characteristics and a method for manufacturing the same can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor memory device of the present invention.

FIG. 2 is a hysteresis characteristic diagram showing an applied voltage / polarization characteristic of a ferroelectric film.

FIG. 3 is a hysteresis characteristic diagram in a state unfavorable as an FRAM cell.

FIG. 4 is a circuit diagram of an FRAM cell illustrating a writing operation of the FRAM.

FIG. 5 shows a plate electrode PL at the time of writing in an FRAM cell;
FIG.

FIG. 6 is an enlarged partial sectional view of the semiconductor substrate shown in FIG. 1;

FIG. 7 is a sectional view of a conventional semiconductor substrate comparing FIG. 6;

FIG. 8 is an enlarged sectional view of the capacitor shown in FIG. 1;

FIG. 9 is a plan view of the capacitor shown in FIG. 8;

FIG. 10 is a cross-sectional view of the semiconductor substrate illustrating a manufacturing process of a second contact hole in the first embodiment.

FIG. 11 is a cross-sectional view of a semiconductor substrate illustrating a step of embedding a connection wiring in a first contact hole of the second embodiment.

FIG. 12 is a cross-sectional view of a conventional semiconductor memory device.

[Explanation of symbols]

1, 100, 200 ... semiconductor substrate, 2, 102
..Element isolation region, 3, 103, 203 ... impurity diffusion region (source / drain region), 4, 104 ... gate oxide film, 5, 105 ... gate electrode, 6, 1
06, 206... First insulating film (interlayer insulating film), 7,
107: intermediate insulating film, 8, 108: second insulating film, 9, 109: third insulating film, 10, 1
0 ', 13, 13', 110, 110 ', 113, 11
3 '... Wiring, 11, 11', 111, 111 ',.
A third contact hole, 12, 12 ', 71, 71',
72, 72 ', 112, 112', 171, 171 ',
172, 172 ', 271 ... connection wiring, 14, 11
4 ... Protective insulating film, 61, 61 ', 161, 16
1 ′, 261... First contact hole, 62, 6
2 ', 162, 162' ... second contact hole, 7
1A, 171A, 271A ... tungsten (W)
Film, 71B, 171B, 271B ... barrier metal layer, 91, 191 ... lower electrode, 92, 192
..Ferroelectric film, 93, 193... Upper electrode, 107
A, 107C: silicon nitride film formed by low-pressure CVD, 107B: silicon nitride film formed by plasma CVD, 107D: intermediate insulating film (TEOS film by low-pressure CVD), 191A ..P
t film, 191B ... Ti film, 194 ... Protective film.

Claims (8)

[Claims] 1. A semiconductor substrate, a switching transistor formed on the semiconductor substrate and having a drain or a source connected to a bit line, and a first transistor formed on the semiconductor substrate to cover the switching transistor. An intermediate insulating film formed on the first insulating film; a first electrode formed on the intermediate insulating film and connected to a source or a drain of the switching transistor; A charge storage capacitor having a second electrode and a dielectric film in contact with the film and connected to the plate line; and a second electrode formed on the intermediate insulating film so as to cover the charge storage capacitor. The drain or source through a first contact hole formed in the first insulating film and a second contact hole formed in the second insulating film. A wiring for electrically connecting the first electrode; and the intermediate insulating film is composed of a silicon nitride film formed by a low pressure CVD method and a silicon nitride film formed by a plasma CVD method. A semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein said capacitor has a dielectric film made of a ferroelectric material having ferroelectric characteristics. 3. The intermediate insulating film is sandwiched between first and second silicon nitride films formed by a low-pressure CVD method and the first and second silicon nitride films.
2. The semiconductor memory device according to claim 1, comprising a third silicon nitride film formed by a method. 4. The side wall of the first contact hole is formed perpendicular to the first insulating film, and the side wall of the second contact hole is formed with respect to the second insulating film. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed in a tapered shape, and the opening has an area larger than a bottom surface. 5. The semiconductor memory device according to claim 2, wherein a TEOS film formed by a low pressure CVD method is interposed between said capacitor and said intermediate insulating film. 6. The capacitor according to claim 1, wherein said second electrode comprises a titanium film and a platinum film formed thereon, and said titanium film is formed of TEO formed by said low pressure CVD method.
6. The semiconductor device according to claim 5, wherein the first film is formed in contact with the S film.
3. The semiconductor memory device according to claim 1. 7. The ferroelectric film, wherein the first electrode of the capacitor is formed on the ferroelectric film, and the first electrode of the ferroelectric film on which the first electrode is not formed is formed on the ferroelectric film. 7. The semiconductor memory device according to claim 5, wherein a protective film made of the same material as the ferroelectric film is formed thereon. 8. A step of forming a switching transistor having a drain connected to a bit line or a source on a semiconductor substrate, and forming a first insulating film on the semiconductor substrate so as to cover the switching transistor. Forming a first contact hole reaching a drain or a source of the semiconductor substrate by etching the first insulating film; embedding a connection wiring in the first contact hole; Forming an intermediate insulating film on the first insulating film so as to cover the connection wiring in the first contact hole; and forming a first electrode, a second electrode and these electrodes on the intermediate insulating film. Forming a charge storage capacitor having a sandwiched dielectric film; and forming a second insulating film on the intermediate insulating film so as to cover the charge storage capacitor. Forming a second contact hole reaching the connection wiring in the first contact hole by etching the second insulating film and the intermediate insulating film; and connecting wiring in the second contact hole. Burying a connection wiring in the first and second contact holes,
Forming a wiring for electrically connecting the drain or the source to the first electrode through the first contact hole and the second contact hole. A method for manufacturing a semiconductor memory device, comprising: a silicon nitride film formed by a CVD method; and a silicon nitride film formed by a plasma CVD method.