ITVA20060065A1 - MEMORY WITH THREE-LEVEL CELLS AND ITS MANAGEMENT METHOD. - Google Patents
MEMORY WITH THREE-LEVEL CELLS AND ITS MANAGEMENT METHOD.Info
- Publication number
- ITVA20060065A1 ITVA20060065A1 ITVA20060065A ITVA20060065A1 IT VA20060065 A1 ITVA20060065 A1 IT VA20060065A1 IT VA20060065 A ITVA20060065 A IT VA20060065A IT VA20060065 A1 ITVA20060065 A1 IT VA20060065A1
- Authority
- IT
- Italy
- Prior art keywords
- memory
- management method
- level cells
- cells
- level
- Prior art date
Links
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITVA20060065 ITVA20060065A1 (en) | 2006-11-03 | 2006-11-03 | MEMORY WITH THREE-LEVEL CELLS AND ITS MANAGEMENT METHOD. |
DE102007051192.4A DE102007051192B4 (en) | 2006-11-03 | 2007-10-25 | A memory device employing tri-level cells and associated method for managing |
US11/934,144 US7596023B2 (en) | 2006-11-03 | 2007-11-02 | Memory device employing three-level cells and related methods of managing |
CN 200710169601 CN101276645B (en) | 2006-11-03 | 2007-11-02 | Memory device employing three-level cells and related methods of managing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITVA20060065 ITVA20060065A1 (en) | 2006-11-03 | 2006-11-03 | MEMORY WITH THREE-LEVEL CELLS AND ITS MANAGEMENT METHOD. |
Publications (1)
Publication Number | Publication Date |
---|---|
ITVA20060065A1 true ITVA20060065A1 (en) | 2008-05-04 |
Family
ID=39995958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITVA20060065 ITVA20060065A1 (en) | 2006-11-03 | 2006-11-03 | MEMORY WITH THREE-LEVEL CELLS AND ITS MANAGEMENT METHOD. |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN101276645B (en) |
IT (1) | ITVA20060065A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101382931A (en) * | 2008-10-17 | 2009-03-11 | 劳英杰 | Interchange internal code for electronic, information and communication system and use thereof |
US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
US9275720B2 (en) * | 2010-12-30 | 2016-03-01 | Kandou Labs, S.A. | Differential vector storage for dynamic random access memory |
CN105378848B (en) * | 2013-04-24 | 2018-10-02 | 慧与发展有限责任合伙企业 | A kind of memory devices and a kind of method |
EP3672176B1 (en) | 2014-02-28 | 2022-05-11 | Kandou Labs, S.A. | Clock-embedded vector signaling codes |
US10467177B2 (en) | 2017-12-08 | 2019-11-05 | Kandou Labs, S.A. | High speed memory interface |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100666174B1 (en) * | 2005-04-27 | 2007-01-09 | 삼성전자주식회사 | Nonvolatile semiconductor memory device having three-level memory cells and operating method therefor |
-
2006
- 2006-11-03 IT ITVA20060065 patent/ITVA20060065A1/en unknown
-
2007
- 2007-11-02 CN CN 200710169601 patent/CN101276645B/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN101276645B (en) | 2013-03-06 |
CN101276645A (en) | 2008-10-01 |
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