ITTO20130712A1 - PROCEDURE FOR THE FORMATION OF LAYERS OF GRAPHENE, IN PARTICULAR MONO- AND MULTI-ATOMIC, AND RELATIVE SYSTEM OF FORMATION OF GRAFENE LAYERS - Google Patents

Description

DESCRIPTION of the industrial invention entitled:

"Process for the formation of graphene layers, in particular mono- and multi-atomic, and related system for the formation of graphene layers"

TEXT OF THE DESCRIPTION

Technical field

The present description relates to techniques for the formation of graphene layers, in particular mono- and multi-atomic, comprising depositing a layer of catalyst metal on a crystalline semiconductor substrate and depositing said graphene by decomposition of molecules containing carbon atoms, in particular by CVD (Chemical Vapor Deposition), on said catalyst metal layer.

The invention was developed paying particular attention to its possible application to the transfer of graphene layers on insulating substrates, in order to create electronic devices and sensors.

For the sake of simplicity of illustration, in the remainder of the present description an almost constant reference will be made to this possible field of application. It will also be appreciated that the scope of the invention is quite general and therefore not limited to this specific application context.

Various embodiments can be applied to the formation of graphene layers and to the formation of layers with defined devices in graphene.

Technological background

The term 'graphene' usually refers to a two-dimensional material composed of a monatomic layer of carbon atoms placed according to a hexagonal lattice. In general, however, the convention of defining graphene also applies to a set of several monoatomic layers up to five, while for a number of layers greater than five we speak of graphite, as the physical properties found are typical of the latter material.

The physical characteristics of graphene are many and extremely interesting, since this is a zero-gap conductor, where the dispersion relationship that binds the moment and energy of the charge carriers follows a linear law. This causes the motion of the electrons to follow Dirac's relativistic relation, where the velocity of the Fermi level vf is used instead of the speed of light

vf = c / 300 (1) where c indicates the speed of light.

As a consequence, the mobility of the charge carriers can reach values of the order of 10 <5> cm <2> / V s, thus opening up considerable application possibilities in the field of microelectronics and spintronics.

The high sensitivity of the graphene layers to any external perturbations and adsorbates on the surface make it a promising material for physical, chemical and biological sensors.

The exceptional optical transparency, combined with the superior transport properties, make graphene particularly attractive as a contact material for photovoltaic devices.

From this non-exhaustive list of the many applications of graphene emerges the need to obtain this material in a reproducible, controllable way, with methodologies compatible with microelectronic techniques, and possibly at low prices.

The most used technique for depositing graphene in recent times has been represented by mechanical exfoliation from graphite blocks using adhesive tape. This approach is limited in that it is neither reproducible and controllable, nor compatible with current microelectronics technology.

Another technique in use employs the sublimation of carbon atoms from silicon carbide substrates, SiC, obtained at temperatures from 1000 ° C to 2000 ° C, which offers greater guarantees of reproducibility, but is expensive due to the price of SiC. starting point, and not very compatible with the silicon technology, as there are no techniques for transferring the layer from the SiC substrate to a silicon one.

A less expensive technique and in principle applicable over large areas is represented by the decomposition of molecules containing carbon atoms (hydrocarbons and others) on layers of metals capable of acting as catalysts. This process requires a high degree of control, in order to deposit the desired number of layers, the use of a heat source, and the high quality of the metal layers, since the deposited graphene presents defects at the grain boundaries of the metal. below.

In this context, the choice of using metal sheets, such as copper sheets for example, allows the controlled deposition of graphene over large areas, but the transfer on insulating substrates is not immediate due to the high volume of copper that requires be chemically dissolved in order to free the graphene layer.

Much more effective, from this point of view, is the use of metal films deposited on substrates used for microelectronics, such as silicon, or GaAs, or others. In this case, the transfer takes place through the dissolution of small volumes of metal, as the thickness of these films almost never exceeds 1 mm. The metal film can be deposited with a good crystallographic orientation, since the coupling with the underlying crystalline substrate, for example silicon, sometimes allows an almost epitaxial growth. Finally, the crystallographic quality of the metal film allows the subsequent deposition of graphene with a reduced number of defects and grain boundaries.

In the case of copper, for example, it is known that Cu films with a surface orientation of the type <111> grow on silicon substrates oriented <110>, since the reticular steps at the interface between the two structures are close. Furthermore, the lattice pitch of graphene pairs very well with that of Cu <111>.

This technique of formation of graphene by deposition on metal films, which are in turn deposited on crystalline substrates, however, has some drawbacks.

The possibility of depositing graphene using temperatures higher than 650 ° C, necessary for a good crystallinity of the same on metal catalyst films deposited on crystalline silicon substrates is unfortunately precluded by the phenomenon of metal diffusion in the silicon at those temperatures. Such aspects of growth on metals are described for example in publication N. c. Bartelt and K. f. McCarty, «Graphene growth on metal surfaces», MRS Bulletin, vol. 37, n. 12, pp. 1158–1165, 2012.

This effect does not occur if a diffusion opaque layer, such as SiO2, is interleaved between the silicon and the catalyst metal. In this case, unfortunately, the metal grows without a defined crystallographic orientation, resulting in polycrystalline. The same occurs for graphene, with a high density of crystallographic defects, largely present near the grain boundaries of metal crystallites.

Figure 1 shows an example of a metal film support structure for the deposition of graphene, indicated as a whole with the numerical reference 10, obtained with this technique that uses metal films. Starting from the bottom, a crystalline silicon substrate 14 is provided, on which a layer of silicon oxide 13 has grown. A metallic layer 12 is then deposited on it, in the example shown a metallic layer of polycrystalline copper. Monatomic layers of graphene 11 are deposited on this layer 12.

A further drawback is associated with the subsequent transfer of graphene from the metal film support 10, which is necessary for its use in electronic devices. The underlying metal of the metal layer 12, in fact, is able to inject electrons into the graphene layers 11, displacing its Fermi level from its intrinsic position, namely the Dirac point. In other regions of the Energy-Moment space, the linear relationship between these two quantities is no longer verified, and the electronic properties of graphene degrade dramatically. Furthermore, to transfer the graphene onto other insulating substrates, as illustrated with reference to Figure 2, it is envisaged to proceed with the chemical dissolution of the metal layer 12 by means of a removal solution 22 in a bath 22, in order to obtain floatation of the flock. of graphene, which is collected by means of a target substrate 23. Generally, a layer of polymer 21 (for example poly-methyl-methacrylate) is deposited on the graphene 11, in order to strengthen it and avoid fractures during floating and collection. Despite this expedient, the process is scarcely repeatable and does not allow to establish a priori the area of the substrate where the graphene will be deposited. The polymer is then removed by solvents, as described for example in the publication by X. Li, Y. Zhu, W. Cai, M. Borysiak, B. Han, D. Chen, R. D. Piner, L. Colombo, and R. S. Ruoff , "Transfer of Large-Area Graphene Films for High-Performance Performance Transparent Conductive Electrodes", Nano Lett., Vol. 9, no. 12, pp.

4359-4363, Dec. 2009.

Finally, to make devices on the transferred graphene it is necessary to subject it to lithography, optical or electron beam processes, re-coating it with a sensitive polymer, and exposing it to UV radiation or an electron beam. These treatments have the further drawback of greatly reducing the electronic quality of graphene.

Purpose and summary

The embodiments described here have the purpose of improving the potential of the processes according to the known art as discussed above.

Various embodiments achieve this purpose thanks to a method having the characteristics referred to in the following claims. Various embodiments may also refer to corresponding graphene layer formation systems as well as refer to a graphene layer produced by means of said process, to a support structure for the deposition of a graphene layer by decomposition of molecules containing atoms of carbon, or to a graphene structure on support.

The claims form an integral part of the technical teachings administered herein in relation to the invention.

Brief description of the figures

Various embodiments will now be described, purely by way of example, with reference to the attached figures, in which:

- Figures 1 and 2 relating to the known art have already been described above and will not be further described below;

- Figure 3 represents a schematic detail view of a substrate prepared according to the process according to the invention, in the phase just after the deposition of graphene and just before the transfer phase; Figure 4 represents a schematic view of the transfer process;

- Figure 5 represents the final stage of the process according to the invention;

- Figure 6 shows a flowchart representative of further operations of the process according to the invention.

Detailed description

Numerous specific details are provided in the following description in order to allow maximum understanding of the exemplary embodiments. The embodiments can be put into practice with or without specific details, or with other processes, components, materials, etc. In other circumstances, well-known material structures or operations are not shown or described in detail to avoid overshadowing aspects of the embodiments. Reference throughout this description to "an embodiment" means that a particular feature, structure or feature described in connection with the embodiment is included in at least one embodiment. Thus, the occurrence of the phrase "in one embodiment" at various points throughout this description is not necessarily referring to the same embodiment. Furthermore, the particular features, structures or features can be combined in any convenient way in one or more embodiments.

The headings and references are provided herein for the convenience of the reader only and do not define the scope or meaning of the embodiments.

In order to obtain the crystalline layer supporting the deposition of the metal layer, the process according to the invention substantially provides for making layers of semiconductor material porous by applying an electrochemical process such as to create nanometric pores, preserving the original crystallographic orientation of the starting material .

According to a preferred embodiment of the invention, an electrochemical process is applied to p-type silicon substrates, oriented <110>, having resistivity of a few mΩ cm. In this way, the structure of the silicon filaments of the porous layer has a diameter of a few nanometers and preserves the orientation <110> of the starting material.

Figure 3 shows a metal film support structure for the deposition of graphene 30 obtained as part of the process according to the invention.

14 indicates the silicon substrate and 31 indicates an oxidized porous silicon layer, which has been obtained starting from a silicon wafer 40.

With reference to the flow chart of figure 6, as well as to figures 3-5 which show steps of the process according to the invention, this process in a more general embodiment substantially comprises:

- an operation 100 of applying an electrochemical process to a silicon substrate 40 to obtain a porous portion or layer therein;

- an operation 200 of depositing a film of highly oriented catalyst metal 32 on this porous portion obtained through the step 100;

- an operation 300 for lithographic removal of part of the metal corresponding to the highly oriented catalyst metal film 32. This operation can also be optional, since it serves to define the geometries on which the graphenic structures are deposited before depositing the layers graphenic. These geometries can be alternatively defined after the deposition of the graphene layer on the entire metal film;

- an oxidation operation 400 of the porous silicon layer to obtain the oxidized porous silicon layer 31;

- a graphene deposit operation 500 by CVD (Chemical Vapor Deposition) on the highly oriented catalyst metal film 32. If the lithographic removal operation 300 has been applied to the metal film 32, the graphene grows only at the structures metal left.

Following these operations, a mono-atomic layer or more mono-atomic, i.e. multiatomic, layers of graphene 11 are obtained, included in the metal film support structure for the deposit of graphene 30 of figure 3.

Additionally, graphene 11 can be transferred and thus the process additionally comprises:

- an operation 600 for transferring the graphene 11 onto a support structure 60, which, as shown in figure 5, comprises an insulating layer and possibly a second silicon substrate 35.

The operation 100 of applying an electrochemical process to a silicon substrate 40 to obtain a porous portion or layer therein includes for example the following steps:

- the crystalline silicon wafers 40 are initially heated to a temperature of 400 ° C in vacuum to allow the desorption of hydrogen from the surface, residue of the chemical polishing treatment and responsible for a porosity reduction effect during the subsequent electrochemical treatment;

- then, these wafers 40 are inserted in an electrochemical cell, with the lower face in contact with a metal electrode and the upper face exposed to a solution of HF (50% in H2O) diluted 1: 1 in ethanol. Under these conditions, following the electrolytic dissolution of the polarized material as anode, a dissolution rate r of the silicon can be predicted very accurately from the relation:

r = J Ar / [P (J) n (J) r e NA] (2)

where J indicates the electrolytic current density (in A / cm <2>), Ar indicates the relative atomic mass of Si (28.08 g / mol), r is the density of Si (2.33 g cm <-3>), NA is Avogadro's number.

Small deviations from the theoretical behavior are possible due to the resistivity value of the same.

It is planned to associate the operation of applying an electrochemical process 100, therefore a calibration procedure 110 of the system, measuring the porosity by gravimetric method. For this purpose, three weighing operations are required, the first of the wafer 40 before dissolution (produces a first mass value m1), the second after this (second mass value m2), and the third after the complete removal of the porous layer by immersion in an alkaline reagent (third mass value m3). The porosity value is therefore given by:

r = (m1-m2) / (m1-m3) (3) The thickness of the porous layer can be measured by profilometric measurement of the residual excavation following alkaline removal.

It is known, for example from the publication T. Lin, S. Chen, Y. Kao, K. Wang, and S. Iyer, "100-Mum-Wide Silicon-on-Insulator Structures by Si Molecular-Beam Epitaxy Growth on Porous Silicon », Appl. Phys. Lit., vol. 48, n. 26, pp.

1793–1795, June 1986, that a structure with nanometric pores and defined crystallographic orientation allows homo-epitaxial but also hetero-epitaxial growth, as the pores favor a periodically distributed relaxation of the stress caused by the different reticular steps. Therefore, having obtained starting from the wafer 40 a structure with a silicon substrate 33 and a porous silicon layer 31, having a thickness of a few mm, for example between 3 and 10 mm, typically 5 mm, it is therefore possible to proceed with the deposition 200 of the highly oriented catalyst metal film 32, in the example a copper film, with a thickness preferably above 300 nm with possible predeposition by Molecular Beam Epitaxy of some silicon monolayer, in order to reduce the size of the pores on the surface, or, alternatively, a treatment in hydrogen at a temperature of 1000 ° C to increase the mobility of the silicon atoms on the surface of the layer 31 which rearrange themselves in order to obtain the same result.

The next step of the process object of the present invention consists in a removal step 300 by lithographic way of part of the metal deposited in the layer 32, in order to uncover the porous surface of the underlying layer 31, or even to define the initial shape of the devices in graphene, directly on the metal layer 32 catalyst. This lithographic removal step 300 provides, in a per se known manner, to deposit a layer of polymer (the so-called 'resist') on the metal film 32. The surface of this catalyst metal layer 32 can be left covered by this deposited polymer for the lithographic process, or it is covered with a suitable polymeric protective film, for example PMMA, to avoid its oxidation during the subsequent phase.

This subsequent phase corresponds to the oxidation operation 400 of the porous silicon. The support 30 is immersed in an electrochemical cell 37 where there is an oxidizing solution 36, for example ammonium pentaborate in ethylene glycol and water, which, upon coming into contact with the porous portion 31, penetrates inside and oxidizes it completely. The volumic expansion associated with the growth of the oxide is compensated by the initial porosity of the layer 31, thus allowing to obtain a compact or low porosity oxide. The overlying metal layer 32, on the other hand, may undergo a slight oxidation at the interface with the porous silicon layer 31, but its surface is protected by the polymeric film referred to in the previous step. Since the oxidation process is carried out at room temperature, the crystallographic orientation of the metal layer is not changed by the conversion of Si into SiO2.

The support 30 is then subjected in operation 500 to a flow of molecules containing carbon at temperatures above 650 ° C in a vacuum chamber, according to a process known in the literature as CVD (Chemical Vapor Deposition), obtaining the deposition of one or more multiple monatomic layers of graphene, which make up layer 11 of graphene.

According to a main aspect of the present invention, therefore, in the preparation process of the support 30 it is possible to use crystallographically oriented metal layers, without the consequences of its diffusion in the silicon. This is due to the use of the porous silicon layer 31 which, while maintaining the crystallographic orientation, is easily convertible in a subsequent phase into compact oxide by electrochemical way at room temperature.

The graphene of superior crystallographic quality is therefore deposited in the surface regions covered by the layer 32 of catalyst metal, thus assuming the shape and dimensions of devices previously defined by lithography.

A graphene 11 transfer operation 600 is then performed. This transfer operation is carried out using a second support 38 of insulating material, or of material on the surface of which an insulating layer is deposited, possibly the same one used to allow adhesion between the two substrates. In an embodiment, a second silicon substrate 35 can be used on which an insulating layer 34b of Poly-Methyl-Methacrylate is deposited, distributing the material in liquid form on the substrate 35 placed at high rotation on a spinner, and evaporating the solvent by heating. The same procedure is repeated on the support 30, on which the graphene 31 is deposited, obtaining a corresponding insulating layer 34a, for example of Poly-Methyl-Methacrylate. Such layers 34a and 34b each have a thickness of about 1 mm, for example.

Consequently, the second substrate 35 and the support 30 are placed in contact and subjected to values of pressure and temperature, per se known, for example by P. Ramm, J. J.-Q. Lu, and M. M. V. Taklo, Handbook of Wafer Bonding. John Wiley & Sons, 2011, in order to achieve the glass transition of the two adhesion deposits, namely the insulating layers 34a and 34b, and to facilitate their bonding.

The gluing operation determines a sandwich assembly or structure 50 which comprises from top to bottom, the insulating support 38, i.e. in particular the second silicon substrate 35 and the insulating layer 34, the further insulating layer 34, the graphene layer 11, the metal layer 32, the oxidized porous silicon layer 31 and the first substrate 33.

Figure 4 shows an operation for the removal of the porous silicon from the sandwich 50, which involves the subsequent immersion of the sandwich 50, to obtain the chemical dissolution, in a bath 40 of HF diluted in H2O of the oxidized porous silicon layer 31.

Figure 5 shows a separate subsequent removal operation of the metal layer 32. It should be noted that it is possible to detach the oxidized porous silicon layer 31 also through the sole dissolution of the metal layer 32 which is interposed between the graphene 11 and the oxidized porous silicon layer 31, but this procedure is less repeatable than removing first the oxidized porous silicon layer 31 and then the metal layer 32. In the case shown in Figure 5, once removed from the sandwich structure 50 from the first substrate 33 by dissolving the oxidized porous silicon layer 31, the dissolution of the metal, for example Cu, is achieved using a solution to remove the metal 39, for example FeCl3, leaving the areas where the graphene 11 has been previously deposited on the insulating substrate destination 38.

Figure 5 shows in particular a final support structure 60, after the removal of the metal layer 32. This support structure comprises the second crystalline substrate 38 and an insulating layer, composed of two bonded insulating layers 34a and 34b, in particular layers of PMMA, on which the graphene layer 11 has remained attached, after the removal of the metal layer 32. In general, the second crystalline substrate is necessary to provide mechanical support to the two bonded insulating layers 34a and 34b. In any case, in variant forms of the invention the final support structure 60 can also be reduced, by removing the substrate 38, to only the insulating layer, for example of PMMA, which supports the graphene layer 11. This reduced structure, to obtain sufficient mechanical properties, it is used as the basic element of a multilayer of reduced structures, that is, multilayer comprising a plurality of stacked reduced structures, consisting of a respective insulating layer (comprising layers 34a and 34b) and layer of graphene 11. The result is thus insulating multilayer-graphene-insulating-graphene… until the desired thickness and / or mechanical properties are reached. This multilayer thus forms a conductive plastic material.

The support structure 60 therefore carries the graphene layer 11, possibly already structured or to be structured according to the application, and allows transport and installation where its use is required, for example in electronic devices or sensors.

As far as the inventors are aware, the graphene layer 11 is substantially monocrystalline, with a low degree of defectiveness, as demonstrated by Raman spectroscopy measurements that indicate the presence of the emission peak at 1345 cm <-1>, correlated to the presence of defects , having an intensity around a few percent with respect to the peak at 1580 cm <-1>, the intensity of which depends on the volume of the investigated material.

The removal operation of the metal layer 32 with solution to remove the metal 39 can be used to provide for the detachment of the structure, by directly inserting the sandwich 50 into it. In fact, by removing the metal layer 32, the porous silicon 31 and the first substrate 33 detach from the graphene layer 11. This operation is, however, generally less repeatable, essentially due to the fact that the solution 39 removes the metal layer in an uneven way, since the etching occurs laterally and therefore the capillarity phenomena prevent complete penetration of the solution. This phenomenon of capillarity is less important in the case of detachment pursued by removing the porous silicon oxide, as its thickness is chosen about 10 times higher than that of the copper film (5 mm instead of 500 nm).

Any subsequent transfer onto a new substrate may require repeating the procedure just described with reference to figures 4 and 5, using two layers, for example, of Spin-on-Glass, or Frit-Glass as adhesion means and dissolving the Poly-Methyl -Methacrylate with an organic solvent, thus bringing back the structures in graphene 11 on an oxidized silicon substrate. The devices can therefore be made with the standard technology of microelectronics and possibly put in communication with other traditional semiconductor devices made on the same target silicon wafer.

Therefore, the advantages of the invention are clear from what has been described.

The process according to the invention advantageously allows to operate without increases in volume and without changes in the crystallographic quality of the overlying metal.

The process according to the invention advantageously allows to obtain layers of graphene with high crystallographic quality and a reduced percentage of defects caused by the grain boundaries of the underlying catalyst metal layer.

Advantageously, the deposition of graphene can be carried out at temperatures above 650 ° C without causing the diffusion of the metal within the substrate and allows the deposition of the desired layer.

The graphene layer is advantageously protected and never exposed during the transfer process to aggressive chemical reagents that can affect its quality.

The process according to the invention advantageously allows to define graphene devices already on the substrate used for the formation, in order to avoid damage to the graphene itself, if exposed to radiation.

Naturally, the principle of the invention remaining the same, the details and embodiments can vary, even significantly, with respect to what is described here purely by way of example, without departing from the scope of protection. This scope of protection is defined by the attached claims.

The process for the formation of graphene layers according to the invention envisages preferably using crystalline silicon as the semiconductor to make porous, but it is not excluded that another semiconductor capable of being made porous, for example GaAs, may be used.

The graphene layer or graphene structure on support comprising an insulator layer, preferably, but not exclusively, as discussed above, on a crystalline semiconductor substrate and a mono-atomic or multi-atomic layer of graphene lend themselves to multiple applications. For example, an application consists of the possibility of integrating electronic devices in silicon with those in graphene, as in the field of spintronics, since the coherence length of the single spin is the highest measured so far. The graphene material produced and transferred to silicon according to the process according to the invention

it allows to associate, on a single chip, traditional devices based on charge transport with those based on spin transport, allowing the processing of a large amount of information. Graphene itself can be used more simply for the contact tracks of devices in place of copper, which has known electromigration problems, which are one of the main causes of failures in integrated electronics. Graphene, given its properties of very high optical transparency, associated with a high conductivity, can be deposited on photovoltaic cells, in silicon or other material, as a contact exposed to solar radiation, or in touchscreen screens. Other applications, which always exploit integration with silicon electronics, concern the field of sensors, according to a Lab-on-Chip approach, where the sensor element, or an array of different sensors (physical, chemical and biological), it is integrated with the process electronics.

Claims (13)

CLAIMS 1. Process for the formation of layers, in particular mono- or multi-atomic, of graphene, comprising of deposit (200) a catalyst metal layer on a crystalline semiconductor substrate (14; 33), and deposit (400) said graphene (11) by decomposition of molecules containing carbon atoms, in particular by Chemical Vapor Deposition (CVD), on said catalyst metal layer (12; 32), characterized in that includes the following operations: - prepare (100) a first crystalline semiconductor substrate (33) comprising a porous layer (31) which comprises a structure of wires and pores of nanometric size which have the crystallographic orientation of said first crystalline semiconductor substrate (33) - perform said operation of depositing (200) a layer of catalyst metal by growing said catalyst metal layer (32), in particular in an epitaxial manner, following the orientation of said porous portion (31) of the first substrate (33); - converting (500) said porous semiconductor layer (31), in particular converting entirely, into oxide, in particular by means of oxidation techniques in liquid. 2. Process according to claim 1, characterized in that said operation of preparing (100) a first crystalline semiconductor substrate (33) comprising a porous layer (31) comprises carrying out an electrochemical etching step on a wafer of semiconductor material (40 ), placing said wafer of semiconductor material (40) in contact with an electrolyte and imposing the passage in said wafer of semiconductor material (40) of an electric current, to obtain a structure of wires and pores of nanometric size while maintaining the orientation crystallography of said wafer of semiconductor material (40). 3. Process according to claim 1, characterized in that the deposition of graphene (11) is carried out at temperatures higher than 650 ° C. 4. Process according to claim 1, characterized in that it comprises, before said operation of converting (500) said porous semiconductor layer (31) into oxide, a removal operation (300), in particular by lithographic method, of part of the catalyst metal layer (34). 5. Process according to the preceding claims, characterized in that said removal operation (300), in particular by lithographic method, of part of the catalyst metal layer (34) comprises operations for defining graphene devices, in order to avoid the damage to graphene itself from radiation exposure. 6. Process according to one or more of the preceding claims, characterized in that it comprises a transfer operation (600) of the graphene layer (11) onto a further electrically insulating substrate (38), in particular using hot and under adhesion pressure of two layers of polymeric material or glass material. 7. Process according to claim 6, characterized in that said transfer operation (600) comprises chemically removing said oxide layer (31), allowing the separation of the graphene layer (11) from the first substrate (33). 8. Process according to claim 7, characterized in that said transfer operation (600) further comprises chemically removing (39) said metal layer (32). 9. System for the formation of layers, in particular mono- or multi-atomic, of graphene, comprising means for implementing the operations of the process according to one of claims 1 to 8. 10. Support structure for the deposition of a graphene layer by decomposition of molecules containing carbon atoms, comprising a crystalline semiconductor substrate (33), a porous semiconductor layer (31) above said substrate (31), a catalyst metal layer (32) deposited on top of said porous layer (31), said graphene layer being deposited on top of said metal layer (32). 11. Structure of graphene on support comprising an insulating layer (34a, 34b), in particular a PMMA layer, in particular deposited on a crystalline semiconductor substrate (38), and a mono-atomic or multi-atomic layer of graphene . 12. Graphene structure on support according to claim 11, characterized in that it is comprised in a multilayer of said graphene and insulating structures, in particular of PMMA layer. 13. Graphene layer produced according to the process of one or more of claims 1 to 8.