ITMO20120317A1 - SYSTEM AND METHOD FOR DIGITAL PREDISTORS IN POWER AMPLIFIERS, PARTICULARLY FOR RADIOFREQUENCY COMMUNICATIONS - Google Patents

Description

“SYSTEM AND METHOD FOR DIGITAL PREDISTORTION IN POWER AMPLIFIERS, ESPECIALLY FOR RADIO FREQUENCY COMMUNICATIONS”.

DESCRIPTION

The present invention relates to a system and a method for digital predistortion in power amplifiers, which can be used in particular for radio frequency communications.

In telecommunications, particularly in cellular mobile telephony, the use of power amplifiers is known and common.

It is also known that the current standards defined in the field of mobile communication consider the linearity and efficiency of a power amplifier as fundamental technical characteristics, which must be taken into account in order to meet the requirements regarding intermodulation disturbances and spurious emissions.

Therefore, in order to obtain high linearity and efficiency power amplifiers, the use of digital predistortion techniques, known by the acronym DPD (Digital Pre-Distortion), is widespread.

These DPD techniques involve the use of a predistortion circuit that allows to obtain a high linearity of operation of the power amplifiers. Typically the DPD technique is flanked by the adaptive correction technique of the predistortion coefficients to optimize operation.

In practice, the adaptive correction technique uses a sampling of the output signal from the power amplifier to calculate the error vectors, obtained by comparing the sampling of the output signal with the appropriately delayed input signal, and to generate suitable correction coefficients. of the DPD circuit, which are used to ensure the effectiveness of the digital predistortion of the input signal thus allowing to obtain the maximum linearity of the power amplifier. Figure 1 illustrates, by way of example, a general block diagram of a digital predistortion system of a known type, indicated as a whole with the reference S.

The system S comprises an amplification line AL, suitable for amplifying the digital input signal SDIN, in order to generate an output signal

Analog SOUT to be retransmitted.

In particular, the amplification line AL comprises a digital predistortion unit U, consisting for example of a FPGA (Field Programmable Gate Array) circuit programmed to perform the digital predistortion of the digital input signal SDIN by means of a digital predistortion functional block DPD all inside which an adaptive algorithm operates.

The system S also comprises a digital-to-analog converter DAC, arranged downstream of the digital predistortion unit U and adapted to convert the digital input signal and predistorted SDÌN into a predistorted analog input signal SAIN at intermediate frequency.

Downstream of the DAC converter there may be a first intermediate frequency filter, indicated in the figure with the reference F, a first analog multiplier (mixer) MIX1, and a radio frequency filter, indicated in the figure with the reference FRF.

The first analog multiplier MIX1 brings the frequency of the SAIN analog signal up to radio frequencies.

In particular, the first analog multiplier MIX1 accepts in input the analog signal SAINa intermediate frequency, filtered by means of the first filter FIF1, and a signal coming from a local oscillator LO and returns, in output, the corresponding analogue signal SAIN at radio frequency.

The system S further comprises an amplifier AMP adapted to amplify the analog signal SAIN SO as to generate the output signal S0ut to be transmitted.

A directional coupler C then allows the connection of the AMP amplifier to the appropriate antenna for the transmission of the SOUT output signal and also allows the interception of the output signal S0UT to bring it back to an FP feedback branch.

Furthermore, on the feedback branch FP, a second analog multiplier MIX2 and a second intermediate frequency filter are present in sequence, indicated in the figure with the reference F.

In particular, the second analog multiplier MIX2 accepts the S0UTa radiofrequency output signal and the signal from the local oscillator LO as input and reports, at the output, the corresponding output signal SOUTa intermediate frequency.

Subsequently, always on the feedback branch FP there is an analog-digital converter ADC adapted to convert the output signal SOUTa intermediate frequency into a corresponding digital reference signal SR.

In practice, the reference signal SR is the digital signal corresponding to the output signal SOUT, and therefore includes all the intermodulation disturbances and spurious emissions generated by the amplification line L.

The DPD circuit then makes a comparison between the reference signal SR and the corresponding digital input signal SDIN, in order to determine the appropriate predistortion coefficients that can be used by the DPD digital predistortion algorithm.

However, known DPD systems have some drawbacks.

In particular, the bandwidth of the ADC analog-to-digital converter must necessarily be three to five times wider than the operating band.

For example, with an operating band of 75Mhz, the bandwidth of the ADC converter must necessarily be 375MHz, with a sampling frequency of at least 800MHz.

This inevitably involves the use of considerably high cost ADC converters.

Another limitation is given by the fact that in the digital predistortion systems of the known type, ADC converters with a high resolution between 12 and 14 bits must necessarily be used, in order to obtain a dynamics such as to reduce the distortion introduced by the amplifier with respect to the distortion of the ADC converter.

In particular, the precision of intermodulation suppression is particularly relevant in the presence of low-amplitude intermodulation, when the difference between the signal and the intermodulation itself is greater than 70dBc.

Therefore, even the need for a high resolution for the analog-to-digital conversion of the amplified signal involves the use of considerably high cost ADC converters.

The main task of the present invention is to devise a system and a method for digital predistortion in power amplifiers, particularly for radio frequency communications, which guarantee correct signal amplification, while maintaining high linearity and efficiency, and which allow, at the same time, a reduced bandwidth and resolution of the analog-to-digital converter with respect to known digital predistortion systems and techniques.

Another object of the present invention is to devise a system and a method for digital predistortion in power amplifiers, particularly for radio frequency communications, which allow to overcome the aforementioned drawbacks of the prior art in the context of a simple, rational solution of easy and effective use and low cost.

The above purposes are achieved by the present system for digital predistortion in power amplifiers, particularly for radio frequency communications, comprising:

at least one digital predistortion unit of a digital input signal as a function of a digital reference signal, to generate a predistorted digital input signal;

at least a first digital-to-analog converter arranged downstream of said digital predistortion unit and adapted to convert said predistorted digital input signal into a predistorted analog input signal;

at least one amplifier arranged downstream of said first digital-to-analog converter and adapted to amplify said predistorted analog input signal to generate an output signal;

characterized in that it includes:

at least a second digital-to-analog converter connected to said digital predistortion unit and adapted to convert said digital input signal into an analog input signal;

at least one summing circuit connected to said second digital-to-analog converter and to said amplifier and adapted to subtract said analog input signal from said output signal to obtain an intermodulation signal;

at least one analog-to-digital converter connected downstream of said summing circuit and upstream of said digital predistortion unit, adapted to convert said intermodulation signal to obtain said reference signal.

The objects set out above are also achieved by the present method for digital predistortion in power amplifiers, particularly for radio frequency communications, comprising:

at least one digital predistortion step of a digital input signal as a function of a digital reference signal, to generate a predistorted digital input signal;

at least a first digital-to-analog conversion step of said predistorted digital input signal into a predistorted analog input signal;

at least one amplification step of said predistorted analog input signal for generating an output signal;

characterized in that it includes:

at least a second digital-to-analog conversion step of said digital input signal into an analog input signal; at least one step of subtracting said analog input signal from said output signal to obtain an intermodulation signal; at least one analog-to-digital conversion step of said intermodulation signal to obtain said reference signal.

Other characteristics and advantages of the present invention will become more evident from the description of preferred, but not exclusive, embodiments of a system and a method, illustrated by way of indication, but not of limitation, in the accompanying drawings in which:

Figure 2 illustrates a general block diagram of a possible first embodiment of the system according to the invention;

Figure 3 is a graph illustrating the amplified and intercepted output signal from the feedback branch of the system according to the invention;

Figure 4 is a graph illustrating the intermodulation signal at the output of the adder of the system according to the invention;

Figure 5 illustrates a general block diagram of a possible first embodiment of the digital predistortion unit of the system according to the invention;

Figure 6 illustrates a general block diagram of a possible second embodiment of the digital predistorting unit of the system according to the invention;

Figure 7 illustrates a general block diagram of a possible second embodiment of the system according to the invention;

Figure 8 illustrates a general block diagram of a possible third embodiment of the system according to the invention;

Figure 9 illustrates a general block diagram of a possible fourth embodiment of the system according to the invention;

Figure 10 illustrates a general block diagram of a possible fifth embodiment of the system according to the invention.

With particular reference to these figures, the numeral S globally indicates a digital predistortion system in power amplifiers used for radio frequency communications.

The S system can be used in telecommunications, in particular in cellular mobile telephony, and can be implemented within radiofrequency repeaters designed to extend the coverage area normally guaranteed by a conventional radio cell.

Figure 2 illustrates, by way of example, a general block diagram of a first possible embodiment of the S system.

The system S comprises an amplification line, indicated as a whole with the reference AL, suitable for amplifying a digital input signal SDIN, received from input I, in order to generate an analog output signal S0UT to be sent on output O for subsequent retransmission.

The AL amplification line includes a digital predistortion unit U, consisting for example of an FPGA (Field Programmable Gate Array) circuit programmed to perform the digital predistortion of the digital SDIN input signal ·

In particular, the digital predistortion of the digital input signal SDIN is carried out by means of a suitable predistortion circuit DPD, as a function of a digital SR reference signal, in order to generate a predistorted digital input signal SDIN.

The AL amplification line also includes a first digital-to-analog converter DAC1, arranged downstream of the digital predistortion unit U and adapted to convert the digital input signal and predistorted

SDINa pre-distorted SAIN intermediate frequency analog input signal.

Downstream of the first digital-analog converter DAC1 there are a first intermediate frequency filter, indicated in the figure with the reference FIF1, a first analog multiplier (mixer) MIX1, and a radio frequency filter, indicated in the figure with the reference Frf.

The first analog multiplier MIX1 raises the frequency of the SAIN analog signal up to radio frequencies.

In particular, the first analog multiplier MIX1 accepts as input the predistorted intermediate frequency SAIN analog input signal, filtered by the first intermediate frequency filter FIF1, and a signal coming from a local oscillator LO and outputs the corresponding analog signal. radio frequency SAIN pre-distorted input.

The system S also comprises an amplifier AMP arranged downstream of the FRFed filter adapted to amplify the radio frequency analog input signal SAIN, so as to generate the analog output signal S0UT to be transmitted.

A directional coupler C then allows the connection of the amplifier AMP to the appropriate circuit for the transmission of the output signal S0UT and also allows to intercept the output signal

SOUT to bring it back to an FP feedback branch.

Furthermore, on the feedback branch FP, a second analog multiplier MIX2 and a second intermediate frequency filter are present in sequence, indicated in the figure with the reference F ^.

In particular, the second analog multiplier MIX2 accepts the radio frequency SOUT output signal and the signal coming from the local oscillator LO at the input and reports, at the output, the corresponding output signal SOUT at intermediate frequency.

Advantageously, the system S comprises a second digital-to-analog converter DAC2 connected to the digital predistortion unit U and adapted to convert the digital input signal S ^ into a corresponding analog input signal SAIN ·

The feedback branch FP further comprises an adder circuit ADR arranged downstream of the second intermediate frequency filter F and connected to the second digital-to-analog converter DAC2.

This adder circuit ADR can be applied with the same principle to a feedback branch FP in the base band.

In this case, the circuit is no longer realized at intermediate frequency, but by means of a zero-IF demodulation technique.

In particular, the adder circuit ADR is adapted to subtract the analog input signal SAIN from the output signal S0uTa intermediate frequency (or in baseband), in order to obtain an intermodulation signal SIMD-II feedback branch FP further comprises a ADC analog-to-digital converter connected downstream of the ADR summing circuit and upstream of the digital predistortion unit U.

In particular, the ADC analog-to-digital converter is adapted to convert the intermodulation signal SIMD to the output of the ADR adder to obtain the corresponding digital reference signal SR to be sent to the digital predistortion unit U.

In particular, thanks to the ADR adder, the useful signal, corresponding to the analog input signal SAIN, is canceled by the output signal S0UT, amplified and intercepted by the feedback branch FP, before the analog-digital conversion carried out by the analog-digital converter ADC .

In this way, while ensuring the same precision compared to known digital predistortion systems in detecting intermodulation, it is possible to use a lower resolution ADC analog-digital converter (which uses a lower number of bits required).

In fact, as shown in Figure 3, the output signal S0UT amplified and intercepted by the feedback branch FP includes both the useful signal and the intermodulation disturbances and spurious emissions.

Instead, as shown in Figure 4, the intermodulation signal SIMD at the output of the adder D mainly depends on the intermodulation disturbances and the spurious emissions.

Therefore, by reducing the level of the analog signal within the passband, a lower resolution and low-cost ADC analog-to-digital converter can be used, significantly reducing the overall costs of the S system.

In particular, the resolution of the analog-to-digital converter ADC can be reduced by 1dB for every 6dB of signal canceled by the adder D.

As shown schematically in Figure 5, after the analog-to-digital conversion, the digital input signal SDIN is added again to the reference signal SR and the digital predistortion circuit DPD operates on the digital input signal SDIN to limit the level of intermodulation spurious, in order to to obtain a high linearity of the power amplifier.

In particular, the digital predistortion circuit DPD is connected to input I and is arranged downstream with respect to the analog-to-digital converter ADC and upstream from the first digital-to-analog converter DAC1, and the digital predistortion unit U comprises an additional adder connected ADR to input I, to the ADC analog-to-digital converter and to the DPD digital predistortion circuit.

The additional adder ADR is adapted to add the digital input signal SDIN to the reference signal SR and the signal thus summed is sent to the digital predistortion circuit DPD.

Conveniently, the digital predistortion unit U comprises a digital delay line DDL arranged downstream of the input I and upstream of the second digital-analog converter DAC2 and of the additional adder ADR '.

In particular, the delay line DDL is adapted to delay in time the digital input signal SDIN so as to align it with the reference signal SR coming from the feedback branch FP.

Usefully, the digital predistortion unit U comprises a regulation circuit R arranged downstream of the delay line DDL, arranged upstream of the second digital-to-analog converter DAC2 and connected to the analog-to-digital converter ADC.

In particular, the regulation circuit R is adapted to adjust the amplitude and / or phase of the digital input signal SDIN so as to make them substantially conform to the amplitude and / or phase of the signal entering the ADR in order to have maximum cancellation of the FP signal.

In practice, the regulation loop R balances and compensates the amplitude and phase of the digital input signal SDIN so as to make the reference signal SR free of the content of the SDIN signal - For example, the regulation loop R can be implemented using an adaptive FIR digital filter.

Conveniently, as illustrated in Figure 6, in an alternative embodiment the digital predistortion unit could be without the additional adder ADR '.

In this case, the DPD digital predistortion circuit makes a comparison between the digital input signal SDIN and the reference signal SR.

Figure 7 illustrates, by way of example, a second embodiment of the system S according to the invention.

In particular, according to this second embodiment, the adder ADR is arranged upstream with respect to the second filter FIF2 and the system S comprises a third filter FIF3 and third analog multiplier MDG arranged downstream of the second digital-analog converter DAC2.

The third analog multiplier MDG accepts as input the SAIN intermediate frequency analogue input signal, filtered by the third FIF3 filter, and the signal coming from the oscillator LO and outputs the corresponding SAIN radio frequency analogue input signal.

Conveniently, with reference to a third embodiment illustrated in Figure 8, the system S can comprise at least one variable attenuator ATN arranged upstream with respect to the analog-digital converter ADC and downstream with respect to the adder ADR.

The variable attenuator ATN is able to be activated for a predetermined period of time during a preliminary start-up phase of the S system. Thus, during the preliminary phase, when the difference between the useful signal and the intermodulation spurious is minimal, signal attenuation (for example equal to 10dB) introduced by means of the variable attenuator ATN allows to reduce the amplitude of the signal on the feedback branch FP.

In particular, the attenuation of the signal is carried out after the cancellation of a portion of the amplified S0U output signal, carried out by means of the ADR adder, so as to further reduce the width of the operating band of the ADC analog-digital converter during the preliminary start-up phase. of the S.

Therefore, the resolution of the analog-to-digital converter ADC required during the preliminary phase is the same as required after this preliminary phase, during normal operation of the S system, when the intermodulation level is lower.

Intact, after the preliminary phase, the DPD digital predistortion circuit reduced the level of intermodulation spurious.

In this way it is possible to maintain a low resolution of the ADC analog-digital converter during the whole normal operation of the S system. After the preliminary phase, the attenuation can be removed, and therefore the variable attenuator ATN can be deactivated, so as to increase the channel response level, obtaining a more accurate cancellation of intermodulation spurious by means of the DPD digital predistortion circuit. As illustrated in Figure 9, the system S can comprise a detection circuit DET arranged upstream of the analog-to-digital converter (ADC) and downstream of the variable attenuator ATN, adapted to operate the variable attenuator ATN in the event that saturation is detected. of the ADC analog-to-digital converter.

Figure 10 illustrates, by way of example, a further embodiment of the system S according to the invention.

In particular, according to this embodiment, the variable attenuator ATN is arranged upstream with respect to the second analog multiplier MIX2 and downstream with respect to the adder ADR. Furthermore, the system S comprises a third intermediate frequency filter Fif3 and a third analog multiplier MIX3 arranged downstream of the second digital-to-analog converter DAC2. The third analog multiplier MIX3 accepts in input the analogue input signal SAINa intermediate frequency, filtered by the third filter FIF3, and the signal coming from the oscillator LO and returns, in output, the corresponding analogue input signal SAINa radiofrequency.

The method according to the invention provides:

at least one digital predistortion step of the digital input signal SDIN as a function of the reference signal SRdigitale, to generate the predistorted digital input signal SDIN;

at least a first digital-to-analog conversion step of the predistorted digital input signal SDIN into the predistorted analog input signal SAIN;

at least one amplification step of the SAIN predistorted analog input signal to generate the output signal S0UT

Advantageously, the method according to the invention comprises:

at least a second digital-to-analog conversion step of the SDIN input digital signal into the SAIN analog input signal, '

at least one step for subtracting the analog input signal SAIN from the output signal SOUT to obtain the intermodulation signal

SMD;

at least one analog-to-digital conversion step of the intermodulation signal SIMD to obtain the reference signal SR.

In particular, the method can predict the sum of the digital input signal SDIN to the reference signal SR, prior to the digital predistortion step.

Usefully, the method provides the step of delaying the digital input signal SDIN before the analog-digital conversion and before the subtraction of the analog input signal SAIN from the output signal S0UT.

Usefully, the method can provide for the adjustment of the amplitude and / or phase of the digital input signal SDIN so as to substantially conform to the amplitude and / or phase of the ADR input signal so as to render the reference signal SR devoid of SDIN-content Advantageously, the method can further comprise Γ attenuation of the intermodulation signal SIMD for a predetermined period of time, during a preliminary start-up phase of the S system.

In particular, the detection of the intermodulation signal SIM can be carried out from the input of the ADC analog-digital converter, prior to the analog-digital conversion step, and the attenuation can be carried out in the event that an amplitude of the signal is detected. SIMD intermodulation higher than a predefined threshold value.

In practice it has been found that the described invention achieves the intended aim and objects.

In particular, it is emphasized that the system and the method according to the invention guarantee a correct amplification of the signal, maintaining a high linearity and efficiency, and at the same time allow a reduced bandwidth and resolution of the analog-digital converter. compared to known digital predistortion systems and techniques. Therefore, the system and the method according to the invention allow the realization of a simple, rational solution, easy and effective to use and with a considerably low cost.

Claims (12)

CLAIMS 1) System (S) for digital predistortion in power amplifiers, particularly for radio frequency communications, comprising: at least one digital predistortion unit (U) of a digital input signal (SDIN) as a finishing of a digital reference signal (SR), to generate a predistorted digital input signal (SDIN); at least a first digital-to-analog converter (DAC1) arranged downstream of said digital predistortion unit (U) and adapted to convert said predistorted digital input signal (SDIN) into a predistorted analog input signal (SAIN); at least one amplifier (AMP) arranged downstream of said first digital-to-analog converter (DAC1) and adapted to amplify said predistorted analog input signal (SAIN) to generate an output signal (Sour) j characterized in that it includes: at least a second digital-to-analog converter (DAC2) connected to said digital predistortion unit (U) and adapted to convert said digital input signal (SDIN) into an analog input signal (SAIN); at least one summing circuit (ADR) connected to said second digital-to-analog converter (DAC2) and to said amplifier (AMP) and adapted to subtract said analog input signal (SA) from said output signal (S0UT) to obtain a intermodulation (SIMD); at least one analog-to-digital converter (ADC) connected downstream of said adder circuit (ADR) and upstream of said digital predistortion unit (U), adapted to convert said intermodulation signal (SMD) to obtain said reference signal (SR ). 2) System (S) according to claim 1, characterized in that said digital predistortion unit (U) comprises at least one input (I) of said digital input signal (SDIN), and at least one digital predistortion circuit (DPD) arranged downstream of said input (I) and of said analog-to-digital converter (ADC) and upstream of said first digital-to-analog converter (DAC1). 3) System (S) according to one or more of the preceding claims, characterized in that said digital predistortion unit (U) comprises at least one additional adder (ADR ') connected to said input (I), arranged downstream of said analog converter -digital (ADC) and arranged upstream of said digital predistortion circuit (DPD), able to add said digital input signal (SDIN) to said reference signal (SR). 4) System (S) according to one or more of the preceding claims, characterized in that said digital predistortion unit (U) comprises at least one digital delay line (DDL) arranged downstream of said input (I) and upstream of said second digital-to-analog converter (DAC2). 5) System (S) according to one or more of the preceding claims, characterized in that said digital predistortion unit (U) comprises at least one digital delay line (DDL) arranged downstream of said input (I) and upstream of said additional adder (ADR '). 6) System (S) according to one or more of the preceding claims, characterized in that it comprises at least one regulation circuit (R) arranged downstream of said input (I), arranged upstream of said second digital-analog converter (DAC2) and connected to said analog-to-digital converter (ADC), adapted to adjust the amplitude and / or phase of said digital input signal (SDIN) so as to substantially render the reference signal (SR) devoid of SDIN content. 7) System (S) according to one or more of the preceding claims, characterized in that it comprises at least one variable attenuator (ATN) arranged upstream of said analog-digital converter (ADC) and downstream of said adder (ADR), said attenuator variable (ATN) being able to be activated for a predetermined period of time, during a preliminary start-up phase of said system (S). 8) System (S) according to claim 7, characterized by the fact that it comprises at least one detection circuit (DET) arranged upstream of said analog-digital converter (ADC) and operatively connected to said variable attenuator (ATN), able to actuate said variable attenuator (ATN) in case of detection of a saturation of said analog-digital converter (ADC). 9) Method for digital predistortion in power amplifiers, particularly for radio frequency communications, comprising: at least one digital predistortion step of a digital input signal (SDIN) as a function of a digital reference signal (SR), to generate a predistorted digital input signal (SDIN); at least a first digital-to-analog conversion step of said predistorted digital input signal (SDIN) into a predistorted analog input signal (SAIN); at least one amplification step of said predistorted analog input signal (SAIN) to generate an output signal (S0UT); characterized in that it includes: at least a second digital-to-analog conversion step of said digital input signal (SDIN) into an analog input signal (SAIN); - at least one step of subtracting said analog input signal (SA) from said output signal (S0ut) to obtain an intermodulation signal (SIMD); at least one analog-digital conversion step of said intermodulation signal (SIMD) to obtain said reference signal (SR). 10) Method according to claim 9, characterized in that it comprises at least one step of adding said digital input signal (SDIN) to said reference signal (SR), before said digital predistortion step. 11) Method according to one or more of claims 9 and 10, characterized in that it comprises at least one step of delaying said digital input signal (SDIN) prior to said second analog-digital conversion step and / or preliminary to said step of subtracting . 12) Method according to one or more of claims from 9 to 11, characterized in that it comprises at least one step of adjusting the amplitude and / or the phase of said digital input signal (SDIN) so as to make the reference signal ( SR) devoid of SDIN content13) Method according to one or more of claims 9 to 12, characterized in that it comprises at least one step of attenuating said intermodulation signal (SIMD) for a predetermined period of time, during a preliminary start-up phase . 14) Method according to claim 13, characterized in that it comprises at least one step of detecting said intermodulation signal (SMD), prior to said analog-digital conversion step, said attenuating step being carried out in case of detection of a amplitude of said intermodulation signal (SIMD) greater than a predefined threshold value.