ITMI940917A1 - DC / DC CONVERTER INCLUDING A HIGH INSULATION CHARGE TRANSFER FEEDBACK NETWORK - Google Patents

Description

DESCRIPTION

The present invention relates to the field of DC / DC converters and more precisely to a DC / DC converter comprising a highly insulated charge transfer feedback network.

The operating principles of DC / DC converters have been known for some time, as well as the numerous circuit configurations that are based on these principles. An exhaustive discussion of the subject is given, for example, in the volume by LLoyd Dixon Jr, entitled: Switching Power Supply Topology Review; published by UNITRODE CORPORATION, following the Power Supply Design Seminar, held in Lexinghton (USA) in 1985.

The design of a DC / DC converter is nowadays greatly facilitated by the fact that specific integrated circuits are commonly available which are able to perform all the main functions for governing the converter itself. Said circuits essentially comprise: a) a presettable frequency oscillator, from which the wave forms useful for driving the electronic switches are obtained; b) a generator of a constant reference voltage, made stable in temperature; c) an operational amplifier that makes the difference between the constant reference voltage and the voltage on the load, obtaining an error signal; d) a feedback network which, on the basis of the error signal, produces a modulation of the duration of the oscillator pulses, stabilizing the voltage on the load.

Often for safety reasons, both for people and for the equipment powered by the DC / DC converter, galvanic isolation is also required between the primary power source of the converter and the user load; a transformer is almost always used for this purpose. However, the transformer alone is not sufficient to guarantee galvanic isolation, since a direct way of connection between the primary and secondary side circuits could be provided through the feedback network. It is therefore necessary to use suitable measures in the feedback network in order to preserve the above insulation.

A first known solution uses an auxiliary primary winding on the transformer connected to a rectifier bridge and to a low pass filter. At the output of the filter there is a direct voltage whose level varies proportionally to the secondary voltage, therefore it can be used for the generation of the error signal. The major drawback of this first solution is that if the direct junction voltage of the diodes that rectify the secondary current varies, or that across any components in series with the load, the voltage on the load also varies without the feedback network revealing this. variation, as it is sensitive only to the sum of said voltages.

A second known solution uses an optocoupler to transfer the error voltage towards the remaining feedback network. The major drawback of this second solution is due to the fact that the optocoupler introduces a low frequency pole in the closed loop response, linked to the low operating speed of these components, typically less than 10 KHz. For the known stability criteria, it is advisable to have a trend of the frequency response of the converter loop gain, similar to that of a single pole function. It is therefore necessary to neutralize the pole introduced by the optoisolator by introducing a dominant zero network into the feedback loop, however this is difficult to implement due to the following causes: a) the wide variability of the physical parameters found in the production batches of the optocouplers; b) the strong dependence on the temperature of the frequency of the pole of the optocouplers.

A practical way to compensate for the variability referred to in point a) is to generate the error signal upstream of the optocoupler, thus forcing the feedback loop to perform said compensation automatically. In doing so, however, it is no longer possible to use the differential comparator and the generator of the reference voltage inside the integrated circuit that controls the converter, it is therefore necessary to use further electronic components. Contrary to what happens for point a), it is difficult to compensate for the thermal effects mentioned in point b), in any case the compensation introduced is only partial and not repetitive.

The fundamental problem solved by the optocoupler, and which in any case must be solved by any device or circuit that replaces it, is that of transferring a slowly variable voltage between two decoupled points, such as the error voltage.

A circuit which "in the first analysis" could solve the same problem is described in the international patent application PCT No. WO-A-86/01653. In reality, the document describes and claims two different circuits, of which a first is called "Capacitive voltage transformer" (see attached Fig. 4), and a second, closer to a charge transfer network used in the invention in object, is a "decoupler stage" used to separate the user equipment from the main AC power supply lines, or from a direct voltage (see fig.2). The aforesaid separation is carried out by a switching circuit comprising two double electronic switches which work in phase opposition between the input and output points. They are controlled by a square wave frequency generator, which can be obtained by squaring the waveform of the alternating voltage on the main lines. In the description it is also stated that the aforementioned alternating voltage has a period of 50 or 60 Hz, and that an optocoupler is optionally used to control the electronic switches.

The teaching of the Italian patent could induce the person skilled in the art, moved by the intention of removing the drawbacks caused by the optocoupler in the feedback network of a DC / DC converter, to take into due consideration the hypothesis of replacing the optocoupler with the decoupler stage, as it results from the description. However, this would involve two major drawbacks that would make a mere replacement impossible. A first drawback would be that of the lack of galvanic isolation, and a second that of the inadequacy of the error signal that would be generated. The first drawback could be remedied as suggested in the text, ie by using at least one optocoupler to control the electronic switches. This would however reintroduce the aforementioned drawbacks which were intended to be removed, substantially attributable to the neutralization of a low frequency pole and its temperature compensation. In this case the pole in the loop gain would be caused by the fact that a change in the voltage on the load faster than the switching time of the optocoupler would be felt only partially, or not felt at all.

As for the reintroduction of the optoisolator, it is not to be considered as a possible possibility, but as an essential requirement to obtain the isolation between the two points to be decoupled. In fact, wanting to realize the square wave generator Gf (indicated only schematically in fig. 2) it is necessary to have a squaring circuit followed by an inverter, inevitably connected to the main lines, after which the two double switches would be respectively controlled by the true waveform or denied. In the absence of an optocoupler, it is necessary to have a common reference point for the potentials on the control electrodes of the transistors that make up the two double electronic switches, thus losing the galvanic isolation between them. Using instead an optocoupler to control the double switch connected to the load, and powering the optocoupler transistor with the voltage on the load, it would no longer be necessary to connect the two masses together and the galvanic isolation would be preserved.

As regards the second drawback, namely the inadequacy of the error signal, it is immediately obvious that the decoupler stage described in the Italian patent transfers a voltage in a substantially discontinuous manner. In fact, when a double switch is closed towards the main lines, the other is open and the load is no longer powered for the duration of a half wave. This type of operation does not pose limitations in slow applications, such as in the case of switching on a light bulb, but can instead be unacceptable in cases where the duration of the circuit breakers closing can be very short compared to their opening time, such as takes place in the context of the present invention. In these cases, as will also be seen below, the possibility of transferring part of the charge accumulated on the first capacitor to a second capacitor which supplies the voltage at the point where it is needed when the first capacitor is disconnected becomes fundamental. It is precisely the presence of a second capacitor that can qualify the above decoupler stage as a charge transfer network.

Finally, another cause is analyzed that could contribute to the loss of galvanic insulation, again with reference to the decoupler stage mentioned. It depends on the fact that a square wave is used to control the electronic switches, which involves simultaneous switching of the two double switches upon arrival of the steep edge. As is known, the active devices constituting the aforementioned switches take a finite time to go from a conduction state to an interdiction state, during which a direct path remains between the two points to be decoupled.

Therefore, the object of the present invention is to overcome all the aforementioned drawbacks and to indicate a DC / DC converter comprising a highly insulated charge transfer feedback network.

To achieve these purposes, the present invention relates to a DC / DC converter which uses a transformer to galvanically isolate the load from the primary power source, ensuring the aforementioned isolation also along the feedback path thanks to a charge transfer network inserted along said path. The network is essentially made up of two capacitors and two pairs of electronic switches made using solid state devices. A first pair of switches, when closed, connects a first capacitor in parallel to the load; the second pair connects the first capacitor in parallel to the second, which has one end connected to the primary ground. The two pairs of electronic switches are controlled by two respective periodic signals decoupled from each other through the transformer, which correspond to the signals used for switching two power transistors of the converter in a push-pull configuration. During each period of the control signals there are four phases in which: in a first of them, the first capacitor charges to the value of the voltage across the load; in a second step, the two pairs of switches are both open; in a third, the charge of the first capacitor is partially transferred to the second, and in a fourth phase the two pairs of switches are still both open. At the ends of the second capacitor a fraction of the voltage on the load is thus determined, even though the capacitor is galvanically isolated from the load itself, as better described in claim 1.

The DC / DC converter in question has the fundamental advantage of always guaranteeing perfect galvanic isolation between the load and the primary source. Power off isolation is obtained thanks to the use of enhancement MOSFETs (ie charge enrichment in the channel) in the charge transfer network. During operation, isolation is obtained thanks to the particular circuit structure of the charge transfer network, and the use of control signals decoupled from each other through the transformer. The use of optocouplers to control electronic switches is therefore completely superfluous. Furthermore, since the control signals are mutually out of phase by half a period and with a duty cycle of less than 0.5, any possibility of simultaneous closing of the two pairs of switches is eliminated, due to the finite time taken by the active devices to pass from conduction to interdiction. More precisely, the closing of a generic pair of switches is always preceded and followed by phases in which the two pairs of switches are both open.

A second advantage of the converter object of the present invention lies in its intrinsic stability, due to the fact that the charge control network works at frequencies of the order of 120 KHz without introducing an appreciable phase delay in the ring band, typically 12 wide. kHz. There is therefore no low frequency pole to neutralize and thermally compensate. It is also possible, given the invariance of the physical parameters of the charge transfer network, to use the voltage reference and the differential comparator inside the integrated circuit that governs the converter itself.

A third advantage is due to the fact that each switch is realized by means of two MOSFETs having the source electrodes connected to the respective substrates; the transistors are crossed by the same channel current, one in direct conduction and the other in reverse. Consequently, the diodes that are formed between the drain-substrate junctions are in series and with opposite polarity. This implies the guarantee of insulation also through the substrate.

Further objects and advantages of the present invention will become clear from the following detailed description of an example of its embodiment and from the attached drawing given purely for explanatory and non-limiting purposes, in which:

in the single figure (fig. 1) a general circuit diagram of the DC / DC converter object of the present invention is indicated in which the charge transfer network TRFC included in the feedback path is clearly shown.

The DC / DC converter of Fig. 1 comprises two power transistors TRI and TR2, respectively connected between the two ends of the primary winding of a TRS transformer and a primary ground, common to the negative terminal of a battery (not visible in the figure) which supplies a continuous voltage Vbat. The positive terminal of the battery is connected to one end of an inductor Li whose other end is connected to a central socket of the primary of the TRS; the latter divides the primary itself into two half-windings P1 and P2. The central tap of the primary is also connected to one end of a capacitor Ci, which has the other end to primary ground. The secondary of the transformer is also divided into two half-windings Si and S2 by a central socket connected to a secondary ground, galvanically isolated from the primary one. The two ends of Si and S2 are respectively connected to the anodes of two diodes DI and D2, whose cathodes are both connected to one end of an inductor Lo, which has the other end connected to the output terminal of the DC / DC converter . A capacitor Co is connected between the output terminal and the secondary ground, in parallel to Co a load resistance Ro is visible, at the ends of which there is the continuous output voltage Vout.

The transformer TRS has a further primary winding P3 which feeds a rectifier circuit RD; the latter supplies a direct voltage V for the power supply of a PWM integrated circuit which generates two signals, indicated with Q (t) and Q (t + T / 2), respectively applied to the control electrodes of the transistors TRI and TR2. The voltage V is also used by the converter protection circuits, connected as PWM to the primary ground, and not shown in the figure for reasons of simplicity. Inside the PWM integrated there is an operational amplifier OP whose non-inverting input is connected to the cathode of a zener diode Z (which schematises a reference voltage generator), and whose inverting input is connected to the output of a TRFC charge transfer network, possibly by means of a potentiometric voltage divider not visible in the figure. The anode of the zener diode Z is internally connected to the primary ground, the cathode is connected to the power supply pin V by means of circuits schematized with a resistor. At the output of the operational OP there is an error signal e, used inside the PWM integrated to generate the signals Q (t) and Q (t + T / 2).

The TRFC charge transfer network consists of two identical integrated circuits IC1 and IC2, two capacitors CI and C2 and two resistors RI and R2. Each integrated IC1 and IC2 comprises four identical enhancement-type n-channel MOSFET transistors, respectively indicated with 1, 2, 3, 4 and 5, 6, 7, 8; the use of p-channel MOSFETs, instead of n-channel, does not in any case alter the operation of the network. All transistors have the substrate (p-type) connected to the respective source electrode. Inside IC1 and IC2 there are also visible diodes (Ι ',. 8') corresponding to those existing between the drain electrode and the substrate of respective transistors. The gate electrodes of the MOSFETs 1, 2, 3 and 4 are all connected to each other and to one end of the secondary S2 connected to the diode D2. The gate electrodes of the MOSFETs 5, 6, 7 and 8 are all connected to each other and to one end of the primary P3. In the integrated IC1 the MOSFETs 1 and 2 have the source electrodes connected to each other, and the MOSFETs 3 and 4 have the drain electrodes connected to each other. In the integrated IC2 the MOSFETs 5 and 6 have the source electrodes connected to each other, as well as the MOSFETs 7 and 8.

Resistor R1 is connected between the output terminal of the converter and the drain electrode of MOSFET 1; the capacitor C1 has one end connected to the drain electrodes of the MOSFETs 2 and 3, and the other end connected to the drain electrode of the MOSFET 8 and to the source electrode of the MOSFET 3. The source electrode of the MOSFET 4 is connected to the secondary ground. The capacitor C2 has one end connected to the drain electrode of the MOSFET 6, the other end of C2 is connected to the drain electrode of the MOSFET 7 and to the primary ground. Resistor R2 is connected in parallel to C2 and to the inverting input of the operational OP inside the PWM integrated circuit.

As regards the illustration of the operation of the DC / DC converter of fig. 1, in push-pull configuration, please refer to the volume cited in the introduction, specifying that the PWM integrated in the example is the UCL846 of UNITRODE, however today there are many circuits capable of performing similar functions. As previously anticipated, they include an oscillator that generates a periodic signal with a presettable frequency, from which two identical periodic impulsive waveforms, of period T, are out of phase with each other by T / 2, corresponding to the signals Q (t ) and Q (t + T / 2). The width of the pulses is adjusted in negative feedback on the basis of the error signal and, with the constraint that it is always less than T / 2. To satisfy this last requirement, the UC1846 has a pin on which to act as described in the application notes of the same. The error amplifier OP makes the difference between the reference voltage present at the ends of the Zener diode Z, inversely biased, and a fraction of the voltage Vout present at the ends of C2.

The TRFC network makes the above fraction of Vout available without breaking the galvanic isolation existing between the primary and secondary side circuits, and even more so between the respective masses. This is made possible by the particular circuit configuration of TRFC, together with the shape of the signals that control iMOSFET of IC1 and IC2, and the choice of suitable points of origin for the application of said control signals.

As regards the first point, it can be noted that the MOSFETs 1, 2 and 3, A are able to completely dissect the contacts between the two ends of CI and the load Ro; as well as the MOSFETs 5, 6 and 7, 8 are able to completely dissect the contacts between the two ends of IC and those of C2. In practice, IC1 comprises a first pair of synchronous electronic switches, one of which consists of MOSFETs 1 and 2, and the other of MOSFETs 3 and 4. Similarly, IC2 comprises a second pair of synchronous electronic switches, of which one consists by the MOSFETs 5 and 6, and another by the MOSFETs 7 and 8. It is therefore circuitally possible to charge CI to the voltage Vout regardless of the charge present on C2, and in a similar way it is possible to transfer the charge of CI to C2 regardless of the voltage Vout. As will be seen shortly, it is precisely the independence of the aforementioned operations that preserves the galvanic isolation. In the open state, the MOSFETs used are able to withstand voltages of the order of 400 Volts, and being of the enhancement type, they remain open even with zero voltage on the source electrode. In the conduction state, the MOSFETs have a completely negligible channel resistance, specifying that of the two MOSFETs connected in series which form a generic electronic switch, one is always in direct conduction and the other in reverse. In this way the diodes formed between the well-substrate junctions are in series and with opposite polarity, thereby eliminating any possibility of conduction through the substrates and consequent breakdown of the galvanic insulation. A wrong choice of the type of transistors, especially in cases where the electronic switches are made with a single transistor, could instead lead to the establishment of a permanent conduction path through the substrates independent of the open or closed state of the electronic switches.

As regards the points of origin of the control signals of IC1 and IC2, it can be seen that said points are galvanically isolated from each other, since one belongs to the primary P3 and the other to the secondary S2 of the TRS transformer. The galvanic isolation between the control signals is maintained within the TRFC network, since the control signal taken from the secondary S2 controls only IC1, which is always isolated from the primary side circuits, as will be seen shortly; similarly, the control signal taken from the primary P3 only controls IC2, which is always isolated from the secondary side circuits.

A valid, and more general, alternative is to connect the control input of IC2 to an output of the PWM integrated circuit, while maintaining the connection between the control input of IC1 and the secondary S2 end which supplies the signal. suitable.

As regards the shape of the control signals of IC1 and IC2, it is that produced at the ends of the primary and secondary windings of the TRS transformer, due to the switching of TRI and TR2. The voltages at the ends of PI, P2, P3, Si and S2 are pulses of the same width as those belonging to Q (t) and Q (t + T / 2), but with polarity that are inverted at each half-period T / 2. In order to use them for the control of TRFC, it is necessary to take the voltage from the primary P3 and the secondary S2 with opposite polarity, then straighten them to single half-wave, using the positive half-waves to control IC2 and IC1 respectively. In practice, the rectification is performed by the MOSFETs themselves, it is therefore sufficient to connect P3 and S2 to the respective control point of IC2 and IC1.

It now remains to be seen if an insulation break could possibly occur during the transfer of the voltage Vout between the input and output of the TRFC governed by the above signals. The aforesaid control signals divide the operation of the TRFC network into four sequential phases which are repeated at each period T, the starting order is indifferent. Let's assume, for example, that the control signal corresponding to Q (t) is applied to IC1, and the one corresponding to Q (t + T / 2) to IC2, starting from an initial state in which the converter is off and the aforementioned signals bound to the respective mass potentials. In the initial state the two pairs of switches ICl and IC2 are both open, it follows that Cl and C2 are discharged, and Cl is isolated both from Ro and from C2.

During a first of the four operating phases an active control pulse reaches IC1 which produces the closure of the respective pair of switches, connecting one end of Cl to the output terminal of the converter and the other end to the secondary ground; Cl is charged to the Vout value through the resistor RI. At the same time, the control signal on IC2 is null and the pair of switches IC2 is open, isolating Cl from the circuits connected to the primary of the TRS. The charging time constant R1C1 is small enough to allow complete loading of Cl even in cases where the control pulse has a minimum duration.

In a second phase the two control signals are both null, in which case the load Cl is isolated from both Ro and C2. This second phase is always guaranteed, as the duration of the control pulses is always less than T / 2.

In a third phase an active control pulse reaches IC2 which produces the closure of the respective pair of switches, connecting Cl in parallel to C2 and allowing the charge transfer between Cl and C2. At the same time, the control signal on ICl is null and the pair of switches ICl is open, isolating Cl and C2 from the secondary side circuits of TRS. The charge transfer occurs almost instantaneously, the duration is limited only by the very low channel resistance of the MOSFETs 5, 6, 7 and 8. The parallel between the two capacitors remains for the entire duration of the active pulse, during this time the accumulated charge on the two capacitors it discharges through R2 with a time constant given by the product of R2 by C1 + C2.

In a fourth and last phase the two control signals are again both null, in this case the parallel between Cl and C2 is dissected, also in this case the same considerations made for the second phase are valid.

According to what has been said, the synchrony of operation of the two pairs of switches IC1 and IC2 is thus excluded in the most absolute way, preventing the formation of a connection path between them during the opening / closing transients, with the possibility of interrupt, even if briefly, the galvanic isolation.

At this point it is useful to make some further considerations on the values of RI, Cl, R2 and C2. A first necessity is that the time constants RlxCl and R2xC2 are small, to ensure that the respective poles introduced in the frequency response of the system fall far above the upper end of the ring band which, in the case of the example is about 12 KHz. In this way their existence does not disturb the stability of the converter itself. In practice, considering the Bode diagram of the loop gain, it is sufficient that these poles are at least a decade higher than said band end. A second necessity is that the voltage Vout on CI is not reduced too much on the parallel of CI with C2, which places a limit on the value of C2. Said value should in any case always be greater than that of Cl to ensure that, once the transfer is complete, the charge is mainly accumulated on C2; in this way C2 can act as a "memory" when the connection with Cl is interrupted before the completion of the discharge, which occurs in cases where the duration of the control pulses of IC2 is minimal. A good choice is, for example, C2 = 4C1. The value of R2 must be such as not to allow a too rapid discharge of the capacitor equivalent to the parallel of Cl with C2, or of C2 only, compatibly with the period T, because otherwise an error signal consisting of narrow pulses would result; In this case the energy would fall mainly on the components located outside the ring band.

The considerations made for the DC / DC converter of the example remain valid also for other circuit configurations other than the push-pull one, as long as they include a transformer to isolate the load from the primary power source. The configurations comprising a single power transistor have primary and secondary voltages in which the pulse fails in the middle of the period. The fact does not cause particular problems as regards the control of the TRFC network, it is sufficient only to connect the control input of IC2 directly to that PWM output that does not drive the power transistor, while for the control of IC1 the signal is taken to the secondary, as in the case of the example.

Devices other than those indicated can be used as electronic switches, the considerations made are in any case sufficient for the person skilled in the art to search for the waveforms that are each time most suitable for controlling the charge transfer network that uses the chosen devices. .

Claims (10)

CLAIMS 1. DC / DC converter comprising one or more power devices (TRI, TR2) operating as electronic switches that cyclically open and close the connection between a battery and the primary of a transformer (TRS), whose secondary voltage supplies a rectifier circuit connected to the output terminal of the converter, to which a load (Ro) is connected, and to a secondary ground galvanically isolated from the primary battery ground; said converter also comprising primary-side powered steering and control circuits (PWM), essentially consisting of: a) an oscillator that drives a logic for obtaining two identical periodic waveforms, of period T, out of phase between T / 2, consisting of pulses (Q (t), Q (t + T / 2)) used, or usable, for controlling the conduction state of power devices; b) a generator of a constant reference voltage stable in temperature; c) a circuit (OP) which makes the difference between said reference voltage and a fraction of the voltage (Vout) on the load, obtaining an error signal supplied to a regulation circuit (d), in negative feedback, of the duration of said pulses control, characterized in that said fraction of the voltage (Vout) on the load is obtained by means of a charge transfer network (TRFC) comprising: a first pair of synchronous electronic switches (IC1), controlled by a first control signal, which connect or disconnect respective ends of a first capacitor (Cl) to the output terminal of said power supply or to said secondary ground, allowing charging of said first capacitor up to a voltage value (Vout) across said load (Ro); a second pair of synchronous electronic switches (IC2), controlled by a second control signal, which connect or disconnect said first capacitor (Cl) in parallel to a second capacitor (C2), having one end connected to said primary ground, allowing a charge transfer between said capacitors (Cl, C2) and a consequent generation across said second capacitor (C2) of said fraction of the voltage on the load (Ro) used for determining said error (e); further characterized in that said first control signal corresponds to a first said impulsive periodic wave form (Q (t), Q (t + T / 2)), transferred to the secondary (S2) of said transformer (TRS), said first pair of electronic switches (IC1) being closed at said control pulses; from the fact that said second control signal is a said second impulsive periodic wave form (Q (t + T / 2), Q (t)), generated on the primary side, said second pair of electronic switches (IC2) being closed in correspondence of said control pulses; And by the fact that said regulation circuit limits the duration of said control pulses to values lower than T / 2, allowing the opening of both said pairs of electronic switches (IC1, IC2) before and after the charging of said first capacitor (Cl ). 2. DC / DC converter according to claim 1, characterized in that said first pair of electronic switches (IC1) connects said first capacitor (Cl) to the ends of said load (Ro) by means of a first resistor (RI) placed in series a said first capacitor (Cl). 3. DC / DC converter according to claim 1, characterized in that said second capacitor (C2) is connected in parallel to a second resistance (R2). 4. DC / DC converter according to claim 2, characterized in that the inverse of the time constant given by the product of 2π by the capacitance value of said first capacitor (Cl) and by the value of said first resistance (RI) , corresponds to a pole of the logarithmic frequency response of the loop gain of said DC / DC converter, the value of which is at least one decade higher than the upper end of the band of said response. 5. DC / DC converter according to claim 3, characterized in that the inverse of the time constant given by the product of 2π by the capacitance value of said second capacitor (C2) and by the value of said second resistance (R2) , corresponds to a pole of the logarithmic frequency response of the loop gain of said DC / DC converter, the value of which is at least one decade higher than the upper end of the band of said response. 6. DC / DC converter according to claim 1, characterized in that the capacitance value of said second capacitor (Cl) is higher than the capacitance value of said first capacitor (Cl). 7. DC / DC converter according to claim 1, characterized in that the electronic switches belonging to said pairs of electronic switches (IC1, IC2) are made by means of enhancement MOSFET transistors (1 ... 4, 5 .. 8), the transistors of each said pair having the control electrodes connected to each other. 8. DC / DC converter according to claim 7, characterized in that said transistors have the substrate connected to the respective source electrode; and in that each said electronic switch is made by means of two said transistors connected in series, a first transistor being in direct conduction and a second transistor in reverse conduction. 9. DC / DC converter according to claim 1, characterized in that the transfer to the secondary (S2) of said first pulsed periodic wave form (Q (t), Q (t + T / 2)), occurs by effect switching of a said power device (TRI, TR2) controlled by said first wave form. 10. DC / DC converter according to claim 1, characterized in that the transfer to the secondary (S2) of said first impulsive periodic wave form (Q (t), Q (t + T / 2)), occurs by effect switching of said power devices (TRI, TR2), said first control signal being obtained by rectifying the secondary voltage to a single half-wave.