IT971839B - PROCESS FOR THE MANUFACTURE OF MONOLITHIC DEVICES WITH ISOLATED TRAN SISTORS - Google Patents

PROCESS FOR THE MANUFACTURE OF MONOLITHIC DEVICES WITH ISOLATED TRAN SISTORS

Info

Publication number
IT971839B
IT971839B IT32876/72A IT3287672A IT971839B IT 971839 B IT971839 B IT 971839B IT 32876/72 A IT32876/72 A IT 32876/72A IT 3287672 A IT3287672 A IT 3287672A IT 971839 B IT971839 B IT 971839B
Authority
IT
Italy
Prior art keywords
isolated
manufacture
monolithic devices
tran sistors
sistors
Prior art date
Application number
IT32876/72A
Other languages
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT971839B publication Critical patent/IT971839B/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137Collector regions of BJTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
IT32876/72A 1972-01-25 1972-12-14 PROCESS FOR THE MANUFACTURE OF MONOLITHIC DEVICES WITH ISOLATED TRAN SISTORS IT971839B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH105572A CH536028A (en) 1972-01-25 1972-01-25 Method of making a monolithic device with isolated transistors

Publications (1)

Publication Number Publication Date
IT971839B true IT971839B (en) 1974-05-10

Family

ID=4201392

Family Applications (1)

Application Number Title Priority Date Filing Date
IT32876/72A IT971839B (en) 1972-01-25 1972-12-14 PROCESS FOR THE MANUFACTURE OF MONOLITHIC DEVICES WITH ISOLATED TRAN SISTORS

Country Status (6)

Country Link
JP (1) JPS4886490A (en)
CA (1) CA992218A (en)
CH (1) CH536028A (en)
DE (1) DE2300412A1 (en)
FR (1) FR2169069A1 (en)
IT (1) IT971839B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2532694B2 (en) * 1989-11-22 1996-09-11 三菱電機株式会社 Method for manufacturing semiconductor device
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate

Also Published As

Publication number Publication date
FR2169069A1 (en) 1973-09-07
DE2300412A1 (en) 1973-08-02
JPS4886490A (en) 1973-11-15
CA992218A (en) 1976-06-29
CH536028A (en) 1973-04-15

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