IT8421505A0 - Sincronizzazione di fase con un circuito per minimizzare le circuito d'orologio di riferimento. pertubazioni della frequenza d'orologio locale nella - Google Patents

Sincronizzazione di fase con un circuito per minimizzare le circuito d'orologio di riferimento. pertubazioni della frequenza d'orologio locale nella

Info

Publication number
IT8421505A0
IT8421505A0 IT8421505A IT2150584A IT8421505A0 IT 8421505 A0 IT8421505 A0 IT 8421505A0 IT 8421505 A IT8421505 A IT 8421505A IT 2150584 A IT2150584 A IT 2150584A IT 8421505 A0 IT8421505 A0 IT 8421505A0
Authority
IT
Italy
Prior art keywords
circuit
phase synchronization
frequency disturbances
reference clock
clock frequency
Prior art date
Application number
IT8421505A
Other languages
English (en)
Other versions
IT1175524B (it
IT8421505A1 (it
Inventor
Ivan L Edwards
Robert C Mc Laughlin
Max S Macrander
Original Assignee
Gte Communication Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Communication Syst filed Critical Gte Communication Syst
Publication of IT8421505A0 publication Critical patent/IT8421505A0/it
Publication of IT8421505A1 publication Critical patent/IT8421505A1/it
Application granted granted Critical
Publication of IT1175524B publication Critical patent/IT1175524B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
IT21505/84A 1983-06-23 1984-06-20 Circuito per minimizzare le pertubazioni della frequenza d'orologio locale nella sincronizzazione di fase con un circuito d'orologio di riferimento IT1175524B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/507,427 US4503400A (en) 1983-06-23 1983-06-23 Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit

Publications (3)

Publication Number Publication Date
IT8421505A0 true IT8421505A0 (it) 1984-06-20
IT8421505A1 IT8421505A1 (it) 1985-12-20
IT1175524B IT1175524B (it) 1987-07-01

Family

ID=24018603

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21505/84A IT1175524B (it) 1983-06-23 1984-06-20 Circuito per minimizzare le pertubazioni della frequenza d'orologio locale nella sincronizzazione di fase con un circuito d'orologio di riferimento

Country Status (4)

Country Link
US (1) US4503400A (it)
BE (1) BE899989A (it)
CA (1) CA1215436A (it)
IT (1) IT1175524B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890305A (en) * 1988-02-12 1989-12-26 Northern Telecom Limited Dual-tracking phase-locked loop
US4972160A (en) * 1989-12-07 1990-11-20 Northern Telecom Limited Phase-lock loop circuit with improved output signal jitter performance
US5220275A (en) * 1991-07-26 1993-06-15 Ericsson Ge Mobile Communication Holding, Inc. Accumulator phase digitizer
US7698588B2 (en) * 2003-05-15 2010-04-13 International Business Machines Corporation Circuit and related method for synchronizing data signals to a core clock
CN114513293B (zh) * 2022-02-24 2022-10-14 中国水利水电科学研究院 一种秒脉冲延迟补偿系统及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151485A (en) * 1977-11-21 1979-04-24 Rockwell International Corporation Digital clock recovery circuit
US4305045A (en) * 1979-11-14 1981-12-08 Bell Telephone Laboratories, Incorporated Phase locked loop clock synchronizing circuit with programmable controller
DE3025358A1 (de) * 1980-07-04 1982-01-21 Deutsche Itt Industries Gmbh, 7800 Freiburg Regelsystem zum einstellen einer physikalischen groesse

Also Published As

Publication number Publication date
CA1215436A (en) 1986-12-16
IT1175524B (it) 1987-07-01
US4503400A (en) 1985-03-05
BE899989A (fr) 1984-10-15
IT8421505A1 (it) 1985-12-20

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