IT239685Y1 - CIRCUIT SYSTEM SUITABLE FOR OPERATING AT DIFFERENT OPERATING VOLTAGE VALUES - Google Patents
CIRCUIT SYSTEM SUITABLE FOR OPERATING AT DIFFERENT OPERATING VOLTAGE VALUESInfo
- Publication number
- IT239685Y1 IT239685Y1 ITTO960050U IT239685Y1 IT 239685 Y1 IT239685 Y1 IT 239685Y1 IT TO960050 U ITTO960050 U IT TO960050U IT 239685 Y1 IT239685 Y1 IT 239685Y1
- Authority
- IT
- Italy
- Prior art keywords
- circuit system
- voltage values
- system suitable
- operating
- operating voltage
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017581—Coupling arrangements; Interface arrangements programmable
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE1995110947 DE19510947C1 (en) | 1995-03-25 | 1995-03-25 | Circuit arrangement for operation in different operating voltage ranges |
Publications (2)
Publication Number | Publication Date |
---|---|
ITTO960050U1 ITTO960050U1 (en) | 1997-09-13 |
IT239685Y1 true IT239685Y1 (en) | 2001-03-13 |
Family
ID=7757712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT96TO000050 IT239685Y1 (en) | 1995-03-25 | 1996-03-13 | CIRCUIT SYSTEM SUITABLE FOR OPERATING AT DIFFERENT OPERATING VOLTAGE VALUES |
Country Status (4)
Country | Link |
---|---|
DE (1) | DE19510947C1 (en) |
ES (1) | ES2122911B1 (en) |
FR (1) | FR2732171A3 (en) |
IT (1) | IT239685Y1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE504636C2 (en) * | 1995-07-27 | 1997-03-24 | Ericsson Telefon Ab L M | Universal transmitter device |
US6385547B1 (en) * | 1999-09-22 | 2002-05-07 | Otis Elevator Company | Automatic monitoring of high voltage signals |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61234118A (en) * | 1985-04-09 | 1986-10-18 | Mitsubishi Electric Corp | Waveform shaping circuit |
US5298807A (en) * | 1991-12-23 | 1994-03-29 | Intel Corporation | Buffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitry |
DE4219553A1 (en) * | 1992-06-15 | 1993-12-16 | Siemens Ag | Logic level converter between CMOS or TTL and current mode logic - provides output with smaller level shift at junction of resistance and chain of two complementary MOSFET(s) with different gate voltages |
US5371424A (en) * | 1992-11-25 | 1994-12-06 | Motorola, Inc. | Transmitter/receiver circuit and method therefor |
US5469082A (en) * | 1994-12-08 | 1995-11-21 | At&T Global Information Solutions Company | Peripheral component interfacing system with bus voltage/logic supply comparison means |
-
1995
- 1995-03-25 DE DE1995110947 patent/DE19510947C1/en not_active Expired - Fee Related
-
1996
- 1996-03-13 IT IT96TO000050 patent/IT239685Y1/en active
- 1996-03-13 ES ES9601914A patent/ES2122911B1/en not_active Expired - Lifetime
- 1996-03-25 FR FR9603669A patent/FR2732171A3/en active Granted
Also Published As
Publication number | Publication date |
---|---|
ES2122911A1 (en) | 1998-12-16 |
ES2122911B1 (en) | 1999-06-16 |
ITTO960050U1 (en) | 1997-09-13 |
FR2732171A3 (en) | 1996-09-27 |
FR2732171B3 (en) | 1997-03-07 |
DE19510947C1 (en) | 1996-11-28 |
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