IT202000017581A1 - PROCESSING SYSTEM FOR MONITORING THE CELL VOLTAGES OF A RECHARGEABLE BATTERY, RELATED BATTERY AND ELECTRIC VEHICLE MONITORING SYSTEM - Google Patents

Description

DESCRIPTION of the industrial invention entitled:

?Computer system for monitoring cell voltages of a rechargeable battery, related battery and electric vehicle monitoring system?

DESCRIPTION TEXT

Technical field

The embodiments of the present description relate to a monitoring and/or management system for a high voltage rechargeable battery comprising a plurality of of cells, such as lithium-ion cells.

Description of the related technique

Figure 1 represents a typical electronic system, such as the electronic system of a vehicle, including a plurality of of processing systems 10, such as embedded systems or integrated circuits, for example, an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor) or a microcontroller (for example, dedicated to the automotive market).

For example, three computer systems 101, 102 and 103 connected via a suitable communication system 20 are shown in Figure 1 .

For example, in the case of a vehicle, the communication system 20 can include a vehicle control bus, such as a controller area network (CAN) bus, and possibly a media bus, such as a media oriented systems transport (MOST) bus, connected to the vehicle control bus via a gateway. Typically, the processing systems 10 are located in different positions of the vehicle and can comprise, for example, a Unit? of Engine Control (ECU, ?Engine Control Unit?), a Unit? Control Unit (TCU, ?Transmission Control Unit?), an Anti-lock Braking System (ABS, ?Anti-lock Braking System?), Body Control Modules (BCM, ?Body Control Module?), and/or a multimedia and/or navigation audio.

In the case of electric vehicles, including all-electric vehicles, plug-in hybrid vehicles and non-plug-in hybrid vehicles, such as electric scooters, bicycles, motorcycles, trucks, cars, etc., the vehicle also includes a rechargeable battery 30 and a processing system 10 implementing a battery management system 40.

For example, Figure 2 depicts an example of a battery management system 40 configured to monitor a rechargeable battery 30, such as a lithium ion (Li ion) battery. As mentioned above, such a battery management system 40 can be used in an electric vehicle. However, the battery management systems 40 can also be used in other energy storage applications, such as home energy storage.

Specifically, in the example considered, the rechargeable battery 30 comprises a plurality of of C cells connected in series. For example, such cells C are usually organized in sets of cells, e.g. in the form of battery modules, where each set of cells usually comprises the same number n of cells. For example, in Figure 2, the cells are organized into m sets, where each set includes n cells, ie? the battery 30 comprises a first set of cells C1,1..C1,n, a last set of cells Cm,1..Cm,n and optionally one or more? intermediate sets of cells, where the sets of cells from C1,1..C1,n to Cm,1..Cm,n are connected in series.

Usually, such a battery management system 40 comprises two terminals 400 and 402 for connection to the battery 30, in particular to the first cell C1,1 and to the last cell Cm,n, and two terminals 404 and 406 for connection to a charging and charging circuit. Usually, the charging and charging circuit includes a switching circuit, e.g. in the form of an electrical (usually electronic) converter/inverter configured to receive energy from at least one power source and to supply energy to an electrical load. For example, in an electric vehicle, terminals 404 and 406 may be connected by a power controller to an electric drive motor of the vehicle. Conversely, in home energy storage applications, the 404 and 406 terminals can be connected to an inverter configured to:

- receive energy from the mains / distribution network or from a local electricity generator, as one or more? photovoltaic panels, e

- supply energy to a load in the home or even to the network.

In Figure 2 , the battery management system 40 includes a digital processing system 42 configured to monitor and/or control one or more batteries. battery parameters 30.

For example, Figure 3 represents a block diagram of an example of a digital processing system 42, such as a microcontroller. In the example considered, the processing system 42 comprises at least one digital processing circuit 422, such as a microprocessor, usually the Unit? Central Processing Unit (CPU, ?Central Processing Unit?), programmed by software instructions. Typically, the software that the drive runs of processing 422 ? stored in a program memory 424, such as a nonvolatile memory, such as a Flash memory or an EEPROM. Generally, 424 memory can? be integrated with the? unit? of processing 422 in a single integrated circuit or the memory 424 pu? be in the form of a separate integrated circuit and pu? be connected to the unit? of processing 422, e.g., by the tracks of a printed circuit board. Cos?, in general the memory 424 contains the firmware for the unit? processor 422, wherein the term firmware includes both the software of a microprocessor and the programming data of a programmable logic circuit, such as an FPGA.

In the example considered, the unit? processing 422 pu? have associated one or more? 426 resources, such as:

- one or more communication interfaces, such as Universal Asynchronous Receiver/ Transmitter (UART), Serial Peripheral Interface (SPI) bus, Inter-Integrated Circuit (I<2>C), Controller Area Network (CAN) bus, Ethernet, and/or debug interfaces ; and/or

- one or more analog/digital and/or digital/analog converters; and/or

- one or more dedicated digital components, such as hardware counters and/or timers, or a cryptographic coprocessor; and/or

- one or more analog components, such as comparators, sensors, such as a temperature sensor, etc.; and/or

- one or more mixed-signal components, such as a Pulse-Width Modulation (PWM) driver.

For example, using resources 426 and by suitable programming of digital processing circuitry 422, battery management system 40 can be configured to manage one or more? of the following functions:

- data exchange with other processing systems 10 of the electronic system, e.g. via communication channel 20;

- a piloting of one or more? electronic or electrical switches 410 and 412 in order to selectively connect the battery 30 to the terminals 404 and 406, e.g. based on the state of the vehicle (driving, parking, charging, etc.);

- a piloting and/or monitoring of a 414 pyro-fuse, which supplies e.g. an emergency shutdown of the battery 30 in the event of an accident, insulation breakdown or other breakdowns; And

- a monitoring of the current flowing through the battery 30, e.g. by a current sensor 418, such as a shunt resistor or a Hall effect sensor, and optionally a current sensor circuit 416, which performs already? a preprocessing of the signal supplied by the current sensor 418, e.g. in order to determine whether the measured current exceeds a given threshold.

Furthermore, in the case of rechargeable batteries 30 comprising a plurality of cells, such as high-voltage Li-ion batteries, the battery management system 40 ? often configured for:

- monitoring the voltages in the individual cells C of the battery 30; And

- optionally monitoring the temperature of the individual cells C or of sets of cells of the battery 30; and - optionally balance the charge level of the individual C-cells of the battery.

For example, as depicted in Figure 2 , often these battery management functions are not implemented directly in the digital processing system/circuit 42, but in additional processing systems/circuits 441..44m, wherein each processing system 44 performs the above operations for a respective set of cells, e.g. the processing system 441 manages the cells C1,1..C1,n and the processing system 44m manages the cells Cm,1..Cm,n.

In the considered example, the additional processing systems 44, such as integrated circuits, are then connected to the digital processing system 42 via a suitable communication channel 48. For example, digital processing system 42 can be configured to receive the cell voltages measured by the various processing circuits 44.

For example, Figure 4 represents a known solution. In the example considered, the processing system 44, e.g. an L9963 integrated circuit from STMicroelectronics, ? configured to be connected to a given number n of C cells, e.g. up to 14 C cells, and to generate digital samples of the respective cell voltages.

For example, as shown in Figure 5 , for this purpose, the computer system 44 can include a given number n 1 of pins CP0..CPn, where each pin CP ? configured to be connected to a respective cell terminal, e.g. the CP0 pin can? be connected to the negative terminal of a first cell C1, the pin CP1 pu? be connected to the positive terminal of a first cell C1 corresponding to the negative terminal of a second cell C2, etc. Thus, the voltage between two CP pins corresponds to the voltage in a given C cell. Generally, an analog filter, such as an RC low-pass filter, can also? be connected in parallel with each cell, where pins CP0..CPn receive filtered versions of the cell voltages.

In the considered example, the tensions are supplied to one or more? analog-to-digital converters (ADC, ?Analog-to-Digital Converter?) 448 differential, such as delta-sigma converters. To this end, the processing system 44 can also include a switching circuit 446, e.g. including one or more multiplexers, configured to connect a given pair of CP pins to a given analog-to-digital converter 448. Generally, the switching circuit 446 ? purely optional, why? the processing system 44 pu? also include n analog/digital converters, the cio? an ADC for each cell C of the respective set of cells. In the considered example, the digital samples are supplied to a digital processing circuit 444 of the processing system 44. Generally, the digital processing circuit 444 can be any hardware and/or software digital processing circuit, such as an integrated finite state machine (e.g., implemented with a hardware sequential logic circuit) or a microprocessor programmed by software instructions.

The processing system 44, e.g. the digital processing circuit 444, ? also configured to transmit the digital samples to the digital processing system 42, such as a microcontroller. To this end, the processing system 44 includes a communication interface 440. For example, in the case of an L9963 circuit, the communication interface 440 supports two modes: Communications: Serial Peripheral Interface (SPI) or isolated communication using capacitive or inductive coupling. However, in general, other communication protocols can also be used, such as I<2>C, UART or CAN bus.

Furthermore, e.g. in the case of a circuit L9963, a plurality? of processing circuits 44 can be connected in series in order to form a daisy chain. Specifically, for this purpose, each processing system 44 can comprising a further communication interface 442 configured to be connected to the communication interface 440 of a following/downstream processing circuit 44. Consequently, in this case, the digital processing circuit 444 can also manage the data exchange between the interfaces 440 and 442 of the respective processing circuit 44.

Consequently, the digital processing system 42 can include a communication interface 426 configured to be connected to communication channel 48:

- for example. when using isolated daisy chain communication, at interface 440 of first processing circuit 441; or

- for example. when using SPI communication, to each interface 440 of the various processing circuits 44.

Generally, in the event that the 426 interface is not compatible with the 440 interface, it can? be used a bridge circuit 46 to interface the 426 interface with the 440 interface. For example, such a bridge circuit 46 can? include a first interface 460, such as an SPI interface, for connection to interface 426, and a second interface 462 for connection to interface(s) 440. For example, the bridge circuit 46 can? be an STMicroelectronics L9963T integrated circuit.

Thus, in Figure 4 (and similarly in Figure 2 ), the processing systems 44 are configured to acquire by analog-to-digital converters 448 the voltages in the battery cells C (or filtered versions thereof) and to transmit (e.g., by means of other processing systems 44 and/or the bridge circuit 46) the digital samples of the cell voltages to the digital processing system 42. For example, when each set of cells includes the same number n of cells C, they must be acquired and transmitted up to n x m samples. For example, a typical 30 vehicle battery can have a voltage in the range of 200V to 1000V, typically between 400V and 800V. In this regard, a typical Li-ion cell has a voltage of approximately 3.7V. For example, this implies that at least 108 C cells must be connected in series in order to obtain a voltage of 400 V. Consequently, in this case, eight STM L9963 would be required to monitor the respective C cells. Evidently, in the case of 800 V systems, the numbers must be doubled. Thus, in typical applications between 50 and 250 cell voltages must be acquired. For example, cell voltages can be sampled with 448 ADCs that have 16 bits.

Preferably, the number of ADCs 448 in the processing systems 44 corresponds to (or ? greater than) the number n in order to allow the cell voltages in the cells (at least of the same set of cells and preferably of all the cells of the battery 30) can be sampled at the same time. For example, for this purpose, digital processing system 42 may send a sync trigger signal, or some kind of other sync signal, e.g. including a sampling period, to processing systems 44.

Furthermore, as mentioned above, the processing systems 44 can also implement other operations, such as a temperature monitoring of the respective cells or of the respective battery module, and/or a balancing function. For this purpose, further data can be exchanged between the digital processing system 42 and the processing systems 44.

However, due to the use of a serial communication channel 48, e.g. in the form of a daisy chain, preferably a galvanically isolated communication channel, data transfer has limited bandwidth. For example, does this imply that, especially in the case of high voltage batteries comprising at least 50 series-connected C cells, the sampling period ? slow.

Purpose and summary

In view of the foregoing, a purpose of various embodiments ? to provide a communication pi? efficiency of the cell voltages of a rechargeable battery, such as a high-voltage Li-ion vehicle battery.

According to one or more forms of implementation, one or more? of the preceding objects are achieved by a processing system for monitoring the cell voltages of a rechargeable battery having the distinctive elements specifically disclosed in the claims which follow. Embodiments are further related to a related battery and electric vehicle monitoring system.

The claims form an integral part of the technical teaching of the description provided herein.

As mentioned above, various embodiments of the present disclosure relate to a computer system, e.g. implemented in an integrated circuit, configured to monitor the cell voltages of a given number of cells in a rechargeable battery. For example, such processing systems may be used in a battery monitoring and optionally management system comprising terminals configured to be connected to a rechargeable battery, and a further processing system, such as a microprocessor, configured to receive cell voltages. from processing systems. For example, such a battery monitoring system can be used to monitor an electric vehicle rechargeable (traction) battery.

In various embodiments, the processing system comprises terminals configured to be connected to cells in order to receive cell voltages, and at least one analog-to-digital converter configured to generate digital samples of the cell voltages, wherein each digital sample has a given number of bits.

In various embodiments, the processing system also includes a digital processing circuit, a serial communication interface, and a transmission queue used to interface the serial communication interface with the digital processing circuit. Specifically, in various embodiments, the serial communication interface ? configured to sequentially transmit the stored data to the transmission queue, so the digital processing circuit and the serial communication interface can operate in parallel.

Specifically, in various embodiments, the digital processing circuit comprises a memory (e.g., volatile) and a data compression module (such as a software module and/or a dedicated hardware circuit) and the digital processing circuit ? configured to synchronously acquire a given number of digital samples of each of the given number of cell voltages and to store the acquired digital samples in a memory. Next, the digital processing circuit encodes the given number of digital samples of the given number of cell voltages stored in the memory by the data compression module, thereby generating encrypted data, and stores the encrypted data in the transmission queue. Consequently, in various embodiments, the serial communication interface ? configured to transmit the stored (encoded) data to the transmission queue, while the digital processing circuit acquires a new digital sample.

Generally, the data compression module can be configured to implement various lossy (?lossy?) or lossless (?lossless?) data compression operations.

For example, in various embodiments, the data compression module ? configured to generate the encoded data by means of a dynamic range reduction operation. In various embodiments, during the dynamic range reduction operation, the data compression module ? configured to subtract a given offset from each of the digital samples, generating with this? indicative values of the dynamic variation of each sample with respect to the offset. Next, the data compression module generates the encoded data by removing a given number of bits more? significant from each of the indicative values of the dynamic variation of each sample with respect to the given offset. Consequently, in this case, the further processing system can? reconstruct the original samples by adding the given offset to the received values. In various embodiments, the given offset ? programmable, e.g. the digital processing circuit can? be configured to receive the offset data via the serial communication interface, e.g. from the further processing system.

In various embodiments, also the given number of bits pi? significant can? be programmable, e.g. the digital processing circuit can? be configured to receive the given number of bits pi? significant via the serial communication interface, e.g. from the further processing system.

In various embodiments, during the dynamic range reduction operation, the data compression module ? also configured to generate the encoded data by removing a given number of least significant bits from each of the values indicative of each sample's dynamic variation with respect to offset. Even the given number of least significant bits pu? be programmable, e.g. the digital processing circuit can? be configured to receive the given number of least significant bits via the serial communication interface, e.g. from the further processing system.

Thus?, in various embodiments, the? range of values of the samples ? reduced. The inventor noted that this implies that the value of a sample could also be outside the range of values, e.g. in case of malfunctions. For this reason, in various embodiments, the data compression module ? configured to determine whether each of the given number of digital samples of the given number of cell voltages ? between a minimum and a maximum threshold. In the event that one or more of digital samples is not between the minimum and maximum thresholds, the data compression module can? store the value (original) of? one or more? digital samples that do not ? between the minimum threshold and the maximum, and pu? store data in encoded data that identifies which one or more? some digital samples are not between the minimum and maximum thresholds. For example, the data compression module can? write default values in the encoded data or pu? set a flag in the data packet transmitted to the further processing system.

Consequently, based on these data, the further processing system can determine that the encoded data is invalid and can? send a retransmission request to the processing system. As a result, the digital processing circuit/data compression module can? be configured to receive this retransmission request and, in response to the retransmission request, can? transmit through the serial communication interface at least one of the values of? one or more? digital samples that are not between the minimum and maximum thresholds, e.g. storing the stored (original) value in the transmission queue.

Additionally or alternatively, the data compression module can support other modes? of data compression. For example, in various embodiments, the data compression module ? configured to support a plurality? of mode? of coding, in which the data compression module ? configured to generate the data encoded in function of a modality? of coding selected, in which the modality? of selected coding ? programmable. For example, the digital processing circuit can? be configured to receive the mode? code selected via the serial communication interface, e.g. from the further processing system.

For example, in various embodiments, the modalities? coding can? include, in addition to or as an alternative to dynamic range reduction, at least one of:

- a mode? of delta encoding, in which the data compression module ? configured to generate delta coded values of digital samples with respect to one or more? reference values; And

- a mode? a Discrete Fourier Transform in 2D, in which the data compression modulus ? configured to apply a mode? a Discrete Fourier Transform in 2D at the given number of digital samples of the given number of cell voltages.

For example, the data compression module can? be configured to generate the delta-coded values of a given cell voltage:

- selecting the first of the given number of digital samples of the given cell voltage as a reference value, and generating the delta coded values by calculating the difference between each of the following digital samples of the given cell voltage with respect to the reference value; or

- selecting the first of the given number of digital samples of the given cell voltage as a reference value, and generating the delta coded values by calculating the difference between following digital samples of the given cell voltage with respect to a previous digital sample of the given cell voltage cell; or

- determining the values of a reference curve as a function of the digital samples, and generating the delta coded values by calculating the difference between each digital sample of the given cell voltage with respect to the values of the reference curve.

In various embodiments, the data compression module can also support a plurality? of these modalities? of delta coding, and the modalities? of delta encoding can be selected by programming the mode? of selected coding.

Also, in various embodiments, the data compression module can be configured to receive data identifying a value format and generate the delta encoded values based on the data identifying the value format by encoding the delta encoded values with a linear value encoding, or by encoding the delta encoded values with a mantissa and a exponent.

Thus, in various embodiments, the processing system/data compression module supports a plurality of data compression modules. of mode? coding and / or formats, and the? further processing system can? program the mode? of selected coding and/or the selected format, through the serial communication interface. For example, in this way, the further processing system can be configured to determine if the rechargeable battery ? in a state of charge or discharge and to select a first mode? of coding and/or a first format when the rechargeable battery ? in the state of charge and a second modality? encoding and/or a second format when the rechargeable battery? in the discharged state (which usually implies a higher variability of the cell voltages).

In various embodiments, the computer system can also be configured to form a daisy chain with other computing systems. In this case, the processing system can? comprise a further transmission queue, and a further serial communication interface configured to sequentially receive data (from another processing system) and to store the received data in the further transmission queue. Consequently, in this case, a multiplexer/arbiter can? be configured to connect the serial communication interface to the transmission queue or to the further transmission queue, for which the serial communication interface ? configured to sequentially transmit the stored data to the transmission queue or to the further transmission queue.

Brief description of the accompanying drawings

The embodiments of the present description will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting example, and in which:

The distinctive elements and advantages of the present invention will become apparent from the following detailed description of its practical embodiments, shown by way of non-limiting example in the attached drawings, in which:

- Figure 1 represents an example of an electronic system;

Figure 2 represents an example of a battery management system for a rechargeable battery;

Figure 3 represents an example of a digital processing system adapted to be used in the battery management system of Figure 2 ;

- Figure 4 represents an example of the implementation of the battery management function using additional battery management modules;

Figure 5 represents an example of the battery management module of Figure 4;

- Figure 6 represents an example of the operation of a battery management module;

Figure 7 represents an embodiment of the operation of a battery management module according to the present description;

- Figure 8 ? a block diagram representing an embodiment of a battery management module according to the present disclosure;

- Figure 9 ? a flowchart representing an embodiment of the operation of a battery management module according to the present disclosure;

- Figure 10 represents an embodiment of the data acquired by the battery management module of the present description;

Figure 11 represents an embodiment of the operation of the communication interfaces of the battery management module of Figure 8 ; And

- Figures 12 to 15 show embodiments of data compression operations suitable to be implemented inside the battery management module according to the present description.

Detailed description of embodiments

In the following description, various specific details are illustrated, in order to enable a thorough understanding of the embodiments. Can embodiments be provided without one or more? specific details or with other processes, components, materials, etc. In other cases, known operations, materials, or structures are not depicted or described in detail to avoid making various aspects of the embodiments unclear.

A reference to ?an embodiment? within the framework of this description it is meant to indicate that a particular configuration, structure, or feature described with reference to the embodiment ? included in at least one embodiment. Hence, sentences such as ?in an embodiment? or the like which may be present in various points of this description do not necessarily refer to the very same embodiment. Furthermore, particular conformations, structures or characteristics can be combined in any suitable way in one or more? forms of implementation.

References used herein are provided for convenience only and therefore do not define the scope or scope of the embodiments.

In Figures 6 to 15 described below, the parts, elements or components that are already? described with reference to Figures 1 to 5 are indicated with the same references used previously in these figures. The description of these elements ? already been made and will not be? repeated hereafter in order not to make the present detailed description too heavy.

As mentioned above, various embodiments of the present disclosure relate to a solution for communicating the cell voltages of a rechargeable battery, such as a high voltage Li-ion battery, such as the traction battery of an electric vehicle. In this regard, can you? refer to the previous description of a battery management system.

Figure 6 represents the operation of a computer system 44 as depicted in Figures 2, 4 and 5.

Specifically, in Figure 6, the analog-to-digital converters 448 are configured to sample the voltages VC in the respective cells C, i.e.? the voltages between pins CP0..CPn. In general, such analog-to-digital conversions require TCONV time. As previously mentioned, in various embodiments, each of the processing systems 44 includes n analog-to-digital converters 448, because? There? allows to carry out the conversions of the cell voltages in parallel at the same instant, and ? also reduced the total conversion time TCONV. For example, in various embodiments, the conversion time of a 448 ADC ? in the range between 100 us and 2 ms, preferably between 200 us and 400 us.

Once the digital samples of the cell voltages have been acquired by the digital processing circuit 444, the digital processing circuit 444 transmits one or more of the cell voltages. data packets via communication interface 440 to digital processing circuit 42, e.g. using a daisy chain as represented in Figure 4. Consequently, the one or more? Data packets usually comprise n samples, where each sample has a NADC number of bits corresponding to the NADC number of bits of the ADCs 448, such as 16 bits. Thus, at least a given number of bits (n x NADC) must be transmitted by each of the processing systems 44.

For example, does the L9963 chip support a mode? burst, in which ? transmitted a sequence of n data packets. Specifically, each data packet has 40 bits, only 16 bits of which are used to transmit the actual sample and the other bits contain additional data, such as a device ID which identifies the number of one of the 44 computing systems in a daisy chain . Furthermore, the transmission pu? also add additional error detection and/or error correction bits, such as ?Cyclic Redundancy Check? (CRC) bits. For example, typically the TTX transmission time to transmit the values of all the battery cells ? in a range between 4 ms and 8 ms.

Consequently, the transmission of the cell voltages of all processing systems requires a given time TTX, where the transmission time TTX also depends on the number m of sets of cells.

For example, when? used a daisy chain as shown in Figures 4 and 5, the digital processing circuit 42 can? send, through the communication interface 426, a command to the processing systems 44 which requests the sampling of the cell voltages and, in response to this command, each of the processing systems 44 can? sample the respective cell voltages.

In various embodiments, the processing systems 44 can automatically transmit the respective data and/or can wait for the unit? of digital processing 42 sends a command which contains a read request.

For example, in the latter case, the unit? of digital processing 42 pu? send a read request to each processing system 44 (e.g., including an identification of the respective processing system 44 in the command), and the respective processing system 44 can? send in response one or more? data packets that contain the sampled data. Generally, when? If a daisy chain is used, the read request and the sampled data can be transmitted by intermediate processing systems 44, ie? each processing system 44 can? be configured for:

- receiving data via the communication interface 440 and retransmitting the data via the communication interface 442; And

- receive data via the 442 communication interface and retransmit the data via the 440 communication interface.

Conversely, in the first case, the processing systems 44 can automatically generate a sequence of data packets. For example, in this case, the latest 44m processing system can? transmit, through the? interface 440, one or more? data packets including the respective data sampled to the processing system 44m-

1 previous, what? receives the data packet via the 442 interface, adds the respective sampled data and transmits the new data packets via the 440 interface to the previous processing system 44m-2, etc.

Regardless of the specific solution used to transmit the data packets, the total conversion time TCONV and the transmission time TTX define the minimum sampling period TSAMPLE between two consecutive conversions/transmissions, ie? TSAMPLE > TCONV + TTX.

Thus, in this solution, all of the n x m digital samples of the cell voltages must be transmitted to the digital processing circuit 42. During this time, the processing system 44 does not perform any further analog-to-digital conversions.

However, the inventor noted that, for high-power rechargeable batteries, such as Li-ion traction batteries for electric vehicles, a TSAMPLE sampling time between a few milliseconds and several tens of milliseconds can be too high. Specifically, as depicted in Figure 6, between two consecutive analog/digital conversions, one or more? of cell voltages can vary in a critical range without detection. In fact, as mentioned earlier, the minimum sampling time mainly depends on the communication bandwidth and the amount of of data, which in turn depends on the number n x m of cells C. On the other hand, an ADC usually has more performance? high, which would allow a better sampling frequency (?rate?).

Consequently, in the event that a disorder exceeds the Nyquist criterion, this disorder can not be detected, even if the ADC 448 could be used with performance pi? elevated.

A fairly simple and immediate solution to this problem would be to divide the communication channel 48 into various parallel communication channels, thereby reducing the the number of data to be transmitted on each communication channel. However, this means that the digital processing circuit 42 would also require various communication interfaces 426 and additional pins, and must handle various parallel communications.

Conversely, Figure 7 represents an embodiment of the operation of a processing system 44a according to the present disclosure.

Specifically, in the embodiment considered, the processing system 44a is configured to carry out, for each of the n cell voltages, a plurality? of k analog-to-digital conversions during one TSAMPLE sampling period. For example, in Figure 7 , the processing system 44a performs three analog-to-digital conversions at approximately time intervals TADC = TSAMPLE/k, with TADC > TCONV.

Afterwards, the 44a processing system ? configured to generate one or more? data packets comprising data determined by performing lossless and/or lossy data compression of the k digital samples of the n cell voltages, and for transmitting one or more? data packets. Specifically, as depicted in Figure 7 , in various embodiments, the transmission can take place while the subsequent analog/digital conversions are made, and the only constraint ? that the transmission time TTX of the data packet (comprising the compressed data of a plurality of digital samples) is less than the sampling time TSAMPLE, or vice versa that the sampling time TSAMPLE must be greater than the transmission time TTX.

Figure 8 represents an embodiment of the processing system 44a. Specifically, in the embodiment, the processing system 44a has the same basic architecture as the processing system 44 already. described with reference to Figure 5. Specifically, also in this case, the processing system 44a comprises:

- a given number n 1 of pins CP0..CPn for connection to n cells C1..Cn;

- a plurality? of (preferably n) analog/digital converters 448 configured to generate digital samples of the voltages between two pins CP0..CPn connected to the same cell C, thereby generating? digital samples of the voltages in the cells C1..Cn (or their filtered versions); - optional 446 multiplexer to connect CP0..CPn pins to 448 analog/digital converters;

- a communication interface 440 for transmitting digital data;

- a further optional communication interface 442 in the event that the processing systems 44a can be connected in cascade to form a daisy chain; And

- a?unit? of digital processing 444a.

Specifically, with reference to Figure 5, the unit? of digital processing 444a ? configured to implement a? unit? of data compression 450. Generally, the unit? of data compression 450 pu? be a dedicated hardware circuit and/or can? be implemented with computer instructions executed by a programmable microprocessor 444a.

Figure 9 represents an embodiment of the operation of the unit? of digital processing 444a.

Specifically, after a 1000 start phase, the unit? processing unit 444a proceeds to a phase 1002, where the unit? processing unit 444a awaits the start of a new sampling interval TSAMPLE. For example, the unit? of digital processing 444a pu? wait in phase 1002 for a trigger event, such as:

- a trigger signal received by the unit? digital processing systems 42 (possibly by means of other processing systems 44a); or

- a trigger signal generated within the processing system 44a, e.g. by means of a timer circuit (possibly also implemented within the digital processing unit 444a), e.g. which indicates that the time TSAMPLE ? spent.

For example, in various embodiments, each processing system 44a includes a respective timer circuit, which can be started (or reset) in response to a sync signal received from digital processing circuit 42. In this case, the TSAMPLE time can also? be programmable.

Generally, this stage? purely optional, why? the unit? of digital processing 444a pu? also start a new TSAMPLE sampling interval immediately, and the duration of the TSAMPLE sampling interval can? be defined by other delays, as sar? described, e.g., with reference to step 1008.

Once ? detected (or, in general, is it started) a new sampling interval in the phase 1002, the unit? processing unit 444a proceeds to a phase 1004, where the unit? processing unit 444a acquires the digital samples of the cell voltages through the analog-to-digital converters 448. For example, the unit? of digital processing 444a pu? start, in phase 1004, an analog conversion and pu? wait for the analog-to-digital converters 448 to signal that their respective conversions have been completed. In the event that the number of analog/digital converters 448 is less than n, the unit? of digital processing 444a pu? also set up the 446 multiplexers and start a new analog/digital conversion.

Consequently, at the end of the 1004 phase, the unit? The digital processing unit 444a obtained the digital samples of the cell voltages for a given sampling instant.

The unit of digital processing 444a then proceeds to a verification phase 1006. Substantially, the unit? The digital processing unit 444a checks in step 1006 whether further sampling operations should be performed for the same sampling interval. Indeed, as previously mentioned, in various embodiments the data packet to be transmitted is? determined according to a plurality? of k samples for each of the cell voltages, as three samples. For example, in various embodiments the unit? of digital processing 444a pu? be configured such that the k-value is programmable. For example, for this purpose, the value k pu? be stored in a programmable memory (volatile or non-volatile), and the unit? of digital processing 444a pu? be configured to receive a new value via the 440 (or 442) communication interface and to overwrite the stored k value.

Specifically, in the embodiment considered, in the event that further samples are to be obtained (output "N" of the verification phase 1006), the unit? processing unit 444a proceeds to a waiting phase 1008, where the unit? processing unit 444a waits for the next sampling instant.

For example, the unit? of digital processing 444a pu? wait in phase 1008 for a given trigger event which indicates that the TADC time ? spent. Once the unit? digital processing unit 444a detects the next sampling instant, the unit? digital processing unit 444a proceeds again to step 1004 to obtain the next samples of the cell voltages. For example, at various times, each processing system 44a includes a respective timer circuit configured to generate a trigger when the TADC time is ? spent. For example, such a timer circuit can be started (or reset) in step 1004 or 1008 (depending on whether the TADC time refers to the time between two consecutive start instances of A/D conversions, or the time between the end of an A/D conversion and the? start of the next A/D conversion). In this case, even the TADC time can? be programmable.

Generally, also the waiting phase 1008 ? purely optional, and the TADC time pu? correspond to the conversion time TCONV of A/D conversions. For example, in this case, the sampling period TSAMPLE can? have (approximately) a time k TCONV. For example, in various embodiments, ADCs 448 may be configured such that the conversion time or ?conversion window? TCONV is programmable. For example, sigma-delta ADCs work in such a way that there? results in averaging the voltage during the window. There? does it mean that the voltage curve ? flattened (?smoothened?), but that the information contained is not lost per se.

On the other hand, if a given number k of samples has been obtained ("Y" output of the verification phase 1006), the unit? of digital processing 444a proceeds to a phase 1010, in which the unit? of digital processing 444a generates one or more? data packets using a lossless and/or lossy data compression operation. Thus, as also shown in Figure 10 , the digital processing circuit 444a is configured to acquire a DATA set of data, e.g. in the form of a matrix, comprising for each cell voltage a respective set of k samples, ie? from samples S1,1..S1,k for the voltage of cell C1 (connected between pins CP0 and CP1) to samples Sn,1..Sn,k for the voltage of cell Cn (connected between pins CPn-1 and CPn), and to generate the? One or more? data packets to be transmitted depending on the data set DATA.

Afterwards, the unit? processing unit 444a proceeds to a phase 1012, where the unit? processing module 444a sets a transmission flag which indicates that the one or more? packets of data are ready for the transmission and the unit? processing unit 444a returns to step 1002 in order to wait for the start of the next sampling period TSAMPLE.

For example, in various embodiments, in response to this transmit flag, processing system 44a may:

- automatically transmitting the data packet to the digital processing circuit 42;

- waiting for a transmission request from the digital processing circuit 42 and, in response to this transmission request, transmitting the data packet to the digital processing circuit 42; or

- wait one or more? received data packets via interface 442 (from another processing system 44), add the data packet to the received data packets, and transmit the new data packets via interface 440 (to a following processing system 42 , to the digital processing circuit 42 or to a bridge circuit 46).

For example, the first two options can also be applied to the last 44m processing system in a daisy chain.

As previously mentioned, in various embodiments, communication interface 440 (and 442) can operate in parallel with the analog-to-digital converters 448. For example, as shown in Figure 11 , for this purpose, digital processing circuit 444a, particularly encoder circuit 450, can operate in parallel with analog-to-digital converters 448. store the encoded data packet(s) in a transmission queue 452, such as a FIFO memory, and the communication interface 440 can automatically read the data from the 452 transmission queue and transmit the data.

Specifically, in various embodiments, the processing system 44a includes a first queue 452, such as a first FIFO memory, in which the encoder circuit 450 is configured to store the encoded data packet(s) (indicative of n x k samples) in the first queue 452. Furthermore, the processing system 44a comprises a second queue 454, such as a second FIFO memory, in which the communication interface 442 ? configured to store received data (i.e., data received from another processing system 44) in second queue 452. For example, in various embodiments, first queue 452 has a size that is ? sufficient to store at least the compressed data (generated as a function of the n x k samples S), and preferably the complete data packets. On the other hand, the second queue pu? also include only a single register.

Consequently, using a 456 multiplexer, the 440 communication interface can sequentially transmit the stored data to queues 452 and/or 454. For example, when the transmit flag ? set and once it has received data through the 442 communication interface (which can be detected because the 454 queue contains data), the 440 communication interface can:

- first transmit the stored data to queue 454 and then transmit the stored data to queue 452, ie? the encoded data packet ? added to the received data; or - first transmit the stored data to queue 452 and then transmit the stored data to queue 454, ie? the received data is added to the encoded data packet. In various embodiments, as mentioned above, the latest 44m processing system can directly transmitting the stored data to queue 452 in response to the transmit flag.

As mentioned earlier, in various embodiments, the transmission of stored data to queue 452 may also be initiated in response to a request received from the unit? processing 42 (instead of using an automatic transmission). Consequently, in this case, the interface 440 can? be configured to always send stored data to queue 454 (bypass function) and to send stored data to queue 452 only in response to a read request.

Will the possible embodiments of the operation of the unit now be described? of data compression 450. In general, as previously described, the unit? of data compression 450 ? configured to process a set of data DATA comprising for each of the n cell voltages a plurality? of k samples, that is? the unit? of data compression 450 ? configured to generate one or more? data packets to be transmitted according to the samples S1,1..S1,k to Sn,1..Sn,k. For example, as mentioned earlier, these data packets (or the processed/compressed data) may be stored in queue 452. In order to describe the operations applied to a given sequence, one will do reference to a generic sequence of samples S1..Sk, corresponding to one of the n sequences.

Figure 12 represents a first embodiment of the operation of the unit? compression tool 450 (step 1010 in Figure 9 ).

Specifically, after a phase of the beginning of 2000, the unit? of data compression 450 ? configured to compare in a step 2002 the value of each sample S with a given upper threshold value THH and a given lower threshold value THL.

Specifically, Fig. 13 represents in this regard possible discharge curves of a Li-ion C-cell, such as a Li-ion C-cell based on ManganOxid. Specifically, Figure 13 plots the profile of cell voltage VC versus a percent CH cell charge for different C-rates, such as 0.05C, 0.1C, 0.5C, and 1C.

As represented in Figure 13, in normal operation, the cell voltage remains between an upper threshold value THH and a lower threshold value THL, as between an upper threshold value THH corresponding to the voltage of 4.2 V and a value of lower threshold THL corresponding to the voltage of 3.0 V. Generally, the specific values can vary according to the chemistry of the cell.

Consequently, in the event that the values of all the samples from S1,1..S1,k to Sn,1..Sn,k are between the upper threshold value THH and the lower threshold value THL, the unit? of data compression 450 proceeds to a phase 2004, where the unit? of data compression 450 reduces the dynamic range of the samples from S1,1..S1,k to Sn,1..Sn,k. Specifically, in various embodiments, the unit? compression tool 450 subtracts a given constant OFF offset from each sample S, such as the lower threshold value THL, and removes a given number of bits pi? significant. In various embodiments, the OFF offset ? programmable, e.g. in order to allow the same processing system 44a to be used with different cells having different voltage ranges.

For example, in an L9963, the 448 ADCs have 16 bits with a resolution of 89 uV. For example, for the aforementioned voltage range (3.0V to 4.2V) and resolution (89uV), 12 bits (i.e., 2048) would be sufficient in order to transmit the values of a sample S , that is?, once that ? been subtracted the? offset OFF, the? unit? of data compression 450 pu? remove the 4 bits pi? significant values of each sample S. Indeed, in order to reconstruct the original value of the sample, ? it is sufficient for the digital processing circuit 42 to add the OFF value again to each transmitted value. In various embodiments, the number of bits pi? significant to remove? programmable.

Also, the inventor noted that while 448 ADCs can actually support a resolution of 89 uV, with a speed? of fast conversion in the range of 300 us, this resolution usually not ? satisfied for the value actually measured, and in reality? the two least significant bits can be quite meaningless. Consequently, in various embodiments, the unit? of data compression 450 pu? also remove a given number of least significant bits in step 2004. In various embodiments, the number of least significant bits to remove is ? programmable. For example, the number of least significant bits that can be "useless" can? depend on the conversion time TCONV (fixed or programmed), e.g. fewer least significant bits should be removed as the conversion time increases. Consequently, in various embodiments, the conversion time TCONV can? be programmable and the? unit? of data compression 450 pu? be configured to determine the number of least significant bits to remove according to the data used to program the conversion time TCONV of the ADCs. However, in various embodiments, the number of least significant bits to remove may also be programmed independently.

Thus, substantially, step 2004 reduces the number of bits of the samples S of the data structure DATA, e.g. at 10-bit, without (appreciably) affecting the original precision of the sampled data. For example, in the case where the processed samples S have 10 bits, the data packet(s) would comprise(s) a total of k x 10 bits for each of the n cell voltages.

Conversely, if the value of at least one of the samples from S1,1..S1,k to Sn,1..Sn,k is greater than the upper threshold value THH or lower than the lower threshold value THL, l? unit? of data compression 450 proceeds to a phase 2006. Specifically, usually this condition occurs only in the event of a malfunction. In general, in this case, no ? Samples can be transmitted with a small dynamic range.

In a first embodiment, the unit? of data compression 450 ? configured to replace the values which are between the thresholds THL and THH with the sequences of bits of reduced length described with reference to phase 2004. Conversely, the unit? of data compression 450 pu? memorize the values that exceed the threshold values, and pu? replace the values with default values, e.g. a bit pattern of "0" for samples that are less than the low threshold and a bit pattern of "1" for samples that are greater than the high threshold. Consequently, the unit? of digital processing 42 pu? easily determine that given values were out of range, and pu? request a transmission of the respective (stored) original values if necessary.

By contrast, in other embodiments, the unit? of data compression 450 pu? switch to a different data packet format. For example, such a different data packet format can be indicated using packets of data which also include a? header (? header?), which pu? comprising a field for storing a value indicating a data packet format. Alternatively, the data package can? start with a predetermined bit sequence that usually is not ? possible when using the operations indicated in step 2004, such as a sequence of bits of predetermined length which has all values set to "0" or "1".

For example, in this case, the data packet(s) can? (may) include:

- only a single value (with full resolution) for each cell voltage selected among the k samples S of each cell voltage, such as the pi? large value in the event that one of the samples exceeds the upper threshold value THH or pi? small value in case one of the samples exceeds the lower threshold value THL; or - all the k values (with full resolution) for each cell voltage because, in case of malfunctions, it can? not be necessary to keep the same sample rate.

For example, usually passing a default value or a single ? enough, why? this condition already indicates? a malfunction. Indeed, the transmission of plural values for each cell voltage usually ? required only in order to cause rapid changes during normal battery operation.

In both cases (phases 2004 and 2006), the unit? of data compression goes to a shutdown 2008.

Figure 14 represents a second embodiment, which can also be combined with the embodiment described with reference to Figures 12 and 13 .

Specifically, the embodiment depicted in Figure 14 can be used in the event that a plurality? of k samples S1..Sk (with full or reduced resolution) must be transmitted for the same cell voltage, and pu? what? also be used after the 2004 and/or 2006 phases described above.

Specifically, as represented in Figure 15, in the embodiment considered, the unit? of data compression 450 ? configured to perform a delta encoding operation. Specifically, in this case, one of the samples of each sequence S1..Sk ? maintained as a reference value, e.g. the first sample S1 (as represented in Figure 14) or the last sample Sk of each sequence S1..Sk, and other samples are used to calculate (k - 1) delta values D1..Dk-1, ie? the delta values from D1,1..D1,k-1 to Dn,1..Dn,k-1 for all n cells.

Specifically, each delta value Di, with i = 1..(k - 1), can? be determined by calculating the difference between the value of a respective sample and the reference value, e.g. Di = Si+1 - S1, or each delta value Di pu? be determined by calculating the difference between the value of a respective sample and the value of the previous sample, e.g. Di = Yes+1 - Yes.

Thus, the delta values D1..Dk-1 reflect the absolute change (from the reference value) or a relative change (from the previous value) of the sample sequence S1..Sk.

Generally, the 30 battery can? be in a state of charge or in a state of discharge, and the inventor has observed that the maximum variation of the cell voltages depends on this state. For example, the inventor has observed that in the state of charge the cell voltages usually vary only in the mV range, when the samples are acquired with a TADC period which is ? less than 10 ms. For example, in this case, delta values can be encoded with bit sequences that have 4 to 6 bits.

In a similar way to the operation described with reference to Figure 12, the difference between two samples can also exceed the possible range, for ex. -7 to 7 (for 4 bits) or -31 to 31 (for 6 bits).

Consequently, after an early 2020 phase, the unit? of data compression 450 pu? check (similarly to step 2002) whether all the delta D values are between a maximum threshold value THH and a minimum threshold value THL.

For example, in the event that all the delta D values are between the maximum THH value and the minimum THL value ("Y" output of verification phase 2022), the unit? of data compression 450 pu? encode in a step 2024 (similar to step 2004) the delta value with the reduced bit resolution, e.g. using two's complement binary encoding.

On the other hand, if the delta value is greater than the maximum THH value or less than the minimum THL value ("N" output of the verification phase 2022), the unit? of data compression 450 pu? proceed to a 2026 phase (similar to the 2006 phase).

Generally, the 2026 phase ? used to signal that one or more? delta values exceed the allowed range. For example, as mentioned with reference to the 2006 phase, in this case, the unit? of data compression 450 pu? memorize the respective delta value and pu? replace out-of-range delta values with a default value, e.g. a sequence of bits corresponding to the maximum value THH (e.g., 7) or the minimum value THL (e.g., -7) (similar to step 2006). Alternatively, the unit? of data compression 450 pu? switch to a different data packet format and pu? put in the data package:

- only a single value (with full resolution) for each cell voltage selected among the samples S of each cell voltage, such as the pi? big or the most? small value; or

- all k samples (with full resolution) for each cell voltage.

Also in this case (for both phases 2024 and 2026), the unit? of data compression 450 proceeds to a stop phase 2028.

Consequently, when the dynamic range solution (Figure 12) and the delta value solution (Figure 14) are combined, the unit? data compression module 450 generates a data packet comprising for each cell a first absolute value, e.g. having 10 bits, and therefore (k ? 1) delta values, e.g. having 4 bits. For example, in the case of k = 3, pu? be sufficient that 18 bits are transmitted, which ? close to the 16 bits used in a traditional L9963 chip.

For example, in various embodiments, computer system 44a can support (at least) two data packet formats having the same number of bits, such as 40 bits:

- a first format, in which only a single measured value ? transmitted with full resolution (NADC, eg 16 bit) for each cell voltage (substantially corresponding to the solution currently adopted in the L9963 circuits); And

- a second format, in which compressed data is transmitted.

In this case, the processing system 42 can be configured to issue a command to data processing systems 44a indicating which format should be used, which could be a common format for all processing systems 44a or processing system 42 may sending a command to each processing system 44a indicating a respective format. In various embodiments, the command pu? also include data indicating which compression format should be used, e.g. a reduction of the dynamic range and/or a delta encoding, and possibly the respective parameters (offset, number or MSB and/or LSB to be removed, number of bits of the delta encoding, etc.)

Consequently, in various embodiments, the unit? of data compression 450 pu? be configured to generate the data packets according to the respective configuration. As mentioned earlier, when one or more? of the values are out of range (they exceed the? dynamic range or the range of the delta coding), the unit? of data compression 450 pu? insert data identifying this fact in the data package. For example, the unit? of data compression 450 pu? set a flag or pu? insert data predetermined values into data packets. For example, as mentioned earlier, the data package can include 16 bits to transmit the measured data. In order to enter the compressed data in these 16 bits, the unit? of data compression 450 pu? periodically insert the reference value of the delta encoding (for example, having 10 bits after the reduction of the dynamic range) in a data packet (associated with a given sampling interval), and pu? therefore transmit for a given number of data packets (associated with the following sampling intervals) only the delta encoded values (preferably with a reduction of the previous dynamic range). For example, as mentioned earlier, when delta coded values are used (relative to the reference value or relative to the previous value), each value could have 4 bits. Consequently, three samples would require 12 bits, which also allows us to use i (16 ? 12) = 4 remaining bits for one or more samples. flags that indicate if one or more? some values are out of range. For example, a respective bit of these remaining 4 bits could be associated with each of the delta encoded values.

Consequently, in the event that the processing system 42 determines that one or more? values are out of range, the processing system 42 may request a retransmission of the respective absolute values using the first data packet format.

The inventor has observed that the delta coding scheme described (possibly combined with dynamic range compression) ? particularly useful when the battery 30 ? loaded, why? usually you can? expect only low dynamic range. Specifically, can you? to hypothesize that, during the charge, the cell voltage will vary? in a limited range and that the voltage ? mainly function of the capacity? of the cell (which can change during life cycles and aging), the charge level of the cell and the current that charges the cell. However, this usually won't happen. no jump in voltage level. For example, considering the above example of ADCs with 0.089 mV resolution and with dynamic range reduction and delta encoding, where two LSBs have been removed and 4 bits are used to transmit the delta values, ? used a delta range of 2^6 * 0.089 mV = 5.6 mV (e.g., /-2.8 mV). As mentioned earlier, this range can apply to the difference from the reference value or only between two consecutive samples.

As mentioned earlier, there? does not necessarily apply when the battery ? downloaded, e.g. when the vehicle ? traveling or with other similar high dynamic load variations. However, the inventor has observed that in this case usually the voltages of the n cells have a variability? similar. In fact, a voltage drop can? not be observed only in a single cell, but a similar fall also occurs in the others of the connection series since? they must all deliver the same current (see the C-rate in the discharge curve represented in Figure 13). What?, ? required an interval more? great, but the variation of the cell voltages of the various cells ? connected.

For example, in this case, instead of using a linear delta value, the delta values could be encoded as an exponent and a mantissa. For example, in this case, only a limited number of exponents would be used for all delta values. Consequently, these exponents could be shortened (similarly to a Huffman coding), associating to the possible exponent value sequences of bits with a reduced number of bits, and the unit? of data compression pu? insert the coded exponent value and mantissa with a given number of bits into the data packet. For example, considering the previous example, where 16 bits are used to transmit the encoded data, the data packet could include 2 bits for the mantissa and 3 bits for the encoded exponent for each of the 3 samples. The remaining bits could be used to indicate whether one or more? some values are out of range. In this case, one or more additional data packets could also store data indicating the mapping between the encoded exponent values and the decoded exponent values.

Alternatively, a given cell j of the n cells in a given set could represent a reference cell, such as the first (j = 1) or last (j = n) cell. In this case, the unit? of data compression 450 pu? be configured to transmit the absolute values or the delta values (possibly also with a reduction of the previous dynamic range) of the reference cell with a resolution pi? elevated. For example, the unit? data compression could transmit the 10 bit encoded value Sj,1, and then the following delta encoded values Dj,1 to Dj,k-1 with 8 bits. Conversely, the samples of the other cells are transmitted:

- calculating, for each of the other cells i, an offset Oi of the first sample Si,1 of the respective cell with respect to the first sample Sj,1 for the reference cell, so that the offset Oi represents the voltage offset of cell i with respect to the voltage of cell j:

Oi = Si,1-Sj,1;

- calculating the delta value Di,h, with h = 1..(k - 1) for the other samples of the respective cell according to the following equation:

Di,h = Si,h+1 - Sj,h+1 - Oi.

Consequently, once the samples of the reference cell j have been reconstructed, the processing system 42 can calculate the other samples using the following equations:

Si,1 = Sj,1 Oi;

Si,h+1 = Sj,h+1 + Oi + Di,h.

Consequently, in this case, the processing system 42 can periodically transmit the offset values with a number of bits pi? high, e.g. 8 bits, but delta values Di,j should still have a limited range and can be transmitted with more bits? low, e.g. 4 bits.

Consequently, in the embodiment considered, substantially the samples of the reference cell j represent a reference curve/shape of the behavior of the cell voltages, and the offset Oi ? used to determine an expected waveform for the voltage shape of a given cell i, and the delta value ? used to provide information about the shift of the actual value of a given sample from the expected value. Consequently, instead of using the samples of a predetermined cell as reference samples, new reference samples could also be calculated, e.g. calculating an average value of the samples in a given instant, or dynamically selecting as a reference cell the cell that has the pi? small values, which allows e.g. to use only offset values encoded positive, which allows cos? to improve the range of values.

In various embodiments, more efficient compression algorithms can also be used. complexes that take into consideration the fact that the variation of the voltage of a given cell is not ? linked only to the values of adjacent samples of the same cell (row), but ? also linked to the variation of the voltage of an adjacent cell (column). For example, there are similar situations in traditional image compression algorithms, where the compression algorithm uses the fact that the value of a given pixel (corresponding basically to one of the samples) is? often linked to surrounding pixel values. For example, also in the present case, the quantity? of data can? be reduced by applying a 2D Discrete Fourier Transform to the DATA data.

Generally, the unit? of data compression 450 pu? also support a plurality? of the data compression procedures previously described, the cio? the unit? of data compression 450 pu? include one or more circuits configured to carry out one or more? of the following operations:

- the reduction of? dynamic range, which can? also be used in combination with other compression processes;

- simple delta coding with respect to a reference value of the samples of the same cell;

- a complex delta coding against a reference curve including reference samples, e.g. of a reference cell;

- a delta encoding with mantissa and encoded exponent; And

- a Discrete Fourier Transform in 2D.

Consequently, in various embodiments, the unit? of processing 42 or the processing system 44 pu? determine if the battery ? in the state of charge or discharge, e.g. receiving respective information for an ECU of the vehicle, and pu? selecting a first data compression format (e.g., a simple delta encoding) in the charged state, and a second data compression format in the discharged state.

Consequently, the embodiments described herein allow cell voltages to be supervised even while data communication is in progress. Furthermore, thanks to the proposed data compression, sampling can be carried out with a frequency pi? elevated. For example, this allows to implement new battery models and new ways to calculate battery parameters, which are not based on an instantaneous measurement, but on a time series of multiple signals.

Naturally, the basic principles of the invention remaining the same, the details of construction and the embodiments can vary, even appreciably, with respect to how much? been described and illustrated here, purely as an example, without going out with what? from the scope of the present invention, as defined by the following claims.

Claims (11)

1. Processing system (44a) configured to monitor the cell voltages of a given number (n) of cells (C1,1..C1,n) of a rechargeable battery (30), wherein said processing system (44a ) comprehends: - terminals configured to be connected to said cells in order to receive said cell voltages; - at least one analog-to-digital converter (448) configured to generate digital samples of said cell voltages, each digital sample having a given number of bits (NADC); - a transmission queue (452); - a digital processing circuit (444a) comprising a data compression module (450), wherein said digital processing circuit (444a) ? configured to carry out the following phases for a plurality? of times: - synchronously acquiring (1004-1008) a given number (k) of digital samples (S1,1..Sn,k) of each of said given number (n) of cell voltages and storing said acquired digital samples (S1 ,1..Sn,k) in a memory (DATA), - encoding (1010) said given number (k) of digital samples (S1,1..Sn,k) of said given number (n) of cell voltages stored in said memory (DATA) by means of said data compression module ( 450), generating with what? encrypted data, e - storing (1012) said encoded data in said transmission queue (452); And - a serial communication interface (440) configured to sequentially transmit the stored data to said transmission queue (452), whereby said serial communication interface (440) ? adapted to transmit the memorized data to said transmission queue (452), while said digital processing circuit (444a) acquires a new digital sample (S1,1..Sn,k); wherein said data compression modulus (450) ? configured to generate said encoded data by means of a dynamic range reduction operation (2004) comprising: - subtracting a given offset (OFF) from each of said given number (k) of digital samples (S1,1..Sn,k) of said given number (n) of cell voltages, thereby generating? indicative values of the dynamic variation of each sample with respect to said offset (OFF), e - remove a given number of bits pi? significant by each of said indicative values of the dynamic variation of each sample with respect to said offset (OFF); wherein said digital processing circuit (444a) ? configured to receive said offset data (OFF) via said serial communication interface (440). The processing system (44a) according to claim 1, wherein said digital processing circuit (444a) is configured to receive said given number of bits pi? significant through said serial communication interface (440). The processing system (44a) according to Claim 1 or Claim 2, wherein said data compression module (450) is? configured to generate said encrypted data: - removing a given number of least significant bits from each of said indicative values of the dynamic variation of each sample with respect to said offset (OFF); wherein said digital processing circuit (444a) ? preferably configured to receive said given number of least significant bits via said serial communication interface (440). The processing system (44a) according to any one of the preceding claims, wherein said data compression module (450) is configured for: - determining (2002) whether each of said given number (k) of digital samples (S1,1..Sn,k) of said given number (n) of cell voltages ? between a minimum and a maximum threshold, - in the event that one or more? of said digital samples (S1,1..Sn,k) is not between said minimum threshold and said maximum threshold (2006): a) store the value of said one or more? of said digital samples (S1,1..Sn,k) which are not between said minimum threshold and said maximum threshold, b) store data in said encoded data which identifies which one or more? of said digital samples (S1,1..Sn,k) are not between said minimum threshold and said maximum threshold, c) receiving a retransmission request via said serial communication interface (440), e d) in response to said retransmission request, transmitting via said serial communication interface (440) at least one of said values of said one or more? of said digital samples (S1,1..Sn,k) which are not between said minimum threshold and said maximum threshold. The processing system (44a) according to any one of the preceding claims, wherein said data compression module (450) is configured to support a plurality? of mode? encoding, wherein said data compression module (450) ? configured to generate said data encoded according to a mode? of selected coding, and in which said digital processing circuit (444a) is configured to receive this mode? code selected by means of said serial communication interface (440). 6. Processing system (44a) according to Claim 5, in which said modalities? of coding include, in addition to said reduction of the dynamic range, at least one of: - a mode? of delta coding, in which said data compression module (450) ? configured to generate delta coded values of said digital samples (S1,1..Sn,k) with respect to one or more? reference values; And - a mode? a Discrete Fourier Transform in 2D, in which said data compression modulus (450) ? configured to apply a mode? a Discrete Fourier Transform in 2D at said given number (k) of digital samples (S1,1..Sn,k) of said given number (n) of cell voltages. The processing system (44a) according to claim 6, wherein said data compression module (450) is configured to generate (2024) said delta coded values of a given cell voltage with at least one of: - selecting the first of said given number (k) of digital samples (S1,1..Sn,k) of the given cell voltage as a reference value, and generating said delta coded values by calculating the difference between each of the following digital samples (S1,1..Sn,k) of the given cell voltage with respect to the reference value; or - selecting the first of said given number (k) of digital samples (S1,1..Sn,k) of the given cell voltage as a reference value, and generating said delta coded values by calculating the difference between the following digital samples ( S1,1..Sn,k) of the given cell voltage versus a previous digital sample (S1,1..Sn,k) of the given cell voltage; or - determining the values of a reference curve as a function of said digital samples (S1,1..Sn,k), and generating said delta coded values by calculating the difference between each digital sample (S1,1..Sn,k) of the given cell voltage with respect to said values of said reference curve. The processing system (44a) according to claim 6 or claim 7, wherein said data compression module (450) is? configured to receive data identifying a value format and generate said delta encoded values as a function of said data identifying said value format: - coding said delta coded values with a linear value coding, or - encoding said delta encoded values with a mantissa and an exponent. 9. Processing system (44a) according to any one of the preceding claims, wherein said processing system (44a) comprises: - a further transmission queue (454); - a further serial communication interface (442) configured to sequentially receive data and to store said received data in said further transmission queue (454); And - a multiplexer (456) configured to connect said serial communication interface (440) to said transmission queue (452) or to said further transmission queue (454), whereby said serial communication interface (440) ? configured to sequentially transmit the stored data to said transmission queue (452) or to said further transmission queue (454). 10. A battery monitoring system comprising: - two terminals (400, 402) configured to be connected to a rechargeable battery (30); - a plurality? processing systems (44a) according to any one of the preceding claims; and - a further processing system (42) configured to receive said encoded data from said plurality? of processing systems (44a). An electric vehicle including a rechargeable battery and a battery monitoring system according to claim 10.