IT1406955B1 - Metodo per aumentare l'efficienza di scrittura in nanodispositivi mram - Google Patents

Metodo per aumentare l'efficienza di scrittura in nanodispositivi mram

Info

Publication number
IT1406955B1
IT1406955B1 ITTR2011A000001A ITTR20110001A IT1406955B1 IT 1406955 B1 IT1406955 B1 IT 1406955B1 IT TR2011A000001 A ITTR2011A000001 A IT TR2011A000001A IT TR20110001 A ITTR20110001 A IT TR20110001A IT 1406955 B1 IT1406955 B1 IT 1406955B1
Authority
IT
Italy
Prior art keywords
nanodispositives
mram
increase
writing efficiency
writing
Prior art date
Application number
ITTR2011A000001A
Other languages
English (en)
Inventor
Marco Ricci
Pietro Burrascano
Mario Carpentieri
Original Assignee
Ricci
Burrascano
Carpentieri
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricci, Burrascano, Carpentieri filed Critical Ricci
Priority to ITTR2011A000001A priority Critical patent/IT1406955B1/it
Publication of ITTR20110001A1 publication Critical patent/ITTR20110001A1/it
Application granted granted Critical
Publication of IT1406955B1 publication Critical patent/IT1406955B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
ITTR2011A000001A 2011-02-21 2011-02-21 Metodo per aumentare l'efficienza di scrittura in nanodispositivi mram IT1406955B1 (it)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ITTR2011A000001A IT1406955B1 (it) 2011-02-21 2011-02-21 Metodo per aumentare l'efficienza di scrittura in nanodispositivi mram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITTR2011A000001A IT1406955B1 (it) 2011-02-21 2011-02-21 Metodo per aumentare l'efficienza di scrittura in nanodispositivi mram

Publications (2)

Publication Number Publication Date
ITTR20110001A1 ITTR20110001A1 (it) 2012-08-22
IT1406955B1 true IT1406955B1 (it) 2014-03-14

Family

ID=43976502

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTR2011A000001A IT1406955B1 (it) 2011-02-21 2011-02-21 Metodo per aumentare l'efficienza di scrittura in nanodispositivi mram

Country Status (1)

Country Link
IT (1) IT1406955B1 (it)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007132458A2 (en) * 2006-05-12 2007-11-22 Anobit Technologies Ltd. Memory device programming using combined shaping and linear spreading
US7936592B2 (en) * 2009-02-03 2011-05-03 Seagate Technology Llc Non-volatile memory cell with precessional switching
JP5166322B2 (ja) * 2009-03-03 2013-03-21 株式会社東芝 磁気ランダムアクセスメモリ

Also Published As

Publication number Publication date
ITTR20110001A1 (it) 2012-08-22

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